mirror of https://gitee.com/openkylin/linux.git
[PATCH] dvb: frontend: tda1004x update
o added config options for IF frequency and AGC o support DSP boot from on board eeprom o added pll sleep call Signed-off-by: Hartmut Hackmann <hartmut.hackmann@t-online.de> Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Hartmut Hackmann
Linus Torvalds
parent
bbf24cec93
commit
ecb60deb9d
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@ -49,10 +49,8 @@ struct tda1004x_state {
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/* private demod data */
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u8 initialised;
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enum tda1004x_demod demod_type;
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u8 fw_version;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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@ -315,20 +313,35 @@ static int tda1004x_do_upload(struct tda1004x_state *state,
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memcpy(buf + 1, mem + pos, tx_size);
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fw_msg.len = tx_size + 1;
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if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
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printk("tda1004x: Error during firmware upload\n");
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printk(KERN_ERR "tda1004x: Error during firmware upload\n");
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return -EIO;
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}
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pos += tx_size;
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dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
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}
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// give the DSP a chance to settle 03/10/05 Hac
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msleep(100);
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return 0;
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}
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static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
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static int tda1004x_check_upload_ok(struct tda1004x_state *state)
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{
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u8 data1, data2;
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unsigned long timeout;
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if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
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timeout = jiffies + 2 * HZ;
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while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
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if (time_after(jiffies, timeout)) {
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printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
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break;
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}
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msleep(1);
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}
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} else
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msleep(100);
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// check upload was OK
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tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
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@ -336,9 +349,11 @@ static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
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data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
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data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
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if ((data1 != 0x67) || (data2 != dspVersion))
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if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2a) {
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printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
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return -EIO;
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}
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printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
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return 0;
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}
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@ -349,14 +364,14 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
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const struct firmware *fw;
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/* don't re-upload unless necessary */
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if (tda1004x_check_upload_ok(state, 0x2c) == 0)
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if (tda1004x_check_upload_ok(state) == 0)
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return 0;
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/* request the firmware, this will block until someone uploads it */
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printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
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printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
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ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
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if (ret) {
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printk("tda1004x: no firmware upload (timeout or file not found?)\n");
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printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
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return ret;
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}
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@ -372,93 +387,81 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
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ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
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if (ret)
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return ret;
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printk("tda1004x: firmware upload complete\n");
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printk(KERN_INFO "tda1004x: firmware upload complete\n");
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/* wait for DSP to initialise */
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/* DSPREADY doesn't seem to work on the TDA10045H */
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msleep(100);
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return tda1004x_check_upload_ok(state, 0x2c);
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return tda1004x_check_upload_ok(state);
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}
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static int tda10046_get_fw_version(struct tda1004x_state *state,
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const struct firmware *fw)
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static void tda10046_init_plls(struct dvb_frontend* fe)
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{
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const unsigned char pattern[] = { 0x67, 0x00, 0x50, 0x62, 0x5e, 0x18, 0x67 };
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unsigned int i;
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struct tda1004x_state* state = fe->demodulator_priv;
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/* area guessed from firmware v20, v21 and v25 */
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for (i = 0x660; i < 0x700; i++) {
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if (!memcmp(&fw->data[i], pattern, sizeof(pattern))) {
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state->fw_version = fw->data[i + sizeof(pattern)];
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printk(KERN_INFO "tda1004x: using firmware v%02x\n",
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state->fw_version);
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return 0;
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}
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tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
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if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
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dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
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} else {
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dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
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}
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return -EINVAL;
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
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switch (state->config->if_freq) {
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case TDA10046_FREQ_3617:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
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break;
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case TDA10046_FREQ_3613:
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
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break;
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}
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tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
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}
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static int tda10046_fwupload(struct dvb_frontend* fe)
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{
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struct tda1004x_state* state = fe->demodulator_priv;
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unsigned long timeout;
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int ret;
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const struct firmware *fw;
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/* reset + wake up chip */
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tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0);
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tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
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tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
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msleep(100);
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/* let the clocks recover from sleep */
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msleep(5);
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/* don't re-upload unless necessary */
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if (tda1004x_check_upload_ok(state, state->fw_version) == 0)
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if (tda1004x_check_upload_ok(state) == 0)
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return 0;
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/* request the firmware, this will block until someone uploads it */
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printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10046_DEFAULT_FIRMWARE);
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ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
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if (ret) {
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printk("tda1004x: no firmware upload (timeout or file not found?)\n");
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return ret;
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}
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if (fw->size < 24478) { /* size of firmware v20, which is the smallest of v20, v21 and v25 */
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printk("tda1004x: firmware file seems to be too small (%d bytes)\n", fw->size);
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return -EINVAL;
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}
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ret = tda10046_get_fw_version(state, fw);
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if (ret < 0) {
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printk("tda1004x: unable to find firmware version\n");
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return ret;
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}
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/* set parameters */
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10);
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c);
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
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tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
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tda10046_init_plls(fe);
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ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
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if (ret)
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return ret;
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printk("tda1004x: firmware upload complete\n");
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/* wait for DSP to initialise */
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timeout = jiffies + HZ;
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while (!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
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if (time_after(jiffies, timeout)) {
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printk("tda1004x: DSP failed to initialised.\n");
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return -EIO;
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if (state->config->request_firmware != NULL) {
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/* request the firmware, this will block until someone uploads it */
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printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
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ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
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if (ret) {
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printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
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return ret;
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}
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msleep(1);
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tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
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ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
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if (ret)
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return ret;
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} else {
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/* boot from firmware eeprom */
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/* Hac Note: we might need to do some GPIO Magic here */
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printk(KERN_INFO "tda1004x: booting from eeprom\n");
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tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
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msleep(300);
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}
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return tda1004x_check_upload_ok(state, state->fw_version);
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return tda1004x_check_upload_ok(state);
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}
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static int tda1004x_encode_fec(int fec)
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@ -560,12 +563,10 @@ static int tda10046_init(struct dvb_frontend* fe)
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if (tda10046_fwupload(fe)) {
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printk("tda1004x: firmware upload failed\n");
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return -EIO;
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return -EIO;
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}
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tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip
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// Init the PLL
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// Init the tuner PLL
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if (state->config->pll_init) {
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tda1004x_enable_tuner_i2c(state);
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state->config->pll_init(fe);
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@ -574,32 +575,34 @@ static int tda10046_init(struct dvb_frontend* fe)
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// tda setup
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tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
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tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);
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tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
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tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
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tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
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tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); // PLL P = N = 0
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tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
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tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup
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tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
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tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream
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tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer
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tda10046_init_plls(fe);
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switch (state->config->agc_config) {
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case TDA10046_AGC_DEFAULT:
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tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
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tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
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break;
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case TDA10046_AGC_IFO_AUTO_NEG:
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tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
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tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
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break;
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}
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tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
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tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
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tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
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tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
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tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
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tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
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tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
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tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
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tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
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tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
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tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
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tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
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tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
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tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
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tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
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tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
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tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
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tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
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tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select
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state->initialised = 1;
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return 0;
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@ -629,9 +632,6 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
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state->config->pll_set(fe, fe_params);
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tda1004x_disable_tuner_i2c(state);
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if (state->demod_type == TDA1004X_DEMOD_TDA10046)
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tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
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// Hardcoded to use auto as much as possible on the TDA10045 as it
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// is very unreliable if AUTO mode is _not_ used.
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if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
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@ -1090,6 +1090,8 @@ static int tda1004x_sleep(struct dvb_frontend* fe)
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case TDA1004X_DEMOD_TDA10046:
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tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
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if (state->config->pll_sleep != NULL)
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state->config->pll_sleep(fe);
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break;
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}
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state->initialised = 0;
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@ -1216,7 +1218,6 @@ struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
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memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
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state->initialised = 0;
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state->demod_type = TDA1004X_DEMOD_TDA10046;
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state->fw_version = 0x20; /* dummy default value */
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/* check if the demod is there */
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if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
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@ -26,6 +26,21 @@
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#include <linux/dvb/frontend.h>
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#include <linux/firmware.h>
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enum tda10046_xtal {
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TDA10046_XTAL_4M,
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TDA10046_XTAL_16M,
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};
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enum tda10046_agc {
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TDA10046_AGC_DEFAULT, /* original configuration */
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TDA10046_AGC_IFO_AUTO_NEG, /* IF AGC only, automatic, negtive */
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};
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enum tda10046_if {
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TDA10046_FREQ_3617, /* original config, 36,166 MHZ */
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TDA10046_FREQ_3613, /* 36,13 MHZ */
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};
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struct tda1004x_config
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{
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/* the demodulator's i2c address */
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@ -37,14 +52,22 @@ struct tda1004x_config
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/* Does the OCLK signal need inverted? */
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u8 invert_oclk;
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/* value of N_I2C of the CONF_PLL3 register */
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u8 n_i2c;
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/* Xtal frequency, 4 or 16MHz*/
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enum tda10046_xtal xtal_freq;
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/* IF frequency */
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||||
enum tda10046_if if_freq;
|
||||
|
||||
/* AGC configuration */
|
||||
enum tda10046_agc agc_config;
|
||||
|
||||
/* PLL maintenance */
|
||||
int (*pll_init)(struct dvb_frontend* fe);
|
||||
void (*pll_sleep)(struct dvb_frontend* fe);
|
||||
int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params);
|
||||
|
||||
/* request firmware for device */
|
||||
/* set this to NULL if the card has a firmware EEPROM */
|
||||
int (*request_firmware)(struct dvb_frontend* fe, const struct firmware **fw, char* name);
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -695,8 +695,12 @@ static struct tda1004x_config philips_tu1216_config = {
|
|||
.demod_address = 0x8,
|
||||
.invert = 1,
|
||||
.invert_oclk = 1,
|
||||
.xtal_freq = TDA10046_XTAL_4M,
|
||||
.agc_config = TDA10046_AGC_DEFAULT,
|
||||
.if_freq = TDA10046_FREQ_3617,
|
||||
.pll_init = philips_tu1216_pll_init,
|
||||
.pll_set = philips_tu1216_pll_set,
|
||||
.pll_sleep = NULL,
|
||||
.request_firmware = philips_tu1216_request_firmware,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -838,8 +838,12 @@ static struct tda1004x_config philips_tdm1316l_config = {
|
|||
.demod_address = 0x8,
|
||||
.invert = 0,
|
||||
.invert_oclk = 0,
|
||||
.xtal_freq = TDA10046_XTAL_4M,
|
||||
.agc_config = TDA10046_AGC_DEFAULT,
|
||||
.if_freq = TDA10046_FREQ_3617,
|
||||
.pll_init = philips_tdm1316l_pll_init,
|
||||
.pll_set = philips_tdm1316l_pll_set,
|
||||
.pll_sleep = NULL,
|
||||
.request_firmware = philips_tdm1316l_request_firmware,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue