mirror of https://gitee.com/openkylin/linux.git
[SPARC64]: SUN4V memory exception trap handlers.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
618e9ed98a
commit
ed6b0b4543
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@ -237,6 +237,167 @@ sun4v_tsb_miss_common:
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ba,pt %xcc, tsb_miss_page_table_walk
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add %g1, %g2, %g1
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/* Instruction Access Exception, tl0. */
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sun4v_iacc:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Instruction Access Exception, tl1. */
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sun4v_iacc_tl1:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Data Access Exception, tl0. */
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sun4v_dacc:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Data Access Exception, tl1. */
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sun4v_dacc_tl1:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Memory Address Unaligned. */
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sun4v_mna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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/* Window fixup? */
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rdpr %tl, %g2
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cmp %g2, 1
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bgu,pn %icc, winfix_mna
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rdpr %tpc, %g3
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_mna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Privileged Action. */
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sun4v_privact:
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_privact
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Unaligned ldd float, tl0. */
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sun4v_lddfmna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call handle_lddfmna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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/* Unaligned std float, tl0. */
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sun4v_stdfmna:
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mov SCRATCHPAD_CPUID, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g3
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sethi %hi(trap_block), %g2
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or %g2, %lo(trap_block), %g2
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sllx %g3, TRAP_BLOCK_SZ_SHIFT, %g3
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add %g2, %g3, %g2
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + TRAP_PER_CPU_FAULT_INFO + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call handle_stdfmna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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#define BRANCH_ALWAYS 0x10680000
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#define NOP 0x01000000
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@ -265,6 +426,15 @@ sun4v_patch_tlb_handlers:
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SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
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SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
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SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
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SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
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SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
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SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
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SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
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SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
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SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
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SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
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SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
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SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
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retl
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nop
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.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
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@ -180,6 +180,45 @@ void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr
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spitfire_insn_access_exception(regs, sfsr, sfar);
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}
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void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
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{
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unsigned short type = (type_ctx >> 16);
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unsigned short ctx = (type_ctx & 0xffff);
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siginfo_t info;
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if (notify_die(DIE_TRAP, "instruction access exception", regs,
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0, 0x8, SIGTRAP) == NOTIFY_STOP)
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return;
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if (regs->tstate & TSTATE_PRIV) {
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printk("sun4v_insn_access_exception: ADDR[%016lx] "
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"CTX[%04x] TYPE[%04x], going.\n",
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addr, ctx, type);
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die_if_kernel("Iax", regs);
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}
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if (test_thread_flag(TIF_32BIT)) {
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regs->tpc &= 0xffffffff;
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regs->tnpc &= 0xffffffff;
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}
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info.si_signo = SIGSEGV;
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info.si_errno = 0;
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info.si_code = SEGV_MAPERR;
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info.si_addr = (void __user *) addr;
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info.si_trapno = 0;
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force_sig_info(SIGSEGV, &info, current);
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}
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void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
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{
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if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
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0, 0x8, SIGTRAP) == NOTIFY_STOP)
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return;
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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sun4v_insn_access_exception(regs, addr, type_ctx);
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}
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void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
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{
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siginfo_t info;
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@ -228,6 +267,45 @@ void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr
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spitfire_data_access_exception(regs, sfsr, sfar);
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}
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void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
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{
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unsigned short type = (type_ctx >> 16);
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unsigned short ctx = (type_ctx & 0xffff);
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siginfo_t info;
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if (notify_die(DIE_TRAP, "data access exception", regs,
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0, 0x8, SIGTRAP) == NOTIFY_STOP)
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return;
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if (regs->tstate & TSTATE_PRIV) {
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printk("sun4v_data_access_exception: ADDR[%016lx] "
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"CTX[%04x] TYPE[%04x], going.\n",
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addr, ctx, type);
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die_if_kernel("Iax", regs);
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}
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if (test_thread_flag(TIF_32BIT)) {
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regs->tpc &= 0xffffffff;
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regs->tnpc &= 0xffffffff;
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}
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info.si_signo = SIGSEGV;
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info.si_errno = 0;
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info.si_code = SEGV_MAPERR;
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info.si_addr = (void __user *) addr;
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info.si_trapno = 0;
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force_sig_info(SIGSEGV, &info, current);
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}
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void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
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{
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if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
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0, 0x8, SIGTRAP) == NOTIFY_STOP)
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return;
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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sun4v_data_access_exception(regs, addr, type_ctx);
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}
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#ifdef CONFIG_PCI
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/* This is really pathetic... */
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extern volatile int pci_poke_in_progress;
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@ -2150,6 +2228,8 @@ void do_illegal_instruction(struct pt_regs *regs)
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force_sig_info(SIGILL, &info, current);
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}
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extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
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void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
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{
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siginfo_t info;
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@ -2159,13 +2239,7 @@ void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned lo
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return;
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if (regs->tstate & TSTATE_PRIV) {
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extern void kernel_unaligned_trap(struct pt_regs *regs,
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unsigned int insn,
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unsigned long sfar,
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unsigned long sfsr);
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kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc),
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sfar, sfsr);
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kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
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return;
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}
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info.si_signo = SIGBUS;
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@ -2176,6 +2250,26 @@ void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned lo
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force_sig_info(SIGBUS, &info, current);
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}
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void sun4v_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
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{
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siginfo_t info;
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if (notify_die(DIE_TRAP, "memory address unaligned", regs,
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0, 0x34, SIGSEGV) == NOTIFY_STOP)
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return;
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if (regs->tstate & TSTATE_PRIV) {
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kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
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return;
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}
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info.si_signo = SIGBUS;
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info.si_errno = 0;
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info.si_code = BUS_ADRALN;
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info.si_addr = (void __user *) addr;
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info.si_trapno = 0;
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force_sig_info(SIGBUS, &info, current);
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}
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void do_privop(struct pt_regs *regs)
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{
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siginfo_t info;
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@ -277,7 +277,7 @@ static void kernel_mna_trap_fault(void)
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regs->tstate |= (ASI_AIUS << 24UL);
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}
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asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn, unsigned long sfar, unsigned long sfsr)
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asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
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{
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enum direction dir = decode_direction(insn);
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int size = decode_access_size(insn);
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@ -405,6 +405,9 @@ extern void do_privact(struct pt_regs *regs);
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extern void spitfire_data_access_exception(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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extern void sun4v_data_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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{
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@ -447,6 +450,9 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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break;
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}
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default:
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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@ -454,6 +460,9 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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__put_user ((u32)first, (u32 __user *)(addr + 4)) ||
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__put_user (second >> 32, (u32 __user *)(addr + 8)) ||
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__put_user ((u32)second, (u32 __user *)(addr + 12))) {
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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@ -467,6 +476,9 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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do_privact(regs);
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return 1;
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} else if (asi > ASI_SNFL) {
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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@ -484,6 +496,9 @@ int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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err |= __get_user (data[i], (u32 __user *)(addr + 4*i));
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}
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||||
if (err && !(asi & 0x2 /* NF */)) {
|
||||
if (tlb_type == hypervisor)
|
||||
sun4v_data_access_exception(regs, addr, 0);
|
||||
else
|
||||
spitfire_data_access_exception(regs, 0, addr);
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -548,7 +563,7 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
u32 insn;
|
||||
u32 first, second;
|
||||
u64 value;
|
||||
u8 asi, freg;
|
||||
u8 freg;
|
||||
int flag;
|
||||
struct fpustate *f = FPUSTATE;
|
||||
|
||||
|
|
@ -557,7 +572,7 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
if (test_thread_flag(TIF_32BIT))
|
||||
pc = (u32)pc;
|
||||
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
||||
asi = sfsr >> 16;
|
||||
int asi = decode_asi(insn, regs);
|
||||
if ((asi > ASI_SNFL) ||
|
||||
(asi < ASI_P))
|
||||
goto daex;
|
||||
|
|
@ -587,7 +602,11 @@ void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
*(u64 *)(f->regs + freg) = value;
|
||||
current_thread_info()->fpsaved[0] |= flag;
|
||||
} else {
|
||||
daex: spitfire_data_access_exception(regs, sfsr, sfar);
|
||||
daex:
|
||||
if (tlb_type == hypervisor)
|
||||
sun4v_data_access_exception(regs, sfar, sfsr);
|
||||
else
|
||||
spitfire_data_access_exception(regs, sfsr, sfar);
|
||||
return;
|
||||
}
|
||||
advance(regs);
|
||||
|
|
@ -600,7 +619,7 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
unsigned long tstate = regs->tstate;
|
||||
u32 insn;
|
||||
u64 value;
|
||||
u8 asi, freg;
|
||||
u8 freg;
|
||||
int flag;
|
||||
struct fpustate *f = FPUSTATE;
|
||||
|
||||
|
|
@ -609,8 +628,8 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
if (test_thread_flag(TIF_32BIT))
|
||||
pc = (u32)pc;
|
||||
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
||||
int asi = decode_asi(insn, regs);
|
||||
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
||||
asi = sfsr >> 16;
|
||||
value = 0;
|
||||
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
||||
if ((asi > ASI_SNFL) ||
|
||||
|
|
@ -631,7 +650,11 @@ void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr
|
|||
__put_user ((u32)value, (u32 __user *)(sfar + 4)))
|
||||
goto daex;
|
||||
} else {
|
||||
daex: spitfire_data_access_exception(regs, sfsr, sfar);
|
||||
daex:
|
||||
if (tlb_type == hypervisor)
|
||||
sun4v_data_access_exception(regs, sfar, sfsr);
|
||||
else
|
||||
spitfire_data_access_exception(regs, sfsr, sfar);
|
||||
return;
|
||||
}
|
||||
advance(regs);
|
||||
|
|
|
|||
|
|
@ -109,16 +109,23 @@ winfix_mna:
|
|||
done
|
||||
|
||||
fill_fixup_mna:
|
||||
TRAP_LOAD_THREAD_REG(%g6, %g1)
|
||||
rdpr %tstate, %g1
|
||||
and %g1, TSTATE_CWP, %g1
|
||||
wrpr %g1, %cwp
|
||||
ba,pt %xcc, etrap
|
||||
rd %pc, %g7
|
||||
mov %l4, %o2
|
||||
mov %l5, %o1
|
||||
call mem_address_unaligned
|
||||
sethi %hi(tlb_type), %g1
|
||||
mov %l4, %o1
|
||||
lduw [%g1 + %lo(tlb_type)], %g1
|
||||
mov %l5, %o2
|
||||
cmp %g1, 3
|
||||
bne,pt %icc, 1f
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
call sun4v_mna
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap_clr_l6
|
||||
1: call mem_address_unaligned
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap_clr_l6
|
||||
|
||||
winfix_dax:
|
||||
|
|
@ -128,14 +135,21 @@ winfix_dax:
|
|||
done
|
||||
|
||||
fill_fixup_dax:
|
||||
TRAP_LOAD_THREAD_REG(%g6, %g1)
|
||||
rdpr %tstate, %g1
|
||||
and %g1, TSTATE_CWP, %g1
|
||||
wrpr %g1, %cwp
|
||||
ba,pt %xcc, etrap
|
||||
rd %pc, %g7
|
||||
sethi %hi(tlb_type), %g1
|
||||
mov %l4, %o1
|
||||
lduw [%g1 + %lo(tlb_type)], %g1
|
||||
mov %l5, %o2
|
||||
call spitfire_data_access_exception
|
||||
cmp %g1, 3
|
||||
bne,pt %icc, 1f
|
||||
add %sp, PTREGS_OFF, %o0
|
||||
call sun4v_data_access_exception
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap_clr_l6
|
||||
1: call spitfire_data_access_exception
|
||||
nop
|
||||
ba,a,pt %xcc, rtrap_clr_l6
|
||||
|
|
|
|||
Loading…
Reference in New Issue