mirror of https://gitee.com/openkylin/linux.git
NTB: NTB-RP support
Add support for Non-Transparent Bridge connected to a PCI-E Root Port on the remote system (also known as NTB-RP mode). This allows for a NTB enabled system to be connected to a non-NTB enabled system/slot. Modifications to the registers and BARs/MWs on the Secondary side by the remote system are reflected into registers on the Primary side for the local system. Similarly, modifications of registers and BARs/MWs on Primary side by the local system are reflected into registers on the Secondary side for the Remote System. This allows communication between the 2 sides via these registers and BARs/MWs. Note: there is not a fix for the Xeon Errata (that was already worked around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP will not work on the Secondary side with the Xeon Errata workaround enabled. To get around this, disable the workaround via the xeon_errata_workaround=0 modparm. However, this can cause the hang described in the errata. Signed-off-by: Jon Mason <jon.mason@intel.com>
This commit is contained in:
Jon Mason
parent
497938890a
commit
ed6c24eda9
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@ -69,7 +69,7 @@ module_param(xeon_errata_workaround, bool, 0644);
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MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
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enum {
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NTB_CONN_CLASSIC = 0,
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NTB_CONN_TRANSPARENT = 0,
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NTB_CONN_B2B,
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NTB_CONN_RP,
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};
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@ -509,7 +509,8 @@ static void ntb_link_event(struct ntb_device *ndev, int link_state)
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ndev->link_status = NTB_LINK_UP;
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event = NTB_EVENT_HW_LINK_UP;
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if (ndev->hw_type == BWD_HW)
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if (ndev->hw_type == BWD_HW ||
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ndev->conn_type == NTB_CONN_TRANSPARENT)
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status = readw(ndev->reg_ofs.lnk_stat);
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else {
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int rc = pci_read_config_word(ndev->pdev,
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@ -649,119 +650,174 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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if (rc)
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return rc;
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switch (val & SNB_PPD_CONN_TYPE) {
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case NTB_CONN_B2B:
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ndev->conn_type = NTB_CONN_B2B;
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break;
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case NTB_CONN_CLASSIC:
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case NTB_CONN_RP:
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default:
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dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
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return -EINVAL;
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}
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if (val & SNB_PPD_DEV_TYPE)
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ndev->dev_type = NTB_DEV_USD;
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else
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ndev->dev_type = NTB_DEV_DSD;
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ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
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ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
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switch (val & SNB_PPD_CONN_TYPE) {
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case NTB_CONN_B2B:
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dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
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ndev->conn_type = NTB_CONN_B2B;
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ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
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ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
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ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
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/* There is a Xeon hardware errata related to writes to
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* SDOORBELL or B2BDOORBELL in conjunction with inbound access
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* to NTB MMIO Space, which may hang the system. To workaround
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* this use the second memory window to access the interrupt and
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* scratch pad registers on the remote system.
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*/
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if (xeon_errata_workaround) {
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if (!ndev->mw[1].bar_sz)
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return -EINVAL;
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ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
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ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
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SNB_SPAD_OFFSET;
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ndev->reg_ofs.rdb = ndev->mw[1].vbase +
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SNB_PDOORBELL_OFFSET;
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/* Set the Limit register to 4k, the minimum size, to
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* prevent an illegal access
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*/
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writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
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SNB_PBAR4LMT_OFFSET);
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} else {
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ndev->limits.max_mw = SNB_MAX_MW;
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ndev->reg_ofs.spad_write = ndev->reg_base +
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SNB_B2B_SPAD_OFFSET;
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ndev->reg_ofs.rdb = ndev->reg_base +
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SNB_B2B_DOORBELL_OFFSET;
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/* Disable the Limit register, just incase it is set to
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* something silly
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*/
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writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
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}
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/* The Xeon errata workaround requires setting SBAR Base
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* addresses to known values, so that the PBAR XLAT can be
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* pointed at SBAR0 of the remote system.
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*/
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if (ndev->dev_type == NTB_DEV_USD) {
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writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
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SNB_PBAR2XLAT_OFFSET);
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if (xeon_errata_workaround)
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writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
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writel(SNB_MBAR01_DSD_ADDR >> 32,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
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}
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writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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} else {
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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SNB_PBAR2XLAT_OFFSET);
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if (xeon_errata_workaround)
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writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
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writel(SNB_MBAR01_USD_ADDR >> 32,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
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}
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writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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}
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break;
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case NTB_CONN_RP:
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dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
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ndev->conn_type = NTB_CONN_RP;
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if (xeon_errata_workaround) {
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dev_err(&ndev->pdev->dev,
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"NTB-RP disabled due to hardware errata. To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
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return -EINVAL;
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}
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/* Scratch pads need to have exclusive access from the primary
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* or secondary side. Halve the num spads so that each side can
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* have an equal amount.
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*/
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ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
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/* Note: The SDOORBELL is the cause of the errata. You REALLY
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* don't want to touch it.
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*/
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ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
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ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
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ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
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/* Offset the start of the spads to correspond to whether it is
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* primary or secondary
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*/
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ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
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ndev->limits.max_spads * 4;
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
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ndev->limits.max_mw = SNB_MAX_MW;
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break;
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case NTB_CONN_TRANSPARENT:
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dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
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ndev->conn_type = NTB_CONN_TRANSPARENT;
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/* Scratch pads need to have exclusive access from the primary
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* or secondary side. Halve the num spads so that each side can
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* have an equal amount.
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*/
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ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
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ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
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ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
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ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
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ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
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/* Offset the start of the spads to correspond to whether it is
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* primary or secondary
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*/
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
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ndev->limits.max_spads * 4;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
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ndev->limits.max_mw = SNB_MAX_MW;
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break;
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default:
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/* Most likely caused by the remote NTB-RP device not being
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* configured
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*/
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dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
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return -EINVAL;
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}
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ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
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ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_LINK_STATUS_OFFSET;
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
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ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
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ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
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/* There is a Xeon hardware errata related to writes to
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* SDOORBELL or B2BDOORBELL in conjunction with inbound access
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* to NTB MMIO Space, which may hang the system. To workaround
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* this use the second memory window to access the interrupt and
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* scratch pad registers on the remote system.
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*/
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if (xeon_errata_workaround) {
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if (!ndev->mw[1].bar_sz)
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return -EINVAL;
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ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
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ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
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SNB_SPAD_OFFSET;
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ndev->reg_ofs.rdb = ndev->mw[1].vbase +
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SNB_PDOORBELL_OFFSET;
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/* Set the Limit register to 4k, the minimum size, to
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* prevent an illegal access
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*/
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writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
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SNB_PBAR4LMT_OFFSET);
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} else {
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ndev->limits.max_mw = SNB_MAX_MW;
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ndev->reg_ofs.spad_write = ndev->reg_base +
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SNB_B2B_SPAD_OFFSET;
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ndev->reg_ofs.rdb = ndev->reg_base +
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SNB_B2B_DOORBELL_OFFSET;
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/* Disable the Limit register, just incase it is set to
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* something silly
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*/
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writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
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}
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/* The Xeon errata workaround requires setting SBAR Base
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* addresses to known values, so that the PBAR XLAT can be
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* pointed at SBAR0 of the remote system.
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*/
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if (ndev->dev_type == NTB_DEV_USD) {
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writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
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SNB_PBAR2XLAT_OFFSET);
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if (xeon_errata_workaround)
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writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
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writel(SNB_MBAR01_DSD_ADDR >> 32,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
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}
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writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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} else {
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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SNB_PBAR2XLAT_OFFSET);
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if (xeon_errata_workaround)
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writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
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writel(SNB_MBAR01_USD_ADDR >> 32,
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ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
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}
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writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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}
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ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
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ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
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ndev->limits.msix_cnt = SNB_MSIX_CNT;
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ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
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@ -865,8 +921,10 @@ static int ntb_device_setup(struct ntb_device *ndev)
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dev_info(&ndev->pdev->dev, "Device Type = %s\n",
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ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
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/* Enable Bus Master and Memory Space on the secondary side */
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writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, ndev->reg_ofs.spci_cmd);
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if (ndev->conn_type == NTB_CONN_B2B)
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/* Enable Bus Master and Memory Space on the secondary side */
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writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
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ndev->reg_ofs.spci_cmd);
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return 0;
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}
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@ -1360,7 +1418,7 @@ static void ntb_pci_remove(struct pci_dev *pdev)
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/* Bring NTB link down */
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ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
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ntb_cntl |= NTB_LINK_DISABLE;
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ntb_cntl |= NTB_CNTL_LINK_DISABLE;
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writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
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ntb_transport_free(ndev->ntb_transport);
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@ -46,8 +46,6 @@
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* Jon Mason <jon.mason@intel.com>
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*/
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#define NTB_LINK_ENABLE 0x0000
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#define NTB_LINK_DISABLE 0x0002
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#define NTB_LINK_STATUS_ACTIVE 0x2000
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#define NTB_LINK_SPEED_MASK 0x000f
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#define NTB_LINK_WIDTH_MASK 0x03f0
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@ -65,6 +63,7 @@
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#define SNB_PCICMD_OFFSET 0x0504
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#define SNB_DEVCTRL_OFFSET 0x0598
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#define SNB_SLINK_STATUS_OFFSET 0x05A2
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#define SNB_LINK_STATUS_OFFSET 0x01A2
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#define SNB_PBAR2LMT_OFFSET 0x0000
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@ -147,6 +146,8 @@
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#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
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#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
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#define NTB_CNTL_CFG_LOCK (1 << 0)
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#define NTB_CNTL_LINK_DISABLE (1 << 1)
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#define NTB_CNTL_BAR23_SNOOP (1 << 2)
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#define NTB_CNTL_BAR45_SNOOP (1 << 6)
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#define BWD_CNTL_LINK_DOWN (1 << 16)
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