mirror of https://gitee.com/openkylin/linux.git
usb: chipidea: add freescale imx28 special write register method
According to Freescale imx28 Errata, "ENGR119653 USB: ARM to USB register error issue", All USB register write operations must use the ARM SWP instruction. So, we implement special hw_write and hw_test_and_clear for imx28. Discussion for it at below: http://marc.info/?l=linux-usb&m=137996395529294&w=2 This patch is needed for stable tree 3.11+. Cc: stable@vger.kernel.org Cc: robert.hodaszi@digi.com Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Tested-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -164,6 +164,7 @@ struct hw_bank {
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* @id_event: indicates there is an id event, and handled at ci_otg_work
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* @b_sess_valid_event: indicates there is a vbus event, and handled
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* at ci_otg_work
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* @imx28_write_fix: Freescale imx28 needs swp instruction for writing
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*/
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struct ci_hdrc {
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struct device *dev;
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@ -202,6 +203,7 @@ struct ci_hdrc {
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struct dentry *debugfs;
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bool id_event;
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bool b_sess_valid_event;
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bool imx28_write_fix;
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};
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static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
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@ -250,6 +252,26 @@ static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
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return ioread32(ci->hw_bank.regmap[reg]) & mask;
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}
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#ifdef CONFIG_SOC_IMX28
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static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
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{
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__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
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}
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#else
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static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
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{
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}
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#endif
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static inline void __hw_write(struct ci_hdrc *ci, u32 val,
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void __iomem *addr)
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{
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if (ci->imx28_write_fix)
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imx28_ci_writel(val, addr);
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else
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iowrite32(val, addr);
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}
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/**
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* hw_write: writes to a hw register
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* @reg: register index
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@ -263,7 +285,7 @@ static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
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data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
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| (data & mask);
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iowrite32(data, ci->hw_bank.regmap[reg]);
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__hw_write(ci, data, ci->hw_bank.regmap[reg]);
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}
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/**
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@ -278,7 +300,7 @@ static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
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{
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u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
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iowrite32(val, ci->hw_bank.regmap[reg]);
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__hw_write(ci, val, ci->hw_bank.regmap[reg]);
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return val;
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}
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@ -548,6 +548,8 @@ static int ci_hdrc_probe(struct platform_device *pdev)
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ci->dev = dev;
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ci->platdata = dev->platform_data;
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ci->imx28_write_fix = !!(ci->platdata->flags &
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CI_HDRC_IMX28_WRITE_FIX);
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ret = hw_device_init(ci, base);
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if (ret < 0) {
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@ -65,6 +65,7 @@ static int host_start(struct ci_hdrc *ci)
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ehci->caps = ci->hw_bank.cap;
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ehci->has_hostpc = ci->hw_bank.lpm;
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ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
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ehci->imx28_write_fix = ci->imx28_write_fix;
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if (ci->platdata->reg_vbus) {
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ret = regulator_enable(ci->platdata->reg_vbus);
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@ -24,6 +24,7 @@ struct ci_hdrc_platform_data {
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* but otg is not supported (no register otgsc).
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*/
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#define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
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#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
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enum usb_dr_mode dr_mode;
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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