mirror of https://gitee.com/openkylin/linux.git
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/i915: Move legacy breadcrumb out of the reserved status page area drm/i915: Filter pci devices based on PCI_CLASS_DISPLAY_VGA drm/radeon: map registers at load time drm: Remove infrastructure for supporting i915's vblank swapping. i915: Remove racy delayed vblank swap ioctl. i915: Don't whine when pci_enable_msi() fails. i915: Don't attempt to short-circuit object_wait_rendering by checking domains. i915: Clean up sarea pointers on leavevt i915: Save/restore MCHBAR_RENDER_STANDBY on GM965/GM45
This commit is contained in:
Linus Torvalds
commit
eda1be631a
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@ -266,11 +266,19 @@ int drm_init(struct drm_driver *driver)
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for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) {
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pid = (struct pci_device_id *)&driver->pci_driver.id_table[i];
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/* Loop around setting up a DRM device for each PCI device
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* matching our ID and device class. If we had the internal
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* function that pci_get_subsys and pci_get_class used, we'd
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* be able to just pass pid in instead of doing a two-stage
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* thing.
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*/
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pdev = NULL;
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/* pass back in pdev to account for multiple identical cards */
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while ((pdev =
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pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
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pid->subdevice, pdev)) != NULL) {
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if ((pdev->class & pid->class_mask) != pid->class)
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continue;
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/* stealth mode requires a manual probe */
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pci_dev_get(pdev);
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drm_get_dev(pdev, pid, driver);
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@ -280,8 +280,6 @@ int drm_irq_uninstall(struct drm_device * dev)
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drm_vblank_cleanup(dev);
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dev->locked_tasklet_func = NULL;
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return 0;
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}
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EXPORT_SYMBOL(drm_irq_uninstall);
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@ -699,81 +697,3 @@ void drm_handle_vblank(struct drm_device *dev, int crtc)
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drm_vbl_send_signals(dev, crtc);
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}
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EXPORT_SYMBOL(drm_handle_vblank);
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/**
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* Tasklet wrapper function.
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*
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* \param data DRM device in disguise.
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*
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* Attempts to grab the HW lock and calls the driver callback on success. On
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* failure, leave the lock marked as contended so the callback can be called
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* from drm_unlock().
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*/
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static void drm_locked_tasklet_func(unsigned long data)
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{
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struct drm_device *dev = (struct drm_device *)data;
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unsigned long irqflags;
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void (*tasklet_func)(struct drm_device *);
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spin_lock_irqsave(&dev->tasklet_lock, irqflags);
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tasklet_func = dev->locked_tasklet_func;
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spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
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if (!tasklet_func ||
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!drm_lock_take(&dev->lock,
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DRM_KERNEL_CONTEXT)) {
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return;
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}
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dev->lock.lock_time = jiffies;
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atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
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spin_lock_irqsave(&dev->tasklet_lock, irqflags);
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tasklet_func = dev->locked_tasklet_func;
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dev->locked_tasklet_func = NULL;
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spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
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if (tasklet_func != NULL)
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tasklet_func(dev);
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drm_lock_free(&dev->lock,
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DRM_KERNEL_CONTEXT);
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}
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/**
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* Schedule a tasklet to call back a driver hook with the HW lock held.
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*
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* \param dev DRM device.
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* \param func Driver callback.
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*
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* This is intended for triggering actions that require the HW lock from an
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* interrupt handler. The lock will be grabbed ASAP after the interrupt handler
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* completes. Note that the callback may be called from interrupt or process
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* context, it must not make any assumptions about this. Also, the HW lock will
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* be held with the kernel context or any client context.
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*/
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void drm_locked_tasklet(struct drm_device *dev, void (*func)(struct drm_device *))
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{
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unsigned long irqflags;
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static DECLARE_TASKLET(drm_tasklet, drm_locked_tasklet_func, 0);
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if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ) ||
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test_bit(TASKLET_STATE_SCHED, &drm_tasklet.state))
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return;
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spin_lock_irqsave(&dev->tasklet_lock, irqflags);
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if (dev->locked_tasklet_func) {
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spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
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return;
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}
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dev->locked_tasklet_func = func;
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spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
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drm_tasklet.data = (unsigned long)dev;
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tasklet_hi_schedule(&drm_tasklet);
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}
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EXPORT_SYMBOL(drm_locked_tasklet);
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@ -154,8 +154,6 @@ int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
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int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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struct drm_lock *lock = data;
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unsigned long irqflags;
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void (*tasklet_func)(struct drm_device *);
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if (lock->context == DRM_KERNEL_CONTEXT) {
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DRM_ERROR("Process %d using kernel context %d\n",
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@ -163,13 +161,6 @@ int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
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return -EINVAL;
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}
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spin_lock_irqsave(&dev->tasklet_lock, irqflags);
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tasklet_func = dev->locked_tasklet_func;
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dev->locked_tasklet_func = NULL;
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spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
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if (tasklet_func != NULL)
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tasklet_func(dev);
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atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
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/* kernel_context_switch isn't used by any of the x86 drm
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@ -92,7 +92,6 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev,
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spin_lock_init(&dev->count_lock);
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spin_lock_init(&dev->drw_lock);
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spin_lock_init(&dev->tasklet_lock);
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spin_lock_init(&dev->lock.spinlock);
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init_timer(&dev->timer);
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mutex_init(&dev->struct_mutex);
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@ -154,6 +154,9 @@ static int i915_dma_cleanup(struct drm_device * dev)
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if (I915_NEED_GFX_HWS(dev))
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i915_free_hws(dev);
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dev_priv->sarea = NULL;
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dev_priv->sarea_priv = NULL;
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return 0;
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}
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@ -442,7 +445,7 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
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BEGIN_LP_RING(4);
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OUT_RING(MI_STORE_DWORD_INDEX);
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OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(dev_priv->counter);
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OUT_RING(0);
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ADVANCE_LP_RING();
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@ -573,7 +576,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
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BEGIN_LP_RING(4);
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OUT_RING(MI_STORE_DWORD_INDEX);
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OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(dev_priv->counter);
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OUT_RING(0);
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ADVANCE_LP_RING();
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@ -608,7 +611,6 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 *hw_status = dev_priv->hw_status_page;
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drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
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dev_priv->sarea_priv;
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drm_i915_batchbuffer_t *batch = data;
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@ -634,7 +636,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
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mutex_unlock(&dev->struct_mutex);
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if (sarea_priv)
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sarea_priv->last_dispatch = (int)hw_status[5];
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sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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return ret;
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}
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@ -642,7 +644,6 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 *hw_status = dev_priv->hw_status_page;
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drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
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dev_priv->sarea_priv;
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drm_i915_cmdbuffer_t *cmdbuf = data;
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@ -670,7 +671,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
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}
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if (sarea_priv)
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sarea_priv->last_dispatch = (int)hw_status[5];
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sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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return 0;
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}
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@ -849,8 +850,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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* be lost or delayed
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*/
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if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
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if (pci_enable_msi(dev->pdev))
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DRM_ERROR("failed to enable MSI\n");
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pci_enable_msi(dev->pdev);
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intel_opregion_init(dev);
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@ -88,13 +88,6 @@ struct mem_block {
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struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
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};
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typedef struct _drm_i915_vbl_swap {
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struct list_head head;
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drm_drawable_t drw_id;
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unsigned int pipe;
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unsigned int sequence;
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} drm_i915_vbl_swap_t;
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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@ -146,10 +139,6 @@ typedef struct drm_i915_private {
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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int vblank_pipe;
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spinlock_t swaps_lock;
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drm_i915_vbl_swap_t vbl_swaps;
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unsigned int swaps_pending;
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struct intel_opregion opregion;
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/* Register state */
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@ -157,6 +146,7 @@ typedef struct drm_i915_private {
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 saveRENDERSTANDBY;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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@ -241,9 +231,6 @@ typedef struct drm_i915_private {
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u8 saveDACDATA[256*3]; /* 256 3-byte colors */
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u8 saveCR[37];
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/** Work task for vblank-related ring access */
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struct work_struct vblank_work;
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struct {
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struct drm_mm gtt_space;
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|
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@ -444,7 +431,6 @@ extern int i915_irq_wait(struct drm_device *dev, void *data,
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void i915_user_irq_get(struct drm_device *dev);
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void i915_user_irq_put(struct drm_device *dev);
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extern void i915_vblank_work_handler(struct work_struct *work);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(struct drm_device * dev);
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extern int i915_driver_irq_postinstall(struct drm_device *dev);
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||||
|
|
@ -622,8 +608,9 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; }
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* The area from dword 0x20 to 0x3ff is available for driver usage.
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||||
*/
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||||
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
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#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
|
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#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
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#define I915_GEM_HWS_INDEX 0x20
|
||||
#define I915_BREADCRUMB_INDEX 0x21
|
||||
|
||||
extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
|
||||
|
||||
|
|
|
|||
|
|
@ -1455,11 +1455,9 @@ i915_gem_object_set_domain_range(struct drm_gem_object *obj,
|
|||
read_domains, write_domain);
|
||||
|
||||
/* Wait on any GPU rendering to the object to be flushed. */
|
||||
if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) {
|
||||
ret = i915_gem_object_wait_rendering(obj);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
ret = i915_gem_object_wait_rendering(obj);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (obj_priv->page_cpu_valid == NULL) {
|
||||
obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
|
||||
|
|
|
|||
|
|
@ -80,211 +80,6 @@ i915_pipe_enabled(struct drm_device *dev, int pipe)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Emit blits for scheduled buffer swaps.
|
||||
*
|
||||
* This function will be called with the HW lock held.
|
||||
* Because this function must grab the ring mutex (dev->struct_mutex),
|
||||
* it can no longer run at soft irq time. We'll fix this when we do
|
||||
* the DRI2 swap buffer work.
|
||||
*/
|
||||
static void i915_vblank_tasklet(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
struct list_head *list, *tmp, hits, *hit;
|
||||
int nhits, nrects, slice[2], upper[2], lower[2], i;
|
||||
unsigned counter[2];
|
||||
struct drm_drawable_info *drw;
|
||||
drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
||||
u32 cpp = dev_priv->cpp;
|
||||
u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
|
||||
XY_SRC_COPY_BLT_WRITE_ALPHA |
|
||||
XY_SRC_COPY_BLT_WRITE_RGB)
|
||||
: XY_SRC_COPY_BLT_CMD;
|
||||
u32 src_pitch = sarea_priv->pitch * cpp;
|
||||
u32 dst_pitch = sarea_priv->pitch * cpp;
|
||||
u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
|
||||
RING_LOCALS;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
if (IS_I965G(dev) && sarea_priv->front_tiled) {
|
||||
cmd |= XY_SRC_COPY_BLT_DST_TILED;
|
||||
dst_pitch >>= 2;
|
||||
}
|
||||
if (IS_I965G(dev) && sarea_priv->back_tiled) {
|
||||
cmd |= XY_SRC_COPY_BLT_SRC_TILED;
|
||||
src_pitch >>= 2;
|
||||
}
|
||||
|
||||
counter[0] = drm_vblank_count(dev, 0);
|
||||
counter[1] = drm_vblank_count(dev, 1);
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
|
||||
INIT_LIST_HEAD(&hits);
|
||||
|
||||
nhits = nrects = 0;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
|
||||
|
||||
/* Find buffer swaps scheduled for this vertical blank */
|
||||
list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
|
||||
drm_i915_vbl_swap_t *vbl_swap =
|
||||
list_entry(list, drm_i915_vbl_swap_t, head);
|
||||
int pipe = vbl_swap->pipe;
|
||||
|
||||
if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
|
||||
continue;
|
||||
|
||||
list_del(list);
|
||||
dev_priv->swaps_pending--;
|
||||
drm_vblank_put(dev, pipe);
|
||||
|
||||
spin_unlock(&dev_priv->swaps_lock);
|
||||
spin_lock(&dev->drw_lock);
|
||||
|
||||
drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
|
||||
|
||||
list_for_each(hit, &hits) {
|
||||
drm_i915_vbl_swap_t *swap_cmp =
|
||||
list_entry(hit, drm_i915_vbl_swap_t, head);
|
||||
struct drm_drawable_info *drw_cmp =
|
||||
drm_get_drawable_info(dev, swap_cmp->drw_id);
|
||||
|
||||
/* Make sure both drawables are still
|
||||
* around and have some rectangles before
|
||||
* we look inside to order them for the
|
||||
* blts below.
|
||||
*/
|
||||
if (drw_cmp && drw_cmp->num_rects > 0 &&
|
||||
drw && drw->num_rects > 0 &&
|
||||
drw_cmp->rects[0].y1 > drw->rects[0].y1) {
|
||||
list_add_tail(list, hit);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock(&dev->drw_lock);
|
||||
|
||||
/* List of hits was empty, or we reached the end of it */
|
||||
if (hit == &hits)
|
||||
list_add_tail(list, hits.prev);
|
||||
|
||||
nhits++;
|
||||
|
||||
spin_lock(&dev_priv->swaps_lock);
|
||||
}
|
||||
|
||||
if (nhits == 0) {
|
||||
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return;
|
||||
}
|
||||
|
||||
spin_unlock(&dev_priv->swaps_lock);
|
||||
|
||||
i915_kernel_lost_context(dev);
|
||||
|
||||
if (IS_I965G(dev)) {
|
||||
BEGIN_LP_RING(4);
|
||||
|
||||
OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
|
||||
OUT_RING(0);
|
||||
OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
|
||||
OUT_RING(0);
|
||||
ADVANCE_LP_RING();
|
||||
} else {
|
||||
BEGIN_LP_RING(6);
|
||||
|
||||
OUT_RING(GFX_OP_DRAWRECT_INFO);
|
||||
OUT_RING(0);
|
||||
OUT_RING(0);
|
||||
OUT_RING(sarea_priv->width | sarea_priv->height << 16);
|
||||
OUT_RING(sarea_priv->width | sarea_priv->height << 16);
|
||||
OUT_RING(0);
|
||||
|
||||
ADVANCE_LP_RING();
|
||||
}
|
||||
|
||||
sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
|
||||
|
||||
upper[0] = upper[1] = 0;
|
||||
slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
|
||||
slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
|
||||
lower[0] = sarea_priv->pipeA_y + slice[0];
|
||||
lower[1] = sarea_priv->pipeB_y + slice[0];
|
||||
|
||||
spin_lock(&dev->drw_lock);
|
||||
|
||||
/* Emit blits for buffer swaps, partitioning both outputs into as many
|
||||
* slices as there are buffer swaps scheduled in order to avoid tearing
|
||||
* (based on the assumption that a single buffer swap would always
|
||||
* complete before scanout starts).
|
||||
*/
|
||||
for (i = 0; i++ < nhits;
|
||||
upper[0] = lower[0], lower[0] += slice[0],
|
||||
upper[1] = lower[1], lower[1] += slice[1]) {
|
||||
if (i == nhits)
|
||||
lower[0] = lower[1] = sarea_priv->height;
|
||||
|
||||
list_for_each(hit, &hits) {
|
||||
drm_i915_vbl_swap_t *swap_hit =
|
||||
list_entry(hit, drm_i915_vbl_swap_t, head);
|
||||
struct drm_clip_rect *rect;
|
||||
int num_rects, pipe;
|
||||
unsigned short top, bottom;
|
||||
|
||||
drw = drm_get_drawable_info(dev, swap_hit->drw_id);
|
||||
|
||||
/* The drawable may have been destroyed since
|
||||
* the vblank swap was queued
|
||||
*/
|
||||
if (!drw)
|
||||
continue;
|
||||
|
||||
rect = drw->rects;
|
||||
pipe = swap_hit->pipe;
|
||||
top = upper[pipe];
|
||||
bottom = lower[pipe];
|
||||
|
||||
for (num_rects = drw->num_rects; num_rects--; rect++) {
|
||||
int y1 = max(rect->y1, top);
|
||||
int y2 = min(rect->y2, bottom);
|
||||
|
||||
if (y1 >= y2)
|
||||
continue;
|
||||
|
||||
BEGIN_LP_RING(8);
|
||||
|
||||
OUT_RING(cmd);
|
||||
OUT_RING(ropcpp | dst_pitch);
|
||||
OUT_RING((y1 << 16) | rect->x1);
|
||||
OUT_RING((y2 << 16) | rect->x2);
|
||||
OUT_RING(sarea_priv->front_offset);
|
||||
OUT_RING((y1 << 16) | rect->x1);
|
||||
OUT_RING(src_pitch);
|
||||
OUT_RING(sarea_priv->back_offset);
|
||||
|
||||
ADVANCE_LP_RING();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
list_for_each_safe(hit, tmp, &hits) {
|
||||
drm_i915_vbl_swap_t *swap_hit =
|
||||
list_entry(hit, drm_i915_vbl_swap_t, head);
|
||||
|
||||
list_del(hit);
|
||||
|
||||
drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
|
||||
}
|
||||
}
|
||||
|
||||
/* Called from drm generic code, passed a 'crtc', which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
|
|
@ -322,40 +117,6 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
|
|||
return count;
|
||||
}
|
||||
|
||||
void
|
||||
i915_vblank_work_handler(struct work_struct *work)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
|
||||
vblank_work);
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
unsigned long irqflags;
|
||||
|
||||
if (dev->lock.hw_lock == NULL) {
|
||||
i915_vblank_tasklet(dev);
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
|
||||
dev->locked_tasklet_func = i915_vblank_tasklet;
|
||||
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
|
||||
|
||||
/* Try to get the lock now, if this fails, the lock
|
||||
* holder will execute the tasklet during unlock
|
||||
*/
|
||||
if (!drm_lock_take(&dev->lock, DRM_KERNEL_CONTEXT))
|
||||
return;
|
||||
|
||||
dev->lock.lock_time = jiffies;
|
||||
atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
|
||||
|
||||
spin_lock_irqsave(&dev->tasklet_lock, irqflags);
|
||||
dev->locked_tasklet_func = NULL;
|
||||
spin_unlock_irqrestore(&dev->tasklet_lock, irqflags);
|
||||
|
||||
i915_vblank_tasklet(dev);
|
||||
drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT);
|
||||
}
|
||||
|
||||
irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
||||
{
|
||||
struct drm_device *dev = (struct drm_device *) arg;
|
||||
|
|
@ -433,9 +194,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
|
|||
if (iir & I915_ASLE_INTERRUPT)
|
||||
opregion_asle_intr(dev);
|
||||
|
||||
if (vblank && dev_priv->swaps_pending > 0)
|
||||
schedule_work(&dev_priv->vblank_work);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
@ -454,12 +212,10 @@ static int i915_emit_irq(struct drm_device * dev)
|
|||
if (dev_priv->sarea_priv)
|
||||
dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
|
||||
|
||||
BEGIN_LP_RING(6);
|
||||
BEGIN_LP_RING(4);
|
||||
OUT_RING(MI_STORE_DWORD_INDEX);
|
||||
OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
|
||||
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
||||
OUT_RING(dev_priv->counter);
|
||||
OUT_RING(0);
|
||||
OUT_RING(0);
|
||||
OUT_RING(MI_USER_INTERRUPT);
|
||||
ADVANCE_LP_RING();
|
||||
|
||||
|
|
@ -696,123 +452,21 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
|
|||
int i915_vblank_swap(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
drm_i915_vblank_swap_t *swap = data;
|
||||
drm_i915_vbl_swap_t *vbl_swap, *vbl_old;
|
||||
unsigned int pipe, seqtype, curseq;
|
||||
unsigned long irqflags;
|
||||
struct list_head *list;
|
||||
int ret;
|
||||
|
||||
if (!dev_priv || !dev_priv->sarea_priv) {
|
||||
DRM_ERROR("%s called with no initialization\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (dev_priv->sarea_priv->rotation) {
|
||||
DRM_DEBUG("Rotation not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
|
||||
_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
|
||||
DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
|
||||
|
||||
seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
|
||||
|
||||
if (!(dev_priv->vblank_pipe & (1 << pipe))) {
|
||||
DRM_ERROR("Invalid pipe %d\n", pipe);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&dev->drw_lock, irqflags);
|
||||
|
||||
if (!drm_get_drawable_info(dev, swap->drawable)) {
|
||||
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
||||
DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
||||
|
||||
/*
|
||||
* We take the ref here and put it when the swap actually completes
|
||||
* in the tasklet.
|
||||
/* The delayed swap mechanism was fundamentally racy, and has been
|
||||
* removed. The model was that the client requested a delayed flip/swap
|
||||
* from the kernel, then waited for vblank before continuing to perform
|
||||
* rendering. The problem was that the kernel might wake the client
|
||||
* up before it dispatched the vblank swap (since the lock has to be
|
||||
* held while touching the ringbuffer), in which case the client would
|
||||
* clear and start the next frame before the swap occurred, and
|
||||
* flicker would occur in addition to likely missing the vblank.
|
||||
*
|
||||
* In the absence of this ioctl, userland falls back to a correct path
|
||||
* of waiting for a vblank, then dispatching the swap on its own.
|
||||
* Context switching to userland and back is plenty fast enough for
|
||||
* meeting the requirements of vblank swapping.
|
||||
*/
|
||||
ret = drm_vblank_get(dev, pipe);
|
||||
if (ret)
|
||||
return ret;
|
||||
curseq = drm_vblank_count(dev, pipe);
|
||||
|
||||
if (seqtype == _DRM_VBLANK_RELATIVE)
|
||||
swap->sequence += curseq;
|
||||
|
||||
if ((curseq - swap->sequence) <= (1<<23)) {
|
||||
if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
|
||||
swap->sequence = curseq + 1;
|
||||
} else {
|
||||
DRM_DEBUG("Missed target sequence\n");
|
||||
drm_vblank_put(dev, pipe);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
|
||||
|
||||
if (!vbl_swap) {
|
||||
DRM_ERROR("Failed to allocate memory to queue swap\n");
|
||||
drm_vblank_put(dev, pipe);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
vbl_swap->drw_id = swap->drawable;
|
||||
vbl_swap->pipe = pipe;
|
||||
vbl_swap->sequence = swap->sequence;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
|
||||
|
||||
list_for_each(list, &dev_priv->vbl_swaps.head) {
|
||||
vbl_old = list_entry(list, drm_i915_vbl_swap_t, head);
|
||||
|
||||
if (vbl_old->drw_id == swap->drawable &&
|
||||
vbl_old->pipe == pipe &&
|
||||
vbl_old->sequence == swap->sequence) {
|
||||
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
||||
drm_vblank_put(dev, pipe);
|
||||
drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
|
||||
DRM_DEBUG("Already scheduled\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (dev_priv->swaps_pending >= 10) {
|
||||
DRM_DEBUG("Too many swaps queued\n");
|
||||
DRM_DEBUG(" pipe 0: %d pipe 1: %d\n",
|
||||
drm_vblank_count(dev, 0),
|
||||
drm_vblank_count(dev, 1));
|
||||
|
||||
list_for_each(list, &dev_priv->vbl_swaps.head) {
|
||||
vbl_old = list_entry(list, drm_i915_vbl_swap_t, head);
|
||||
DRM_DEBUG("\tdrw %x pipe %d seq %x\n",
|
||||
vbl_old->drw_id, vbl_old->pipe,
|
||||
vbl_old->sequence);
|
||||
}
|
||||
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
||||
drm_vblank_put(dev, pipe);
|
||||
drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
|
||||
dev_priv->swaps_pending++;
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* drm_dma.h hooks
|
||||
|
|
@ -831,11 +485,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
|
|||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int ret, num_pipes = 2;
|
||||
|
||||
spin_lock_init(&dev_priv->swaps_lock);
|
||||
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
|
||||
INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_handler);
|
||||
dev_priv->swaps_pending = 0;
|
||||
|
||||
/* Set initial unmasked IRQs to just the selected vblank pipes. */
|
||||
dev_priv->irq_mask_reg = ~0;
|
||||
|
||||
|
|
|
|||
|
|
@ -527,6 +527,9 @@
|
|||
#define C0DRB3 0x10206
|
||||
#define C1DRB3 0x10606
|
||||
|
||||
/** GM965 GM45 render standby register */
|
||||
#define MCHBAR_RENDER_STANDBY 0x111B8
|
||||
|
||||
/*
|
||||
* Overlay regs
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -240,6 +240,10 @@ int i915_save_state(struct drm_device *dev)
|
|||
|
||||
pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
|
||||
|
||||
/* Render Standby */
|
||||
if (IS_I965G(dev) && IS_MOBILE(dev))
|
||||
dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
|
||||
|
||||
/* Display arbitration control */
|
||||
dev_priv->saveDSPARB = I915_READ(DSPARB);
|
||||
|
||||
|
|
@ -365,6 +369,11 @@ int i915_restore_state(struct drm_device *dev)
|
|||
|
||||
pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
|
||||
|
||||
/* Render Standby */
|
||||
if (IS_I965G(dev) && IS_MOBILE(dev))
|
||||
I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
|
||||
|
||||
/* Display arbitration */
|
||||
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
|
||||
|
||||
/* Pipe & plane A info */
|
||||
|
|
|
|||
|
|
@ -1751,6 +1751,12 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
|
|||
else
|
||||
dev_priv->flags |= RADEON_IS_PCI;
|
||||
|
||||
ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
|
||||
drm_get_resource_len(dev, 2), _DRM_REGISTERS,
|
||||
_DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
DRM_DEBUG("%s card detected\n",
|
||||
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
|
||||
return ret;
|
||||
|
|
@ -1767,12 +1773,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
|
|||
|
||||
dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
|
||||
|
||||
ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
|
||||
drm_get_resource_len(dev, 2), _DRM_REGISTERS,
|
||||
_DRM_READ_ONLY, &dev_priv->mmio);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
|
||||
ret = drm_addmap(dev, dev_priv->fb_aper_offset,
|
||||
drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
|
||||
|
|
@ -1788,6 +1788,9 @@ int radeon_driver_unload(struct drm_device *dev)
|
|||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
DRM_DEBUG("\n");
|
||||
|
||||
drm_rmmap(dev, dev_priv->mmio);
|
||||
|
||||
drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
|
||||
|
||||
dev->dev_private = NULL;
|
||||
|
|
|
|||
|
|
@ -287,7 +287,6 @@ typedef struct drm_radeon_private {
|
|||
unsigned long gart_textures_offset;
|
||||
|
||||
drm_local_map_t *sarea;
|
||||
drm_local_map_t *mmio;
|
||||
drm_local_map_t *cp_ring;
|
||||
drm_local_map_t *ring_rptr;
|
||||
drm_local_map_t *gart_textures;
|
||||
|
|
@ -318,6 +317,7 @@ typedef struct drm_radeon_private {
|
|||
|
||||
int num_gb_pipes;
|
||||
int track_flush;
|
||||
drm_local_map_t *mmio;
|
||||
} drm_radeon_private_t;
|
||||
|
||||
typedef struct drm_radeon_buf_priv {
|
||||
|
|
|
|||
|
|
@ -861,8 +861,6 @@ struct drm_device {
|
|||
struct timer_list vblank_disable_timer;
|
||||
|
||||
u32 max_vblank_count; /**< size of vblank counter register */
|
||||
spinlock_t tasklet_lock; /**< For drm_locked_tasklet */
|
||||
void (*locked_tasklet_func)(struct drm_device *dev);
|
||||
|
||||
/*@} */
|
||||
cycles_t ctx_start;
|
||||
|
|
@ -1149,8 +1147,6 @@ extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
|
|||
extern int drm_wait_vblank(struct drm_device *dev, void *data,
|
||||
struct drm_file *filp);
|
||||
extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
|
||||
extern void drm_locked_tasklet(struct drm_device *dev,
|
||||
void(*func)(struct drm_device *));
|
||||
extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
|
||||
extern void drm_handle_vblank(struct drm_device *dev, int crtc);
|
||||
extern int drm_vblank_get(struct drm_device *dev, int crtc);
|
||||
|
|
@ -1158,7 +1154,6 @@ extern void drm_vblank_put(struct drm_device *dev, int crtc);
|
|||
/* Modesetting support */
|
||||
extern int drm_modeset_ctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv);
|
||||
extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
|
||||
|
||||
/* AGP/GART support (drm_agpsupport.h) */
|
||||
extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
|
||||
|
|
|
|||
|
|
@ -395,27 +395,27 @@
|
|||
{0, 0, 0}
|
||||
|
||||
#define i915_PCI_IDS \
|
||||
{0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
|
||||
{0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
|
||||
{0, 0, 0}
|
||||
|
|
|
|||
Loading…
Reference in New Issue