mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: add navi10 ih ip block (v3)
IH is the interrupt handler block. v1: add initial ih support (Ray) v2: add dummy prescreen iv function for navi10 (Hawking) v3: squash in additional updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
5527cd0640
commit
edc611475a
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@ -85,7 +85,8 @@ amdgpu-y += \
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iceland_ih.o \
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tonga_ih.o \
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cz_ih.o \
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vega10_ih.o
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vega10_ih.o \
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navi10_ih.o
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# add PSP block
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amdgpu-y += \
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@ -0,0 +1,486 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "oss/osssys_5_0_0_offset.h"
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#include "oss/osssys_5_0_0_sh_mask.h"
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#include "soc15_common.h"
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#include "navi10_ih.h"
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static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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/**
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* navi10_ih_enable_interrupts - Enable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Enable the interrupt ring buffer (NAVI10).
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*/
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static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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adev->irq.ih.enabled = true;
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}
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/**
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* navi10_ih_disable_interrupts - Disable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Disable the interrupt ring buffer (NAVI10).
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*/
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static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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/* set rptr, wptr to 0 */
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
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adev->irq.ih.enabled = false;
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adev->irq.ih.rptr = 0;
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}
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static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
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{
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int rb_bufsz = order_base_2(ih->ring_size / 4);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
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MC_SPACE, ih->use_bus_addr ? 1 : 4);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
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WPTR_OVERFLOW_CLEAR, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
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WPTR_OVERFLOW_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
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* value is written to memory
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*/
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
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WPTR_WRITEBACK_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
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return ih_rb_cntl;
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}
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/**
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* navi10_ih_irq_init - init and enable the interrupt ring
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate a ring buffer for the interrupt controller,
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* enable the RLC, disable interrupts, enable the IH
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* ring buffer and enable it (NAVI).
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* Called at device load and reume.
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* Returns 0 for success, errors for failure.
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*/
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static int navi10_ih_irq_init(struct amdgpu_device *adev)
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{
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struct amdgpu_ih_ring *ih = &adev->irq.ih;
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int ret = 0;
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u32 ih_rb_cntl, ih_doorbell_rtpr, ih_chicken;
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u32 tmp;
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/* disable irqs */
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navi10_ih_disable_interrupts(adev);
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adev->nbio_funcs->ih_control(adev);
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/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
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ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
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ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
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!!adev->irq.msi_enabled);
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if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
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if (ih->use_bus_addr) {
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ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
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ih_chicken = REG_SET_FIELD(ih_chicken,
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IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
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}
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}
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
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/* set the writeback address whether it's enabled or not */
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
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lower_32_bits(ih->wptr_addr));
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
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upper_32_bits(ih->wptr_addr) & 0xFFFF);
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/* set rptr, wptr to 0 */
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
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ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
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if (ih->use_doorbell) {
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
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IH_DOORBELL_RPTR, OFFSET,
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ih->doorbell_index);
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
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IH_DOORBELL_RPTR, ENABLE, 1);
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} else {
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ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
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IH_DOORBELL_RPTR, ENABLE, 0);
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}
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WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
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adev->nbio_funcs->ih_doorbell_range(adev, ih->use_doorbell,
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ih->doorbell_index);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
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tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
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CLIENT18_IS_STORM_CLIENT, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
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tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
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tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
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WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
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pci_set_master(adev->pdev);
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/* enable interrupts */
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navi10_ih_enable_interrupts(adev);
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return ret;
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}
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/**
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* navi10_ih_irq_disable - disable interrupts
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*
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* @adev: amdgpu_device pointer
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*
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* Disable interrupts on the hw (NAVI10).
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*/
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static void navi10_ih_irq_disable(struct amdgpu_device *adev)
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{
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navi10_ih_disable_interrupts(adev);
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/* Wait and acknowledge irq */
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mdelay(1);
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}
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/**
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* navi10_ih_get_wptr - get the IH ring buffer wptr
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*
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* @adev: amdgpu_device pointer
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*
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* Get the IH ring buffer wptr from either the register
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* or the writeback memory buffer (NAVI10). Also check for
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* ring buffer overflow and deal with it.
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* Returns the value of the wptr.
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*/
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static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih)
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{
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u32 wptr, reg, tmp;
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wptr = le32_to_cpu(*ih->wptr_cpu);
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if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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goto out;
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reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
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wptr = RREG32_NO_KIQ(reg);
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if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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goto out;
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wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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/* When a ring buffer overflow happen start parsing interrupt
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* from the last not overwritten vector (wptr + 32). Hopefully
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* this should allow us to catch up.
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*/
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tmp = (wptr + 32) & ih->ptr_mask;
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dev_warn(adev->dev, "IH ring buffer overflow "
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"(0x%08X, 0x%08X, 0x%08X)\n",
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wptr, ih->rptr, tmp);
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ih->rptr = tmp;
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reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
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tmp = RREG32_NO_KIQ(reg);
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(reg, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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/**
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* navi10_ih_decode_iv - decode an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Decodes the interrupt vector at the current rptr
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* position and also advance the position.
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*/
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static void navi10_ih_decode_iv(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih,
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struct amdgpu_iv_entry *entry)
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{
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/* wptr/rptr are in bytes! */
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u32 ring_index = ih->rptr >> 2;
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uint32_t dw[8];
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dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
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dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
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dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
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dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
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dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
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dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
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dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
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dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
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entry->client_id = dw[0] & 0xff;
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entry->src_id = (dw[0] >> 8) & 0xff;
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entry->ring_id = (dw[0] >> 16) & 0xff;
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entry->vmid = (dw[0] >> 24) & 0xf;
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entry->vmid_src = (dw[0] >> 31);
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entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
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entry->timestamp_src = dw[2] >> 31;
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entry->pasid = dw[3] & 0xffff;
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entry->pasid_src = dw[3] >> 31;
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entry->src_data[0] = dw[4];
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entry->src_data[1] = dw[5];
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entry->src_data[2] = dw[6];
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entry->src_data[3] = dw[7];
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/* wptr/rptr are in bytes! */
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ih->rptr += 32;
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}
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/**
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* navi10_ih_set_rptr - set the IH ring buffer rptr
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*
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* @adev: amdgpu_device pointer
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*
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* Set the IH ring buffer rptr.
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*/
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static void navi10_ih_set_rptr(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih)
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{
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if (ih->use_doorbell) {
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/* XXX check if swapping is necessary on BE */
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*ih->rptr_cpu = ih->rptr;
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WDOORBELL32(ih->doorbell_index, ih->rptr);
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} else
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WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
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}
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static int navi10_ih_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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navi10_ih_set_interrupt_funcs(adev);
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return 0;
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}
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static int navi10_ih_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool use_bus_addr;
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/* use gpu virtual address for ih ring
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* until ih_checken is programmed to allow
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* use bus address for ih ring by psp bl */
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use_bus_addr =
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(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
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r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
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if (r)
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return r;
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adev->irq.ih.use_doorbell = true;
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adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
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r = amdgpu_irq_init(adev);
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return r;
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}
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static int navi10_ih_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev, &adev->irq.ih);
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return 0;
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}
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static int navi10_ih_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = navi10_ih_irq_init(adev);
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if (r)
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return r;
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return 0;
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}
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static int navi10_ih_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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navi10_ih_irq_disable(adev);
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return 0;
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}
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static int navi10_ih_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return navi10_ih_hw_fini(adev);
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}
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static int navi10_ih_resume(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return navi10_ih_hw_init(adev);
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}
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static bool navi10_ih_is_idle(void *handle)
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{
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/* todo */
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return true;
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}
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static int navi10_ih_wait_for_idle(void *handle)
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{
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/* todo */
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return -ETIMEDOUT;
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}
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static int navi10_ih_soft_reset(void *handle)
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{
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/* todo */
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return 0;
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}
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static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data, def, field_val;
|
||||
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
|
||||
def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
|
||||
field_val = enable ? 0 : 1;
|
||||
data = REG_SET_FIELD(data, IH_CLK_CTRL,
|
||||
DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
|
||||
data = REG_SET_FIELD(data, IH_CLK_CTRL,
|
||||
OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
|
||||
data = REG_SET_FIELD(data, IH_CLK_CTRL,
|
||||
LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
|
||||
data = REG_SET_FIELD(data, IH_CLK_CTRL,
|
||||
DYN_CLK_SOFT_OVERRIDE, field_val);
|
||||
data = REG_SET_FIELD(data, IH_CLK_CTRL,
|
||||
REG_CLK_SOFT_OVERRIDE, field_val);
|
||||
if (def != data)
|
||||
WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int navi10_ih_set_clockgating_state(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
navi10_ih_update_clockgating_state(adev,
|
||||
state == AMD_CG_STATE_GATE ? true : false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int navi10_ih_set_powergating_state(void *handle,
|
||||
enum amd_powergating_state state)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void navi10_ih_get_clockgating_state(void *handle, u32 *flags)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
|
||||
*flags |= AMD_CG_SUPPORT_IH_CG;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static const struct amd_ip_funcs navi10_ih_ip_funcs = {
|
||||
.name = "navi10_ih",
|
||||
.early_init = navi10_ih_early_init,
|
||||
.late_init = NULL,
|
||||
.sw_init = navi10_ih_sw_init,
|
||||
.sw_fini = navi10_ih_sw_fini,
|
||||
.hw_init = navi10_ih_hw_init,
|
||||
.hw_fini = navi10_ih_hw_fini,
|
||||
.suspend = navi10_ih_suspend,
|
||||
.resume = navi10_ih_resume,
|
||||
.is_idle = navi10_ih_is_idle,
|
||||
.wait_for_idle = navi10_ih_wait_for_idle,
|
||||
.soft_reset = navi10_ih_soft_reset,
|
||||
.set_clockgating_state = navi10_ih_set_clockgating_state,
|
||||
.set_powergating_state = navi10_ih_set_powergating_state,
|
||||
.get_clockgating_state = navi10_ih_get_clockgating_state,
|
||||
};
|
||||
|
||||
static const struct amdgpu_ih_funcs navi10_ih_funcs = {
|
||||
.get_wptr = navi10_ih_get_wptr,
|
||||
.decode_iv = navi10_ih_decode_iv,
|
||||
.set_rptr = navi10_ih_set_rptr
|
||||
};
|
||||
|
||||
static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
if (adev->irq.ih_funcs == NULL)
|
||||
adev->irq.ih_funcs = &navi10_ih_funcs;
|
||||
}
|
||||
|
||||
const struct amdgpu_ip_block_version navi10_ih_ip_block =
|
||||
{
|
||||
.type = AMD_IP_BLOCK_TYPE_IH,
|
||||
.major = 5,
|
||||
.minor = 0,
|
||||
.rev = 0,
|
||||
.funcs = &navi10_ih_ip_funcs,
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2019 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NAVI10_IH_H__
|
||||
#define __NAVI10_IH_H__
|
||||
|
||||
extern const struct amdgpu_ip_block_version navi10_ih_ip_block;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue