mirror of https://gitee.com/openkylin/linux.git
perfcounters: restructure x86 counter math
Impact: restructure code Change counter math from absolute values to clear delta logic. We try to extract elapsed deltas from the raw hw counter - and put that into the generic counter. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
parent
9b194e831f
commit
ee06094f82
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@ -643,7 +643,7 @@ config X86_UP_IOAPIC
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config X86_LOCAL_APIC
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def_bool y
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depends on X86_64 || (X86_32 && (X86_UP_APIC || (SMP && !X86_VOYAGER) || X86_GENERICARCH))
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select HAVE_PERF_COUNTERS
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select HAVE_PERF_COUNTERS if (!M386 && !M486)
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config X86_IO_APIC
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def_bool y
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@ -53,6 +53,48 @@ const int intel_perfmon_event_map[] =
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const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map);
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/*
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* Propagate counter elapsed time into the generic counter.
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* Can only be executed on the CPU where the counter is active.
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* Returns the delta events processed.
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*/
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static void
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x86_perf_counter_update(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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{
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u64 prev_raw_count, new_raw_count, delta;
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WARN_ON_ONCE(counter->state != PERF_COUNTER_STATE_ACTIVE);
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/*
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* Careful: an NMI might modify the previous counter value.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic counter atomically:
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*/
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again:
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prev_raw_count = atomic64_read(&hwc->prev_count);
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rdmsrl(hwc->counter_base + idx, new_raw_count);
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if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (counter-)time and add that to the generic counter.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count, so we do that by clipping the delta to 32 bits:
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*/
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delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
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WARN_ON_ONCE((int)delta < 0);
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atomic64_add(delta, &counter->count);
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atomic64_sub(delta, &hwc->period_left);
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}
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/*
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* Setup the hardware configuration for a given hw_event_type
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*/
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@ -90,10 +132,10 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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* so we install an artificial 1<<31 period regardless of
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* the generic counter period:
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*/
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if (!hwc->irq_period)
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if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF)
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hwc->irq_period = 0x7FFFFFFF;
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hwc->next_count = -(s32)hwc->irq_period;
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atomic64_set(&hwc->period_left, hwc->irq_period);
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/*
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* Raw event type provide the config in the event structure
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@ -118,12 +160,6 @@ void hw_perf_enable_all(void)
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0);
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}
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void hw_perf_restore(u64 ctrl)
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{
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, ctrl, 0);
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}
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EXPORT_SYMBOL_GPL(hw_perf_restore);
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u64 hw_perf_save_disable(void)
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{
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u64 ctrl;
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@ -134,27 +170,74 @@ u64 hw_perf_save_disable(void)
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}
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EXPORT_SYMBOL_GPL(hw_perf_save_disable);
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void hw_perf_restore(u64 ctrl)
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{
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wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, ctrl, 0);
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}
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EXPORT_SYMBOL_GPL(hw_perf_restore);
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static inline void
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__x86_perf_counter_disable(struct hw_perf_counter *hwc, unsigned int idx)
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__x86_perf_counter_disable(struct perf_counter *counter,
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struct hw_perf_counter *hwc, unsigned int idx)
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{
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wrmsr(hwc->config_base + idx, hwc->config, 0);
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int err;
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err = wrmsr_safe(hwc->config_base + idx, hwc->config, 0);
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WARN_ON_ONCE(err);
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}
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static DEFINE_PER_CPU(u64, prev_next_count[MAX_HW_COUNTERS]);
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static DEFINE_PER_CPU(u64, prev_left[MAX_HW_COUNTERS]);
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static void __hw_perf_counter_set_period(struct hw_perf_counter *hwc, int idx)
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/*
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* Set the next IRQ period, based on the hwc->period_left value.
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* To be called with the counter disabled in hw:
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*/
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static void
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__hw_perf_counter_set_period(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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{
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per_cpu(prev_next_count[idx], smp_processor_id()) = hwc->next_count;
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s32 left = atomic64_read(&hwc->period_left);
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s32 period = hwc->irq_period;
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wrmsr(hwc->counter_base + idx, hwc->next_count, 0);
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WARN_ON_ONCE(period <= 0);
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/*
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* If we are way outside a reasoable range then just skip forward:
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*/
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if (unlikely(left <= -period)) {
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left = period;
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atomic64_set(&hwc->period_left, left);
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}
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if (unlikely(left <= 0)) {
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left += period;
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atomic64_set(&hwc->period_left, left);
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}
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WARN_ON_ONCE(left <= 0);
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per_cpu(prev_left[idx], smp_processor_id()) = left;
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/*
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* The hw counter starts counting from this counter offset,
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* mark it to be able to extra future deltas:
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*/
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atomic64_set(&hwc->prev_count, (u64)(s64)-left);
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wrmsr(hwc->counter_base + idx, -left, 0);
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}
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static void __x86_perf_counter_enable(struct hw_perf_counter *hwc, int idx)
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static void
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__x86_perf_counter_enable(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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{
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wrmsr(hwc->config_base + idx,
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hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0);
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}
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/*
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* Find a PMC slot for the freshly enabled / scheduled in counter:
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*/
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static void x86_perf_counter_enable(struct perf_counter *counter)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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@ -170,55 +253,17 @@ static void x86_perf_counter_enable(struct perf_counter *counter)
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perf_counters_lapic_init(hwc->nmi);
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__x86_perf_counter_disable(hwc, idx);
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__x86_perf_counter_disable(counter, hwc, idx);
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cpuc->counters[idx] = counter;
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__hw_perf_counter_set_period(hwc, idx);
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__x86_perf_counter_enable(hwc, idx);
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}
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static void __hw_perf_save_counter(struct perf_counter *counter,
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struct hw_perf_counter *hwc, int idx)
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{
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s64 raw = -1;
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s64 delta;
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/*
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* Get the raw hw counter value:
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*/
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rdmsrl(hwc->counter_base + idx, raw);
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/*
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* Rebase it to zero (it started counting at -irq_period),
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* to see the delta since ->prev_count:
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*/
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delta = (s64)hwc->irq_period + (s64)(s32)raw;
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atomic64_counter_set(counter, hwc->prev_count + delta);
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/*
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* Adjust the ->prev_count offset - if we went beyond
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* irq_period of units, then we got an IRQ and the counter
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* was set back to -irq_period:
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*/
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while (delta >= (s64)hwc->irq_period) {
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hwc->prev_count += hwc->irq_period;
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delta -= (s64)hwc->irq_period;
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}
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/*
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* Calculate the next raw counter value we'll write into
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* the counter at the next sched-in time:
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*/
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delta -= (s64)hwc->irq_period;
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hwc->next_count = (s32)delta;
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__hw_perf_counter_set_period(counter, hwc, idx);
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__x86_perf_counter_enable(counter, hwc, idx);
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}
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void perf_counter_print_debug(void)
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{
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u64 ctrl, status, overflow, pmc_ctrl, pmc_count, next_count;
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u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left;
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int cpu, idx;
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if (!nr_hw_counters)
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@ -241,14 +286,14 @@ void perf_counter_print_debug(void)
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rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl);
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rdmsrl(MSR_ARCH_PERFMON_PERFCTR0 + idx, pmc_count);
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next_count = per_cpu(prev_next_count[idx], cpu);
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prev_left = per_cpu(prev_left[idx], cpu);
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printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n",
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cpu, idx, pmc_ctrl);
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printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n",
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cpu, idx, pmc_count);
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printk(KERN_INFO "CPU#%d: PMC%d next: %016llx\n",
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cpu, idx, next_count);
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printk(KERN_INFO "CPU#%d: PMC%d left: %016llx\n",
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cpu, idx, prev_left);
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}
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local_irq_enable();
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}
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@ -259,29 +304,16 @@ static void x86_perf_counter_disable(struct perf_counter *counter)
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struct hw_perf_counter *hwc = &counter->hw;
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unsigned int idx = hwc->idx;
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__x86_perf_counter_disable(hwc, idx);
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__x86_perf_counter_disable(counter, hwc, idx);
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clear_bit(idx, cpuc->used);
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cpuc->counters[idx] = NULL;
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__hw_perf_save_counter(counter, hwc, idx);
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}
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static void x86_perf_counter_read(struct perf_counter *counter)
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{
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struct hw_perf_counter *hwc = &counter->hw;
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unsigned long addr = hwc->counter_base + hwc->idx;
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s64 offs, val = -1LL;
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s32 val32;
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/* Careful: NMI might modify the counter offset */
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do {
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offs = hwc->prev_count;
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rdmsrl(addr, val);
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} while (offs != hwc->prev_count);
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val32 = (s32) val;
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val = (s64)hwc->irq_period + (s64)val32;
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atomic64_counter_set(counter, hwc->prev_count + val);
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/*
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* Drain the remaining delta count out of a counter
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* that we are disabling:
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*/
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x86_perf_counter_update(counter, hwc, idx);
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}
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static void perf_store_irq_data(struct perf_counter *counter, u64 data)
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@ -299,7 +331,8 @@ static void perf_store_irq_data(struct perf_counter *counter, u64 data)
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}
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/*
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* NMI-safe enable method:
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* Save and restart an expired counter. Called by NMI contexts,
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* so it has to be careful about preempting normal counter ops:
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*/
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static void perf_save_and_restart(struct perf_counter *counter)
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{
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@ -309,45 +342,25 @@ static void perf_save_and_restart(struct perf_counter *counter)
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rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl);
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__hw_perf_save_counter(counter, hwc, idx);
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__hw_perf_counter_set_period(hwc, idx);
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x86_perf_counter_update(counter, hwc, idx);
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__hw_perf_counter_set_period(counter, hwc, idx);
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if (pmc_ctrl & ARCH_PERFMON_EVENTSEL0_ENABLE)
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__x86_perf_counter_enable(hwc, idx);
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__x86_perf_counter_enable(counter, hwc, idx);
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}
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static void
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perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown)
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{
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struct perf_counter *counter, *group_leader = sibling->group_leader;
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int bit;
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/*
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* Store the counter's own timestamp first:
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*/
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perf_store_irq_data(sibling, sibling->hw_event.type);
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perf_store_irq_data(sibling, atomic64_counter_read(sibling));
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/*
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* Then store sibling timestamps (if any):
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* Store sibling timestamps (if any):
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*/
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list_for_each_entry(counter, &group_leader->sibling_list, list_entry) {
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if (counter->state != PERF_COUNTER_STATE_ACTIVE) {
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/*
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* When counter was not in the overflow mask, we have to
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* read it from hardware. We read it as well, when it
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* has not been read yet and clear the bit in the
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* status mask.
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*/
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bit = counter->hw.idx;
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if (!test_bit(bit, (unsigned long *) overflown) ||
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test_bit(bit, (unsigned long *) status)) {
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clear_bit(bit, (unsigned long *) status);
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perf_save_and_restart(counter);
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}
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}
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x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
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perf_store_irq_data(sibling, counter->hw_event.type);
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perf_store_irq_data(sibling, atomic64_counter_read(counter));
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perf_store_irq_data(sibling, atomic64_read(&counter->count));
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}
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}
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@ -540,6 +553,11 @@ void __init init_hw_perf_counters(void)
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perf_counters_initialized = true;
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}
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static void x86_perf_counter_read(struct perf_counter *counter)
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{
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x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
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}
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static const struct hw_perf_counter_ops x86_perf_counter_ops = {
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.hw_perf_counter_enable = x86_perf_counter_enable,
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.hw_perf_counter_disable = x86_perf_counter_disable,
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@ -91,14 +91,16 @@ struct perf_counter_hw_event {
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* struct hw_perf_counter - performance counter hardware details:
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*/
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struct hw_perf_counter {
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#ifdef CONFIG_PERF_COUNTERS
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u64 config;
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unsigned long config_base;
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unsigned long counter_base;
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int nmi;
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unsigned int idx;
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u64 prev_count;
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atomic64_t prev_count;
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u64 irq_period;
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s32 next_count;
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atomic64_t period_left;
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#endif
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};
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/*
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@ -140,17 +142,15 @@ enum perf_counter_active_state {
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* struct perf_counter - performance counter kernel representation:
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*/
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struct perf_counter {
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#ifdef CONFIG_PERF_COUNTERS
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struct list_head list_entry;
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struct list_head sibling_list;
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struct perf_counter *group_leader;
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const struct hw_perf_counter_ops *hw_ops;
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enum perf_counter_active_state state;
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#if BITS_PER_LONG == 64
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atomic64_t count;
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#else
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atomic_t count32[2];
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#endif
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struct perf_counter_hw_event hw_event;
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struct hw_perf_counter hw;
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@ -172,6 +172,7 @@ struct perf_counter {
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struct perf_data *irqdata;
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struct perf_data *usrdata;
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struct perf_data data[2];
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#endif
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};
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/**
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@ -220,8 +221,6 @@ extern void perf_counter_notify(struct pt_regs *regs);
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extern void perf_counter_print_debug(void);
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extern u64 hw_perf_save_disable(void);
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extern void hw_perf_restore(u64 ctrl);
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extern void atomic64_counter_set(struct perf_counter *counter, u64 val64);
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extern u64 atomic64_counter_read(struct perf_counter *counter);
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extern int perf_counter_task_disable(void);
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extern int perf_counter_task_enable(void);
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@ -44,67 +44,9 @@ hw_perf_counter_init(struct perf_counter *counter)
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}
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u64 __weak hw_perf_save_disable(void) { return 0; }
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void __weak hw_perf_restore(u64 ctrl) { }
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void __weak hw_perf_restore(u64 ctrl) { }
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void __weak hw_perf_counter_setup(void) { }
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#if BITS_PER_LONG == 64
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/*
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* Read the cached counter in counter safe against cross CPU / NMI
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* modifications. 64 bit version - no complications.
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*/
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static inline u64 perf_counter_read_safe(struct perf_counter *counter)
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{
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return (u64) atomic64_read(&counter->count);
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}
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void atomic64_counter_set(struct perf_counter *counter, u64 val)
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{
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atomic64_set(&counter->count, val);
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}
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u64 atomic64_counter_read(struct perf_counter *counter)
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{
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return atomic64_read(&counter->count);
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}
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#else
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/*
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* Read the cached counter in counter safe against cross CPU / NMI
|
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* modifications. 32 bit version.
|
||||
*/
|
||||
static u64 perf_counter_read_safe(struct perf_counter *counter)
|
||||
{
|
||||
u32 cntl, cnth;
|
||||
|
||||
local_irq_disable();
|
||||
do {
|
||||
cnth = atomic_read(&counter->count32[1]);
|
||||
cntl = atomic_read(&counter->count32[0]);
|
||||
} while (cnth != atomic_read(&counter->count32[1]));
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
return cntl | ((u64) cnth) << 32;
|
||||
}
|
||||
|
||||
void atomic64_counter_set(struct perf_counter *counter, u64 val64)
|
||||
{
|
||||
u32 *val32 = (void *)&val64;
|
||||
|
||||
atomic_set(counter->count32 + 0, *(val32 + 0));
|
||||
atomic_set(counter->count32 + 1, *(val32 + 1));
|
||||
}
|
||||
|
||||
u64 atomic64_counter_read(struct perf_counter *counter)
|
||||
{
|
||||
return atomic_read(counter->count32 + 0) |
|
||||
(u64) atomic_read(counter->count32 + 1) << 32;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void
|
||||
list_add_counter(struct perf_counter *counter, struct perf_counter_context *ctx)
|
||||
{
|
||||
|
|
@ -280,11 +222,11 @@ static void __perf_install_in_context(void *info)
|
|||
ctx->nr_counters++;
|
||||
|
||||
if (cpuctx->active_oncpu < perf_max_counters) {
|
||||
counter->hw_ops->hw_perf_counter_enable(counter);
|
||||
counter->state = PERF_COUNTER_STATE_ACTIVE;
|
||||
counter->oncpu = cpu;
|
||||
ctx->nr_active++;
|
||||
cpuctx->active_oncpu++;
|
||||
counter->hw_ops->hw_perf_counter_enable(counter);
|
||||
}
|
||||
|
||||
if (!ctx->task && cpuctx->max_pertask)
|
||||
|
|
@ -624,7 +566,7 @@ static u64 perf_counter_read(struct perf_counter *counter)
|
|||
__hw_perf_counter_read, counter, 1);
|
||||
}
|
||||
|
||||
return perf_counter_read_safe(counter);
|
||||
return atomic64_read(&counter->count);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -921,7 +863,7 @@ static void cpu_clock_perf_counter_read(struct perf_counter *counter)
|
|||
{
|
||||
int cpu = raw_smp_processor_id();
|
||||
|
||||
atomic64_counter_set(counter, cpu_clock(cpu));
|
||||
atomic64_set(&counter->count, cpu_clock(cpu));
|
||||
}
|
||||
|
||||
static const struct hw_perf_counter_ops perf_ops_cpu_clock = {
|
||||
|
|
@ -940,7 +882,7 @@ static void task_clock_perf_counter_disable(struct perf_counter *counter)
|
|||
|
||||
static void task_clock_perf_counter_read(struct perf_counter *counter)
|
||||
{
|
||||
atomic64_counter_set(counter, current->se.sum_exec_runtime);
|
||||
atomic64_set(&counter->count, current->se.sum_exec_runtime);
|
||||
}
|
||||
|
||||
static const struct hw_perf_counter_ops perf_ops_task_clock = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue