mirror of https://gitee.com/openkylin/linux.git
Merge tag 'arm-soc/for-4.5/devicetree' of http://github.com/Broadcom/stblinux into next/dt
Pull "Broadcom devicetree changes for v4.5¨ from Florian Fainelli: This pull request contains the Broadcom ARM-based Device Tree changes for 4.5: - Jon Mason enables the following for Broadcom Northstar Plus SoCs: PCI (using iProc PCI), NAND flash controller (BRCMNAND), TWD Timer and Watchdog (Cortex-A9), I2C (iProc), clock providers, does some Device Tree cleanups (re-parenting, fixing register sizes and hierarchy) - Jon Mason also adds support for some reference Broadcom Northstar reference designs like the BCM5301X SVK reference boards, updates the existing binding documentation to cover the Northstar chips: 4708, 4709 and 53012. - Pramod Kumar adds the GPIO to pinctrl mapping for the Broadcom Northstar Plus SoCs - Yendapally Reddy Dhananjaya Reddy adds pinctrl Device Tree nodes for the Broadcom Northstar Plus SoCs device tree nodes - Ray Jui adds Cygnus PCIe PHY Device Tree nodes and enables MSI for the iProc PCI controller on Cygnus platforms - Kapil Hali adds SMP binding documentation and Device Tree nodes for the Northstar Plus SoCs - Florian Fainelli adds clock provider support for the Broadcom BCM63138 DSL SoCs by utilizing the existing iProc ARM PLL controller, this includes a stable topic branch from Stephen Boyd to be merged - Rafal Milecki adds missing LEDs for the Netgear R8000 router * tag 'arm-soc/for-4.5/devicetree' of http://github.com/Broadcom/stblinux: ARM: dts: Enable MSI support for Broadcom Cygnus ARM: dts: Add SMP support for Broadcom NSP dt-bindings: add SMP enable-method for Broadcom NSP ARM: dts: enable pinctrl for Broadcom NSP ARM: dts: enable PCIe PHY support for Cygnus ARM: dts: Cygnus: define ngpios property in gpio controller's node ARM: BCM5301X: Add missing Netgear R8000 LEDs ARM: dts: BCM63xx: Add ARMPLL device tree nodes clk: bcm: Add BCM63138 clock support clk: iproc: Extend binding to cover BCM63138 ARM: dts: enable clock support for Broadcom NSP ARM: dts: enable clock support for BCM5301X ARM: dts: NSP: Add I2C support to the DT ARM: dts: NSP: Device Tree clean-ups dts: pinctrl: Add GPIO to Pinctrl pin mapping in DT ARM: dts: bcm5301x: Add BCM SVK DT files dt-bindings: Add new SoCs to bcm4708 DT bindings ARM: dts: NSP: Add TWD Support to DT ARM: dts: NSP: Add NAND Support to DT ARM: dts: NSP: Add PCI support
This commit is contained in:
Arnd Bergmann
commit
ee5d892395
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|
@ -5,4 +5,11 @@ Boards with the BCM4708 SoC shall have the following properties:
|
|||
|
||||
Required root node property:
|
||||
|
||||
bcm4708
|
||||
compatible = "brcm,bcm4708";
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||||
|
||||
bcm4709
|
||||
compatible = "brcm,bcm4709";
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||||
|
||||
bcm53012
|
||||
compatible = "brcm,bcm53012";
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||||
|
|
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|||
|
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@ -0,0 +1,39 @@
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Broadcom Northstar Plus SoC CPU Enable Method
|
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---------------------------------------------
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This binding defines the enable method used for starting secondary
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CPU in the following Broadcom SoCs:
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BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
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The enable method is specified by defining the following required
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properties in the corresponding secondary "cpu" device tree node:
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- enable-method = "brcm,bcm-nsp-smp";
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- secondary-boot-reg = <...>;
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The secondary-boot-reg property is a u32 value that specifies the
|
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physical address of the register which should hold the common
|
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entry point for a secondary CPU. This entry is cpu node specific
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and should be added per cpu. E.g., in case of NSP (BCM58625) which
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is a dual core CPU SoC, this entry should be added to cpu1 node.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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enable-method = "brcm,bcm-nsp-smp";
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secondary-boot-reg = <0xffff042c>;
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reg = <1>;
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};
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};
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@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"arm,psci"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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|
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@ -208,3 +208,8 @@ These clock IDs are defined in:
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ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
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ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
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ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
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BCM63138
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--------
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PLL and leaf clock compatible strings for BCM63138 are:
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"brcm,bcm63138-armpll"
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@ -75,7 +75,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
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bcm4709-asus-rt-ac87u.dtb \
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bcm4709-buffalo-wxr-1900dhp.dtb \
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bcm4709-netgear-r7000.dtb \
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bcm4709-netgear-r8000.dtb
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bcm4709-netgear-r8000.dtb \
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bcm94708.dtb \
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bcm94709.dtb \
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bcm953012k.dtb
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dtb-$(CONFIG_ARCH_BCM_63XX) += \
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bcm963138dvt.dtb
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dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
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|
|
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@ -91,6 +91,23 @@ axi {
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#address-cells = <1>;
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#size-cells = <1>;
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|
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pcie_phy: phy@0301d0a0 {
|
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compatible = "brcm,cygnus-pcie-phy";
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reg = <0x0301d0a0 0x14>;
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#address-cells = <1>;
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#size-cells = <0>;
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|
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pcie0_phy: phy@0 {
|
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reg = <0>;
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#phy-cells = <0>;
|
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};
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|
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pcie1_phy: phy@1 {
|
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reg = <1>;
|
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#phy-cells = <0>;
|
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};
|
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};
|
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|
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pinctrl: pinctrl@0x0301d0c8 {
|
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compatible = "brcm,cygnus-pinmux";
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reg = <0x0301d0c8 0x30>,
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|
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@ -101,6 +118,7 @@ gpio_crmu: gpio@03024800 {
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compatible = "brcm,cygnus-crmu-gpio";
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reg = <0x03024800 0x50>,
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<0x03024008 0x18>;
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ngpios = <6>;
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#gpio-cells = <2>;
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gpio-controller;
|
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};
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@ -127,6 +145,7 @@ gpio_ccm: gpio@1800a000 {
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compatible = "brcm,cygnus-ccm-gpio";
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reg = <0x1800a000 0x50>,
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<0x0301d164 0x20>;
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ngpios = <24>;
|
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#gpio-cells = <2>;
|
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gpio-controller;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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@ -161,7 +180,21 @@ pcie0: pcie@18012000 {
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000
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||||
0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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|
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phys = <&pcie0_phy>;
|
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phy-names = "pcie-phy";
|
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|
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status = "disabled";
|
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|
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msi-parent = <&msi0>;
|
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msi0: msi@18012000 {
|
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compatible = "brcm,iproc-msi";
|
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msi-controller;
|
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
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<GIC_SPI 97 IRQ_TYPE_NONE>,
|
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<GIC_SPI 98 IRQ_TYPE_NONE>,
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<GIC_SPI 99 IRQ_TYPE_NONE>;
|
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};
|
||||
};
|
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|
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pcie1: pcie@18013000 {
|
||||
|
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@ -182,7 +215,21 @@ pcie1: pcie@18013000 {
|
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000
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0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
|
||||
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pcie-phy";
|
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|
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status = "disabled";
|
||||
|
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msi-parent = <&msi1>;
|
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msi1: msi@18013000 {
|
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compatible = "brcm,iproc-msi";
|
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msi-controller;
|
||||
interrupt-parent = <&gic>;
|
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interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
|
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<GIC_SPI 103 IRQ_TYPE_NONE>,
|
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<GIC_SPI 104 IRQ_TYPE_NONE>,
|
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<GIC_SPI 105 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
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|
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uart0: serial@18020000 {
|
||||
|
|
@ -245,13 +292,63 @@ nand: nand@18046000 {
|
|||
gpio_asiu: gpio@180a5000 {
|
||||
compatible = "brcm,cygnus-asiu-gpio";
|
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reg = <0x180a5000 0x668>;
|
||||
ngpios = <146>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
pinmux = <&pinctrl>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&pinctrl 0 42 1>,
|
||||
<&pinctrl 1 44 3>,
|
||||
<&pinctrl 4 48 1>,
|
||||
<&pinctrl 5 50 3>,
|
||||
<&pinctrl 8 126 1>,
|
||||
<&pinctrl 9 155 1>,
|
||||
<&pinctrl 10 152 1>,
|
||||
<&pinctrl 11 154 1>,
|
||||
<&pinctrl 12 153 1>,
|
||||
<&pinctrl 13 127 3>,
|
||||
<&pinctrl 16 140 1>,
|
||||
<&pinctrl 17 145 7>,
|
||||
<&pinctrl 24 130 10>,
|
||||
<&pinctrl 34 141 4>,
|
||||
<&pinctrl 38 54 1>,
|
||||
<&pinctrl 39 56 3>,
|
||||
<&pinctrl 42 60 3>,
|
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<&pinctrl 45 64 3>,
|
||||
<&pinctrl 48 68 2>,
|
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<&pinctrl 50 84 6>,
|
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<&pinctrl 56 94 6>,
|
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<&pinctrl 62 72 1>,
|
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<&pinctrl 63 70 1>,
|
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<&pinctrl 64 80 1>,
|
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<&pinctrl 65 74 3>,
|
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<&pinctrl 68 78 1>,
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<&pinctrl 69 82 1>,
|
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<&pinctrl 70 156 17>,
|
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<&pinctrl 87 104 12>,
|
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<&pinctrl 99 102 2>,
|
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<&pinctrl 101 90 4>,
|
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<&pinctrl 105 116 6>,
|
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<&pinctrl 111 100 2>,
|
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<&pinctrl 113 122 4>,
|
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<&pinctrl 123 11 1>,
|
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<&pinctrl 124 38 4>,
|
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<&pinctrl 128 43 1>,
|
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<&pinctrl 129 47 1>,
|
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<&pinctrl 130 49 1>,
|
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<&pinctrl 131 53 1>,
|
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<&pinctrl 132 55 1>,
|
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<&pinctrl 133 59 1>,
|
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<&pinctrl 134 63 1>,
|
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<&pinctrl 135 67 1>,
|
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<&pinctrl 136 71 1>,
|
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<&pinctrl 137 73 1>,
|
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<&pinctrl 138 77 1>,
|
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<&pinctrl 139 79 1>,
|
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<&pinctrl 140 81 1>,
|
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<&pinctrl 141 83 1>,
|
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<&pinctrl 142 10 1>;
|
||||
};
|
||||
|
||||
touchscreen: tsc@180a6000 {
|
||||
|
|
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@ -32,6 +32,7 @@
|
|||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/bcm-nsp.h>
|
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|
||||
#include "skeleton.dtsi"
|
||||
|
||||
|
|
@ -40,9 +41,30 @@ / {
|
|||
model = "Broadcom Northstar Plus SoC";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
enable-method = "brcm,bcm-nsp-smp";
|
||||
secondary-boot-reg = <0xffff042c>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mpcore {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x19020000 0x00003000>;
|
||||
ranges = <0x00000000 0x19000000 0x00023000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -58,27 +80,50 @@ cpu@0 {
|
|||
};
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x2000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
a9pll: arm_clk@00000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,nsp-armpll";
|
||||
clocks = <&osc>;
|
||||
reg = <0x00000 0x1000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@19021000 {
|
||||
timer@20200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x20200 0x100>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
twd-timer@20600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x20600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
twd-watchdog@20620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x20620 0x20>;
|
||||
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@21000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x0100 0x100>;
|
||||
reg = <0x21000 0x1000>,
|
||||
<0x20100 0x100>;
|
||||
};
|
||||
|
||||
timer@19020200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x0200 0x100>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x22000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -87,33 +132,178 @@ clocks {
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
iprocmed: iprocmed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
iprocslow: iprocslow {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
periph_clk: periph_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&a9pll>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x18000000 0x00001000>;
|
||||
ranges = <0x00000000 0x18000000 0x0011ba08>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uart0: serial@18000300 {
|
||||
uart0: serial@0300 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x0300 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <62499840>;
|
||||
clocks = <&osc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@18000400 {
|
||||
uart1: serial@0400 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x0400 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <62499840>;
|
||||
clocks = <&osc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: pcie@12000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x12000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pcie@13000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x13000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2: pcie@14000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x14000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@26000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
||||
reg = <0x026000 0x600>,
|
||||
<0x11b408 0x600>,
|
||||
<0x026f00 0x20>;
|
||||
reg-names = "nand", "iproc-idm", "iproc-ext";
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
brcm,nand-has-wp;
|
||||
};
|
||||
|
||||
i2c0: i2c@38000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x38000 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
lcpll0: lcpll0@3f100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-lcpll0";
|
||||
reg = <0x3f100 0x14>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll0", "pcie_phy", "sdio",
|
||||
"ddr_phy";
|
||||
};
|
||||
|
||||
genpll: genpll@3f140 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-genpll";
|
||||
reg = <0x3f140 0x24>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll", "phy", "ethernetclk",
|
||||
"usbclk", "iprocfast", "sata1",
|
||||
"sata2";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@3f1c0 {
|
||||
compatible = "brcm,nsp-pinmux";
|
||||
reg = <0x3f1c0 0x04>,
|
||||
<0x30028 0x04>,
|
||||
<0x3f408 0x04>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,36 @@ power1 {
|
|||
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wireless {
|
||||
label = "bcm53xx:white:wireless";
|
||||
gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "bcm53xx:white:wps";
|
||||
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
5ghz-2 {
|
||||
label = "bcm53xx:white:5ghz-2";
|
||||
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
usb3 {
|
||||
label = "bcm53xx:white:usb3";
|
||||
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
usb2 {
|
||||
label = "bcm53xx:white:usb2";
|
||||
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/bcm-nsp.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
|
@ -27,7 +28,7 @@ uart0: serial@0300 {
|
|||
compatible = "ns16550";
|
||||
reg = <0x0300 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <100000000>;
|
||||
clocks = <&iprocslow>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -35,48 +36,55 @@ uart1: serial@0400 {
|
|||
compatible = "ns16550";
|
||||
reg = <0x0400 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <100000000>;
|
||||
clocks = <&iprocslow>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mpcore {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x19020000 0x00003000>;
|
||||
ranges = <0x00000000 0x19000000 0x00023000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
scu@0000 {
|
||||
a9pll: arm_clk@00000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,nsp-armpll";
|
||||
clocks = <&osc>;
|
||||
reg = <0x00000 0x1000>;
|
||||
};
|
||||
|
||||
scu@20000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x0000 0x100>;
|
||||
reg = <0x20000 0x100>;
|
||||
};
|
||||
|
||||
timer@0200 {
|
||||
timer@20200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x0200 0x100>;
|
||||
reg = <0x20200 0x100>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_periph>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
local-timer@0600 {
|
||||
local-timer@20600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x0600 0x100>;
|
||||
reg = <0x20600 0x100>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_periph>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
gic: interrupt-controller@21000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x0100 0x100>;
|
||||
reg = <0x21000 0x1000>,
|
||||
<0x20100 0x100>;
|
||||
};
|
||||
|
||||
L2: cache-controller@2000 {
|
||||
L2: cache-controller@22000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x2000 0x1000>;
|
||||
reg = <0x22000 0x1000>;
|
||||
cache-unified;
|
||||
arm,shared-override;
|
||||
prefetch-data = <1>;
|
||||
|
|
@ -94,14 +102,37 @@ pmu {
|
|||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/* As long as we do not have a real clock driver us this
|
||||
* fixed clock */
|
||||
clk_periph: periph {
|
||||
compatible = "fixed-clock";
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <400000000>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
iprocmed: iprocmed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
iprocslow: iprocslow {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
periph_clk: periph_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&a9pll>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -178,6 +209,25 @@ chipcommon: chipcommon@0 {
|
|||
};
|
||||
};
|
||||
|
||||
lcpll0: lcpll0@1800c100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-lcpll0";
|
||||
reg = <0x1800c100 0x14>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "lcpll0", "pcie_phy", "sdio",
|
||||
"ddr_phy";
|
||||
};
|
||||
|
||||
genpll: genpll@1800c140 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-genpll";
|
||||
reg = <0x1800c140 0x24>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "genpll", "phy", "ethernetclk",
|
||||
"usbclk", "iprocfast", "sata1",
|
||||
"sata2";
|
||||
};
|
||||
|
||||
nand: nand@18028000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
||||
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
||||
|
|
|
|||
|
|
@ -43,18 +43,31 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
arm_timer_clk: arm_timer_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
/* UBUS peripheral clock */
|
||||
periph_clk: periph_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "periph";
|
||||
};
|
||||
|
||||
/* peripheral clock for system timer */
|
||||
axi_clk: axi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&armpll>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
/* APB bus clock */
|
||||
apb_clk: apb_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&armpll>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* ARM bus */
|
||||
|
|
@ -93,14 +106,14 @@ global_timer: timer@1e200 {
|
|||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x1e200 0x20>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
clocks = <&axi_clk>;
|
||||
};
|
||||
|
||||
local_timer: local-timer@1e600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1e600 0x20>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
clocks = <&axi_clk>;
|
||||
};
|
||||
|
||||
twd_watchdog: watchdog@1e620 {
|
||||
|
|
@ -109,6 +122,13 @@ twd_watchdog: watchdog@1e620 {
|
|||
interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
armpll: armpll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,bcm63138-armpll";
|
||||
clocks = <&periph_clk>;
|
||||
reg = <0x20000 0xf00>;
|
||||
};
|
||||
|
||||
pmb0: reset-controller@4800c0 {
|
||||
compatible = "brcm,bcm63138-pmb";
|
||||
reg = <0x4800c0 0x10>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NorthStar SVK (BCM94708)";
|
||||
compatible = "brcm,bcm94708", "brcm,bcm4708";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NorthStar SVK (BCM94709)";
|
||||
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NorthStar SVK (BCM953012K)";
|
||||
compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <62499840>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clock-frequency = <62499840>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -55,3 +55,62 @@ &uart0 {
|
|||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
nandcs@0 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand-ecc-strength = <24>;
|
||||
nand-ecc-step-size = <1024>;
|
||||
|
||||
brcm,nand-oob-sector-size = <27>;
|
||||
|
||||
partition@0 {
|
||||
label = "nboot";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
read-only;
|
||||
};
|
||||
partition@1 {
|
||||
label = "nenv";
|
||||
reg = <0x00200000 0x00400000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "nsystem";
|
||||
reg = <0x00600000 0x00a00000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "nrootfs";
|
||||
reg = <0x01000000 0x03000000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "ncustfs";
|
||||
reg = <0x04000000 0x3c000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_sel>;
|
||||
nand_sel: nand_sel {
|
||||
function = "nand";
|
||||
groups = "nand_grp";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
config CLK_BCM_63XX
|
||||
bool "Broadcom BCM63xx clock support"
|
||||
depends on ARCH_BCM_63XX || COMPILE_TEST
|
||||
depends on COMMON_CLK
|
||||
select COMMON_CLK_IPROC
|
||||
default ARCH_BCM_63XX
|
||||
help
|
||||
Enable common clock framework support for Broadcom BCM63xx DSL SoCs
|
||||
based on the ARM architecture
|
||||
|
||||
config CLK_BCM_KONA
|
||||
bool "Broadcom Kona CCU clock support"
|
||||
depends on ARCH_BCM_MOBILE || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
|
||||
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include "clk-iproc.h"
|
||||
|
||||
static void __init bcm63138_armpll_init(struct device_node *node)
|
||||
{
|
||||
iproc_armpll_setup(node);
|
||||
}
|
||||
CLK_OF_DECLARE(bcm63138_armpll, "brcm,bcm63138-armpll", bcm63138_armpll_init);
|
||||
Loading…
Reference in New Issue