mirror of https://gitee.com/openkylin/linux.git
iommu/amd: Convert dev_table_entry to u64
Convert the contents of 'struct dev_table_entry' to u64 to allow updating the DTE wit 64bit writes as required by the spec. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -365,8 +365,8 @@ static void dump_dte_entry(u16 devid)
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{
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int i;
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for (i = 0; i < 8; ++i)
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pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
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for (i = 0; i < 4; ++i)
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pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
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amd_iommu_dev_table[devid].data[i]);
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}
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@ -1583,19 +1583,22 @@ static bool dma_ops_domain(struct protection_domain *domain)
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static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
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{
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u64 pte_root = virt_to_phys(domain->pt_root);
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u32 flags = 0;
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u64 flags = 0;
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pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
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<< DEV_ENTRY_MODE_SHIFT;
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pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
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flags = amd_iommu_dev_table[devid].data[1];
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if (ats)
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flags |= DTE_FLAG_IOTLB;
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amd_iommu_dev_table[devid].data[3] |= flags;
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amd_iommu_dev_table[devid].data[2] = domain->id;
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amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
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amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
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flags &= ~(0xffffUL);
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flags |= domain->id;
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amd_iommu_dev_table[devid].data[1] = flags;
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amd_iommu_dev_table[devid].data[0] = pte_root;
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}
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static void clear_dte_entry(u16 devid)
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@ -1603,7 +1606,6 @@ static void clear_dte_entry(u16 devid)
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/* remove entry from the device table seen by the hardware */
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amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
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amd_iommu_dev_table[devid].data[1] = 0;
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amd_iommu_dev_table[devid].data[2] = 0;
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amd_iommu_apply_erratum_63(devid);
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}
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@ -584,18 +584,18 @@ static void __init free_event_buffer(struct amd_iommu *iommu)
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/* sets a specific bit in the device table entry. */
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static void set_dev_entry_bit(u16 devid, u8 bit)
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{
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int i = (bit >> 5) & 0x07;
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int _bit = bit & 0x1f;
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int i = (bit >> 6) & 0x03;
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int _bit = bit & 0x3f;
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amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
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amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
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}
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static int get_dev_entry_bit(u16 devid, u8 bit)
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{
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int i = (bit >> 5) & 0x07;
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int _bit = bit & 0x1f;
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int i = (bit >> 6) & 0x03;
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int _bit = bit & 0x3f;
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return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
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return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
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}
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@ -230,7 +230,7 @@
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#define IOMMU_PTE_IR (1ULL << 61)
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#define IOMMU_PTE_IW (1ULL << 62)
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#define DTE_FLAG_IOTLB 0x01
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#define DTE_FLAG_IOTLB (0x01UL << 32)
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#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
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@ -484,7 +484,7 @@ extern struct list_head amd_iommu_pd_list;
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* Structure defining one entry in the device table
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*/
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struct dev_table_entry {
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u32 data[8];
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u64 data[4];
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};
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/*
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