mirror of https://gitee.com/openkylin/linux.git
drm/i915: move find_pll callback to dev_priv->display
Now that the DP madness is cleared out, this is all only per-platform. So move it out from the intel clock limits structure. While at it drop the intel prefix on the static functions, call the vtable entry find_dpll (since it's for the display pll) and rip out the now unnecessary forward declarations. Note that the parameters of ->find_dpll are still unchanged, but they eventually need to be moved over to just take in a pipe configuration. But currently a lot of things are still missing from the pipe configuration (reflock, output-specific dpll limits and preferences, downclocked dotclock). So this will happen in a later step. Note that intel_g4x_limit has a peculiar case where it selects intel_limits_i9xx_sdvo as the limit. This is pretty bogus and also not used since the only output types left are DP and native TV-out which both use special pre-tuned dpll values. v2: Re-add comment for the find_pll callback (requested by Paulo) and elaborate on why the transformation is correct for g4x platforms (to clarify a review question from Paulo). Double up on that by adding a WARN as suggested by Paulo Zanoni on irc. v3: Initialize limits to NULL since gcc is now unhappy. v4: v2/3 will blow up with a NULL dereference in ->find_dpll for dp and TV-out ports, spotted by Paulo on irc. So just give up on this madness for now, and leave this to be fixed in a later patch. v5: Since the ever-so-slight change for g4x might result in some dpll parameter computation failing spuriously where before it didn't for ports with preset dpll settings (DP & TV-out) override this. For paranoia also do it in the ilk+ code. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
ac58c3f046
commit
ee9300bb5f
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@ -306,6 +306,8 @@ struct drm_i915_error_state {
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struct intel_crtc_config;
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struct intel_crtc;
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struct intel_limit;
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struct dpll;
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struct drm_i915_display_funcs {
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bool (*fbc_enabled)(struct drm_device *dev);
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@ -313,6 +315,24 @@ struct drm_i915_display_funcs {
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void (*disable_fbc)(struct drm_device *dev);
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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/**
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* find_dpll() - Find the best values for the PLL
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* @limit: limits for the PLL
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* @crtc: current CRTC
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* @target: target frequency in kHz
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* @refclk: reference clock frequency in kHz
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* @match_clock: if provided, @best_clock P divider must
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* match the P divider from @match_clock
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* used for LVDS downclocking
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* @best_clock: best PLL values found
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*
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* Returns true on success, false on failure.
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*/
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bool (*find_dpll)(const struct intel_limit *limit,
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struct drm_crtc *crtc,
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int target, int refclk,
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struct dpll *match_clock,
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struct dpll *best_clock);
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void (*update_wm)(struct drm_device *dev);
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void (*update_sprite_wm)(struct drm_device *dev, int pipe,
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uint32_t sprite_width, int pixel_size,
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@ -59,24 +59,6 @@ typedef struct intel_limit intel_limit_t;
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struct intel_limit {
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intel_range_t dot, vco, n, m, m1, m2, p, p1;
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intel_p2_t p2;
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/**
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* find_pll() - Find the best values for the PLL
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* @limit: limits for the PLL
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* @crtc: current CRTC
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* @target: target frequency in kHz
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* @refclk: reference clock frequency in kHz
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* @match_clock: if provided, @best_clock P divider must
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* match the P divider from @match_clock
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* used for LVDS downclocking
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* @best_clock: best PLL values found
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*
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* Returns true on success, false on failure.
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*/
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bool (*find_pll)(const intel_limit_t *limit,
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struct drm_crtc *crtc,
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int target, int refclk,
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intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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};
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/* FDI */
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@ -92,23 +74,6 @@ intel_pch_rawclk(struct drm_device *dev)
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return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
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}
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static bool
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intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static bool
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intel_pnv_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static bool
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intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static bool
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intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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static inline u32 /* units of 100MHz */
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intel_fdi_link_freq(struct drm_device *dev)
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{
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@ -130,7 +95,6 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
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.p1 = { .min = 2, .max = 33 },
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.p2 = { .dot_limit = 165000,
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.p2_slow = 4, .p2_fast = 2 },
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.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i8xx_lvds = {
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@ -144,7 +108,6 @@ static const intel_limit_t intel_limits_i8xx_lvds = {
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.p1 = { .min = 1, .max = 6 },
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.p2 = { .dot_limit = 165000,
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.p2_slow = 14, .p2_fast = 7 },
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.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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@ -158,7 +121,6 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 200000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_find_best_PLL,
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};
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static const intel_limit_t intel_limits_i9xx_lvds = {
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@ -172,7 +134,6 @@ static const intel_limit_t intel_limits_i9xx_lvds = {
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 112000,
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.p2_slow = 14, .p2_fast = 7 },
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.find_pll = intel_find_best_PLL,
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};
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@ -189,7 +150,6 @@ static const intel_limit_t intel_limits_g4x_sdvo = {
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.p2_slow = 10,
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.p2_fast = 10
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},
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_g4x_hdmi = {
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@ -203,7 +163,6 @@ static const intel_limit_t intel_limits_g4x_hdmi = {
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.p1 = { .min = 1, .max = 8},
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.p2 = { .dot_limit = 165000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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@ -218,7 +177,6 @@ static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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.p2 = { .dot_limit = 0,
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.p2_slow = 14, .p2_fast = 14
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},
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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@ -233,7 +191,6 @@ static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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.p2 = { .dot_limit = 0,
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.p2_slow = 7, .p2_fast = 7
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},
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_pineview_sdvo = {
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@ -249,7 +206,6 @@ static const intel_limit_t intel_limits_pineview_sdvo = {
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 200000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_pnv_find_best_PLL,
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};
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static const intel_limit_t intel_limits_pineview_lvds = {
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@ -263,7 +219,6 @@ static const intel_limit_t intel_limits_pineview_lvds = {
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 112000,
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.p2_slow = 14, .p2_fast = 14 },
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.find_pll = intel_pnv_find_best_PLL,
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};
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/* Ironlake / Sandybridge
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@ -282,7 +237,6 @@ static const intel_limit_t intel_limits_ironlake_dac = {
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_ironlake_single_lvds = {
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@ -296,7 +250,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
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.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 14, .p2_fast = 14 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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@ -310,7 +263,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 7, .p2_fast = 7 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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/* LVDS 100mhz refclk limits. */
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@ -325,7 +277,6 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
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.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 14, .p2_fast = 14 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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@ -339,7 +290,6 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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.p1 = { .min = 2, .max = 6 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 7, .p2_fast = 7 },
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.find_pll = intel_g4x_find_best_PLL,
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};
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static const intel_limit_t intel_limits_vlv_dac = {
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@ -353,7 +303,6 @@ static const intel_limit_t intel_limits_vlv_dac = {
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.p1 = { .min = 1, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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static const intel_limit_t intel_limits_vlv_hdmi = {
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@ -367,7 +316,6 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
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.p1 = { .min = 2, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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static const intel_limit_t intel_limits_vlv_dp = {
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@ -381,7 +329,6 @@ static const intel_limit_t intel_limits_vlv_dp = {
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.p1 = { .min = 1, .max = 3 },
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.p2 = { .dot_limit = 270000,
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.p2_slow = 2, .p2_fast = 20 },
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.find_pll = intel_vlv_find_best_pll,
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};
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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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@ -537,7 +484,7 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
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}
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static bool
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intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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@ -599,9 +546,9 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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}
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static bool
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intel_pnv_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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intel_clock_t clock;
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@ -661,9 +608,9 @@ intel_pnv_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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}
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static bool
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intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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intel_clock_t clock;
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@ -718,9 +665,9 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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}
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static bool
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intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock)
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{
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u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
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u32 m, n, fastclk;
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@ -4911,9 +4858,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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limit = intel_limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
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&clock);
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if (!ok) {
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ok = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
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refclk, NULL, &clock);
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if (!ok && !intel_crtc->config.clock_set) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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@ -4928,10 +4875,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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* by using the FP0/FP1. In such case we will disable the LVDS
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* downclock feature.
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*/
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has_reduced_clock = limit->find_pll(limit, crtc,
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has_reduced_clock =
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dev_priv->display.find_dpll(limit, crtc,
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dev_priv->lvds_downclock,
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refclk,
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&clock,
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refclk, &clock,
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&reduced_clock);
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}
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/* Compat-code for transition, will disappear. */
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@ -5547,8 +5494,8 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
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*/
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limit = intel_limit(crtc, refclk);
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ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
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clock);
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ret = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
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refclk, NULL, clock);
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if (!ret)
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return false;
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@ -5559,11 +5506,11 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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* by using the FP0/FP1. In such case we will disable the LVDS
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* downclock feature.
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*/
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*has_reduced_clock = limit->find_pll(limit, crtc,
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dev_priv->lvds_downclock,
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refclk,
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clock,
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reduced_clock);
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*has_reduced_clock =
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dev_priv->display.find_dpll(limit, crtc,
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dev_priv->lvds_downclock,
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refclk, clock,
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reduced_clock);
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}
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return true;
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@ -5749,7 +5696,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock, &reduced_clock);
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if (!ok) {
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if (!ok && !intel_crtc->config.clock_set) {
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DRM_ERROR("Couldn't find PLL settings for mode!\n");
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return -EINVAL;
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}
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@ -9073,6 +9020,15 @@ static void intel_init_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
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dev_priv->display.find_dpll = g4x_find_best_dpll;
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else if (IS_VALLEYVIEW(dev))
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dev_priv->display.find_dpll = vlv_find_best_dpll;
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else if (IS_PINEVIEW(dev))
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dev_priv->display.find_dpll = pnv_find_best_dpll;
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else
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dev_priv->display.find_dpll = i9xx_find_best_dpll;
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if (HAS_DDI(dev)) {
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dev_priv->display.get_pipe_config = haswell_get_pipe_config;
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dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
|
||||
|
|
|
|||
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Reference in New Issue