mirror of https://gitee.com/openkylin/linux.git
ARM: dts: qcom: Fix 'interrupts = <>' property to use proper macros
Fix all nodes to use proper GIC_* macros for the interrupt type and the interrupt trigger settings to avoid the boot warnings. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Sricharan R
Andy Gross
parent
ce397d215c
commit
eea7f21b1e
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@ -5,6 +5,7 @@
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm IPQ8064";
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@ -43,7 +44,8 @@ L2: l2-cache {
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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interrupts = <1 10 0x304>;
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interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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reserved-memory {
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@ -97,7 +99,7 @@ lpass@28100000 {
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clock-names = "ahbix-clk",
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"mi2s-osr-clk",
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"mi2s-bit-clk";
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interrupts = <0 85 1>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "lpass-irq-lpaif";
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reg = <0x28100000 0x10000>;
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reg-names = "lpass-lpaif";
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@ -111,7 +113,7 @@ qcom_pinmux: pinmux@800000 {
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 0x4>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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intc: interrupt-controller@2000000 {
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@ -125,11 +127,16 @@ intc: interrupt-controller@2000000 {
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timer@200a000 {
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compatible = "qcom,kpss-timer",
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"qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>,
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<1 4 0x301>,
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<1 5 0x301>;
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>,
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<32768>;
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@ -177,7 +184,7 @@ serial@12490000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12490000 0x1000>,
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<0x12480000 0x1000>;
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interrupts = <0 195 0x0>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -186,7 +193,7 @@ serial@12490000 {
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i2c@124a0000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x124a0000 0x1000>;
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interrupts = <0 196 0>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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@ -215,7 +222,7 @@ gsbi4_serial: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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<0x16300000 0x1000>;
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interrupts = <0 152 0x0>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -224,7 +231,7 @@ gsbi4_serial: serial@16340000 {
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i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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@ -252,7 +259,7 @@ serial@1a240000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a240000 0x1000>,
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<0x1a200000 0x1000>;
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interrupts = <0 154 0x0>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -261,7 +268,7 @@ serial@1a240000 {
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i2c@1a280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x1a280000 0x1000>;
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interrupts = <0 155 0>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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@ -274,7 +281,7 @@ i2c@1a280000 {
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spi@1a280000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x1a280000 0x1000>;
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interrupts = <0 155 0>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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@ -301,7 +308,7 @@ gsbi7_serial: serial@16640000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <0 158 0x0>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -323,7 +330,7 @@ sata@29000000 {
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compatible = "qcom,ipq806x-ahci", "generic-ahci";
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reg = <0x29000000 0x180>;
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interrupts = <0 209 0x0>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SFAB_SATA_S_H_CLK>,
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<&gcc SATA_H_CLK>,
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