mirror of https://gitee.com/openkylin/linux.git
netdev: octeon_mgmt: Add support for 1Gig ports.
The original hardware only supported 10M and 100M. Later versions added 1G support. Here we update the driver to make use of this. Also minor logic clean-ups for testing PHY registration error codes and TX complete high water marks. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David Daney
parent
70a26a219c
commit
eeae05aa21
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Cavium Networks
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* Copyright (C) 2009-2012 Cavium, Inc
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*/
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#include <linux/platform_device.h>
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@ -93,6 +93,7 @@ union mgmt_port_ring_entry {
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#define AGL_GMX_RX_ADR_CAM4 0x1a0
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#define AGL_GMX_RX_ADR_CAM5 0x1a8
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#define AGL_GMX_TX_CLK 0x208
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#define AGL_GMX_TX_STATS_CTL 0x268
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#define AGL_GMX_TX_CTL 0x270
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#define AGL_GMX_TX_STAT0 0x280
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@ -110,6 +111,7 @@ struct octeon_mgmt {
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struct net_device *netdev;
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u64 mix;
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u64 agl;
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u64 agl_prt_ctl;
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int port;
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int irq;
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u64 *tx_ring;
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@ -131,6 +133,7 @@ struct octeon_mgmt {
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spinlock_t lock;
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unsigned int last_duplex;
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unsigned int last_link;
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unsigned int last_speed;
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struct device *dev;
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struct napi_struct napi;
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struct tasklet_struct tx_clean_tasklet;
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@ -140,6 +143,8 @@ struct octeon_mgmt {
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resource_size_t mix_size;
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resource_size_t agl_phys;
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resource_size_t agl_size;
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resource_size_t agl_prt_ctl_phys;
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resource_size_t agl_prt_ctl_size;
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};
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static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
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@ -488,7 +493,7 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
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mix_ctl.s.reset = 1;
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cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
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cvmx_read_csr(p->mix + MIX_CTL);
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cvmx_wait(64);
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octeon_io_clk_delay(64);
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mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);
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if (mix_bist.u64)
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@ -670,39 +675,148 @@ static int octeon_mgmt_ioctl(struct net_device *netdev,
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return phy_mii_ioctl(p->phydev, rq, cmd);
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}
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static void octeon_mgmt_disable_link(struct octeon_mgmt *p)
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{
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union cvmx_agl_gmx_prtx_cfg prtx_cfg;
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/* Disable GMX before we make any changes. */
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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prtx_cfg.s.en = 0;
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prtx_cfg.s.tx_en = 0;
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prtx_cfg.s.rx_en = 0;
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cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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int i;
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for (i = 0; i < 10; i++) {
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1)
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break;
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mdelay(1);
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i++;
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}
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}
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}
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static void octeon_mgmt_enable_link(struct octeon_mgmt *p)
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{
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union cvmx_agl_gmx_prtx_cfg prtx_cfg;
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/* Restore the GMX enable state only if link is set */
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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prtx_cfg.s.tx_en = 1;
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prtx_cfg.s.rx_en = 1;
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prtx_cfg.s.en = 1;
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cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
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}
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static void octeon_mgmt_update_link(struct octeon_mgmt *p)
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{
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union cvmx_agl_gmx_prtx_cfg prtx_cfg;
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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if (!p->phydev->link)
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prtx_cfg.s.duplex = 1;
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else
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prtx_cfg.s.duplex = p->phydev->duplex;
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switch (p->phydev->speed) {
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case 10:
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prtx_cfg.s.speed = 0;
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prtx_cfg.s.slottime = 0;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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prtx_cfg.s.burst = 1;
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prtx_cfg.s.speed_msb = 1;
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}
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break;
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case 100:
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prtx_cfg.s.speed = 0;
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prtx_cfg.s.slottime = 0;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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prtx_cfg.s.burst = 1;
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prtx_cfg.s.speed_msb = 0;
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}
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break;
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case 1000:
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/* 1000 MBits is only supported on 6XXX chips */
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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prtx_cfg.s.speed = 1;
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prtx_cfg.s.speed_msb = 0;
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/* Only matters for half-duplex */
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prtx_cfg.s.slottime = 1;
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prtx_cfg.s.burst = p->phydev->duplex;
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}
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break;
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case 0: /* No link */
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default:
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break;
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}
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/* Write the new GMX setting with the port still disabled. */
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cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
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/* Read GMX CFG again to make sure the config is completed. */
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
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union cvmx_agl_gmx_txx_clk agl_clk;
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union cvmx_agl_prtx_ctl prtx_ctl;
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prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
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agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK);
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/* MII (both speeds) and RGMII 1000 speed. */
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agl_clk.s.clk_cnt = 1;
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if (prtx_ctl.s.mode == 0) { /* RGMII mode */
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if (p->phydev->speed == 10)
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agl_clk.s.clk_cnt = 50;
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else if (p->phydev->speed == 100)
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agl_clk.s.clk_cnt = 5;
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}
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cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);
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}
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}
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static void octeon_mgmt_adjust_link(struct net_device *netdev)
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{
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struct octeon_mgmt *p = netdev_priv(netdev);
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union cvmx_agl_gmx_prtx_cfg prtx_cfg;
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unsigned long flags;
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int link_changed = 0;
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if (!p->phydev)
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return;
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spin_lock_irqsave(&p->lock, flags);
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if (p->phydev->link) {
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if (!p->last_link)
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link_changed = 1;
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if (p->last_duplex != p->phydev->duplex) {
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p->last_duplex = p->phydev->duplex;
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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prtx_cfg.s.duplex = p->phydev->duplex;
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cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
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}
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} else {
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if (p->last_link)
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link_changed = -1;
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if (!p->phydev->link && p->last_link)
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link_changed = -1;
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if (p->phydev->link
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&& (p->last_duplex != p->phydev->duplex
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|| p->last_link != p->phydev->link
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|| p->last_speed != p->phydev->speed)) {
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octeon_mgmt_disable_link(p);
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link_changed = 1;
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octeon_mgmt_update_link(p);
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octeon_mgmt_enable_link(p);
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}
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p->last_link = p->phydev->link;
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p->last_speed = p->phydev->speed;
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p->last_duplex = p->phydev->duplex;
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spin_unlock_irqrestore(&p->lock, flags);
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if (link_changed != 0) {
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if (link_changed > 0) {
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netif_carrier_on(netdev);
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pr_info("%s: Link is up - %d/%s\n", netdev->name,
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p->phydev->speed,
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DUPLEX_FULL == p->phydev->duplex ?
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"Full" : "Half");
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} else {
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netif_carrier_off(netdev);
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pr_info("%s: Link is down\n", netdev->name);
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}
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}
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@ -722,12 +836,8 @@ static int octeon_mgmt_init_phy(struct net_device *netdev)
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octeon_mgmt_adjust_link, 0,
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PHY_INTERFACE_MODE_MII);
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if (IS_ERR(p->phydev)) {
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p->phydev = NULL;
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return -1;
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}
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phy_start_aneg(p->phydev);
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if (p->phydev == NULL)
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return -ENODEV;
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return 0;
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}
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@ -735,12 +845,10 @@ static int octeon_mgmt_init_phy(struct net_device *netdev)
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static int octeon_mgmt_open(struct net_device *netdev)
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{
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struct octeon_mgmt *p = netdev_priv(netdev);
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int port = p->port;
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union cvmx_mixx_ctl mix_ctl;
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union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
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union cvmx_mixx_oring1 oring1;
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union cvmx_mixx_iring1 iring1;
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union cvmx_agl_gmx_prtx_cfg prtx_cfg;
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union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
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union cvmx_mixx_irhwm mix_irhwm;
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union cvmx_mixx_orhwm mix_orhwm;
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@ -787,9 +895,31 @@ static int octeon_mgmt_open(struct net_device *netdev)
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} while (mix_ctl.s.reset);
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}
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agl_gmx_inf_mode.u64 = 0;
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agl_gmx_inf_mode.s.en = 1;
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cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
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agl_gmx_inf_mode.u64 = 0;
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agl_gmx_inf_mode.s.en = 1;
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cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
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}
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if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
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/*
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* Force compensation values, as they are not
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* determined properly by HW
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*/
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union cvmx_agl_gmx_drv_ctl drv_ctl;
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drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
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if (p->port) {
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drv_ctl.s.byp_en1 = 1;
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drv_ctl.s.nctl1 = 6;
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drv_ctl.s.pctl1 = 6;
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} else {
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drv_ctl.s.byp_en = 1;
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drv_ctl.s.nctl = 6;
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drv_ctl.s.pctl = 6;
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}
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cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
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}
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oring1.u64 = 0;
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oring1.s.obase = p->tx_ring_handle >> 3;
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@ -801,11 +931,6 @@ static int octeon_mgmt_open(struct net_device *netdev)
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iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
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cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);
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/* Disable packet I/O. */
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prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
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prtx_cfg.s.en = 0;
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cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
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memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
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octeon_mgmt_set_mac_address(netdev, &sa);
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@ -821,27 +946,70 @@ static int octeon_mgmt_open(struct net_device *netdev)
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mix_ctl.s.nbtarb = 0; /* Arbitration mode */
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/* MII CB-request FIFO programmable high watermark */
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mix_ctl.s.mrq_hwm = 1;
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#ifdef __LITTLE_ENDIAN
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mix_ctl.s.lendian = 1;
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#endif
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cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
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if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
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|| OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
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/*
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* Force compensation values, as they are not
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* determined properly by HW
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*/
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union cvmx_agl_gmx_drv_ctl drv_ctl;
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/* Read the PHY to find the mode of the interface. */
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if (octeon_mgmt_init_phy(netdev)) {
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dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port);
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goto err_noirq;
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}
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drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
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if (port) {
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drv_ctl.s.byp_en1 = 1;
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drv_ctl.s.nctl1 = 6;
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drv_ctl.s.pctl1 = 6;
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} else {
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drv_ctl.s.byp_en = 1;
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drv_ctl.s.nctl = 6;
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drv_ctl.s.pctl = 6;
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/* Set the mode of the interface, RGMII/MII. */
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && p->phydev) {
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union cvmx_agl_prtx_ctl agl_prtx_ctl;
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int rgmii_mode = (p->phydev->supported &
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(SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) != 0;
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agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
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agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1;
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cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
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/* MII clocks counts are based on the 125Mhz
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* reference, which has an 8nS period. So our delays
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* need to be multiplied by this factor.
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*/
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#define NS_PER_PHY_CLK 8
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/* Take the DLL and clock tree out of reset */
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agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
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agl_prtx_ctl.s.clkrst = 0;
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if (rgmii_mode) {
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agl_prtx_ctl.s.dllrst = 0;
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agl_prtx_ctl.s.clktx_byp = 0;
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}
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cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
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cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
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cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */
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/* Wait for the DLL to lock. External 125 MHz
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* reference clock must be stable at this point.
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*/
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ndelay(256 * NS_PER_PHY_CLK);
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/* Enable the interface */
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agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
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agl_prtx_ctl.s.enable = 1;
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cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
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/* Read the value back to force the previous write */
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agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
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/* Enable the compensation controller */
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agl_prtx_ctl.s.comp = 1;
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agl_prtx_ctl.s.drv_byp = 0;
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cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
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/* Force write out before wait. */
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cvmx_read_csr(p->agl_prt_ctl);
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/* For compensation state to lock. */
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ndelay(1040 * NS_PER_PHY_CLK);
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/* Some Ethernet switches cannot handle standard
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* Interframe Gap, increase to 16 bytes.
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*/
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cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0x88);
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}
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octeon_mgmt_rx_fill_ring(netdev);
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@ -872,7 +1040,7 @@ static int octeon_mgmt_open(struct net_device *netdev)
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/* Interrupt when we have 1 or more packets to clean. */
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mix_orhwm.u64 = 0;
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mix_orhwm.s.orhwm = 1;
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mix_orhwm.s.orhwm = 0;
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cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);
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/* Enable receive and transmit interrupts */
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@ -881,7 +1049,6 @@ static int octeon_mgmt_open(struct net_device *netdev)
|
|||
mix_intena.s.othena = 1;
|
||||
cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
|
||||
|
||||
|
||||
/* Enable packet I/O. */
|
||||
|
||||
rxx_frm_ctl.u64 = 0;
|
||||
|
|
@ -912,26 +1079,20 @@ static int octeon_mgmt_open(struct net_device *netdev)
|
|||
rxx_frm_ctl.s.pre_chk = 1;
|
||||
cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
|
||||
|
||||
/* Enable the AGL block */
|
||||
agl_gmx_inf_mode.u64 = 0;
|
||||
agl_gmx_inf_mode.s.en = 1;
|
||||
cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
|
||||
|
||||
/* Configure the port duplex and enables */
|
||||
prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
|
||||
prtx_cfg.s.tx_en = 1;
|
||||
prtx_cfg.s.rx_en = 1;
|
||||
prtx_cfg.s.en = 1;
|
||||
p->last_duplex = 1;
|
||||
prtx_cfg.s.duplex = p->last_duplex;
|
||||
cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
|
||||
/* Configure the port duplex, speed and enables */
|
||||
octeon_mgmt_disable_link(p);
|
||||
if (p->phydev)
|
||||
octeon_mgmt_update_link(p);
|
||||
octeon_mgmt_enable_link(p);
|
||||
|
||||
p->last_link = 0;
|
||||
netif_carrier_off(netdev);
|
||||
|
||||
if (octeon_mgmt_init_phy(netdev)) {
|
||||
dev_err(p->dev, "Cannot initialize PHY.\n");
|
||||
goto err_noirq;
|
||||
p->last_speed = 0;
|
||||
/* PHY is not present in simulator. The carrier is enabled
|
||||
* while initializing the phy for simulator, leave it enabled.
|
||||
*/
|
||||
if (p->phydev) {
|
||||
netif_carrier_off(netdev);
|
||||
phy_start_aneg(p->phydev);
|
||||
}
|
||||
|
||||
netif_wake_queue(netdev);
|
||||
|
|
@ -961,6 +1122,7 @@ static int octeon_mgmt_stop(struct net_device *netdev)
|
|||
|
||||
if (p->phydev)
|
||||
phy_disconnect(p->phydev);
|
||||
p->phydev = NULL;
|
||||
|
||||
netif_carrier_off(netdev);
|
||||
|
||||
|
|
@ -1033,6 +1195,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
|
|||
/* Ring the bell. */
|
||||
cvmx_write_csr(p->mix + MIX_ORING2, 1);
|
||||
|
||||
netdev->trans_start = jiffies;
|
||||
rv = NETDEV_TX_OK;
|
||||
out:
|
||||
octeon_mgmt_update_tx_stats(netdev);
|
||||
|
|
@ -1098,9 +1261,9 @@ static const struct net_device_ops octeon_mgmt_ops = {
|
|||
.ndo_open = octeon_mgmt_open,
|
||||
.ndo_stop = octeon_mgmt_stop,
|
||||
.ndo_start_xmit = octeon_mgmt_xmit,
|
||||
.ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
|
||||
.ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
|
||||
.ndo_set_mac_address = octeon_mgmt_set_mac_address,
|
||||
.ndo_do_ioctl = octeon_mgmt_ioctl,
|
||||
.ndo_do_ioctl = octeon_mgmt_ioctl,
|
||||
.ndo_change_mtu = octeon_mgmt_change_mtu,
|
||||
#ifdef CONFIG_NET_POLL_CONTROLLER
|
||||
.ndo_poll_controller = octeon_mgmt_poll_controller,
|
||||
|
|
@ -1115,6 +1278,7 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
|
|||
const u8 *mac;
|
||||
struct resource *res_mix;
|
||||
struct resource *res_agl;
|
||||
struct resource *res_agl_prt_ctl;
|
||||
int len;
|
||||
int result;
|
||||
|
||||
|
|
@ -1161,10 +1325,19 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
|
|||
goto err;
|
||||
}
|
||||
|
||||
res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3);
|
||||
if (res_agl_prt_ctl == NULL) {
|
||||
dev_err(&pdev->dev, "no 'reg' resource\n");
|
||||
result = -ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
p->mix_phys = res_mix->start;
|
||||
p->mix_size = resource_size(res_mix);
|
||||
p->agl_phys = res_agl->start;
|
||||
p->agl_size = resource_size(res_agl);
|
||||
p->agl_prt_ctl_phys = res_agl_prt_ctl->start;
|
||||
p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl);
|
||||
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size,
|
||||
|
|
@ -1183,10 +1356,18 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
|
|||
goto err;
|
||||
}
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys,
|
||||
p->agl_prt_ctl_size, res_agl_prt_ctl->name)) {
|
||||
result = -ENXIO;
|
||||
dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
|
||||
res_agl_prt_ctl->name);
|
||||
goto err;
|
||||
}
|
||||
|
||||
p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);
|
||||
p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);
|
||||
|
||||
p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys,
|
||||
p->agl_prt_ctl_size);
|
||||
spin_lock_init(&p->lock);
|
||||
|
||||
skb_queue_head_init(&p->tx_list);
|
||||
|
|
@ -1209,6 +1390,7 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
|
|||
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
netif_carrier_off(netdev);
|
||||
result = register_netdev(netdev);
|
||||
if (result)
|
||||
goto err;
|
||||
|
|
|
|||
Loading…
Reference in New Issue