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drm/i915: Remove LVDS and PPS suspend time save/restore 

In the preceding patches we made sure that:
- the LVDS encoder takes care of reiniting both the LVDS register
and its PPS
- the eDP encoder takes care of reiniting its PPS
- the PPS register unlocking workaround is applied explicitly whenever
the PPS context is lost

Based on the above we can safely remove the opaque LVDS and PPS save /
restore from generic code.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470827254-21954-6-git-send-email-imre.deak@intel.com
This commit is contained in:
Imre Deak 2016-08-10 14:07:34 +03:00
parent 8090ba8c21
commit eebb40e081
2 changed files with 0 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1061,13 +1061,6 @@ struct intel_gmbus {
struct i915_suspend_saved_registers { struct i915_suspend_saved_registers {
u32 saveDSPARB; u32 saveDSPARB;
u32 saveLVDS;
u32 savePP_ON_DELAYS;
u32 savePP_OFF_DELAYS;
u32 savePP_ON;
u32 savePP_OFF;
u32 savePP_CONTROL;
u32 savePP_DIVISOR;
u32 saveFBC_CONTROL; u32 saveFBC_CONTROL;
u32 saveCACHE_MODE_0; u32 saveCACHE_MODE_0;
u32 saveMI_ARB_STATE; u32 saveMI_ARB_STATE;

31
drivers/gpu/drm/i915/i915_suspend.c
View File

@ -37,20 +37,6 @@ static void i915_save_display(struct drm_device *dev)
if (INTEL_INFO(dev)->gen <= 4) if (INTEL_INFO(dev)->gen <= 4)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
/* LVDS state */
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.saveLVDS = I915_READ(LVDS);
/* Panel power sequencer */
if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL(0));
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS(0));
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS(0));
dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR(0));
}
/* save FBC interval */ /* save FBC interval */
if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
@ -59,28 +45,11 @@ static void i915_save_display(struct drm_device *dev)
static void i915_restore_display(struct drm_device *dev) static void i915_restore_display(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
u32 mask = 0xffffffff;
/* Display arbitration */ /* Display arbitration */
if (INTEL_INFO(dev)->gen <= 4) if (INTEL_INFO(dev)->gen <= 4)
I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
mask = ~LVDS_PORT_EN;
/* LVDS state */
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
/* Panel power sequencer */
if (HAS_PCH_SPLIT(dev_priv) || INTEL_GEN(dev_priv) <= 4) {
I915_WRITE(PP_ON_DELAYS(0), dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS(0), dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PP_DIVISOR(0), dev_priv->regfile.savePP_DIVISOR);
I915_WRITE(PP_CONTROL(0), dev_priv->regfile.savePP_CONTROL);
}
/* only restore FBC info on the platform that supports FBC*/ /* only restore FBC info on the platform that supports FBC*/
intel_fbc_global_disable(dev_priv); intel_fbc_global_disable(dev_priv);