mirror of https://gitee.com/openkylin/linux.git
microblaze_v8: Interrupt handling and timer support
Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Reviewed-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
3be100114a
commit
eedbdab99f
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@ -0,0 +1,47 @@
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/*
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASM_MICROBLAZE_IRQ_H
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#define _ASM_MICROBLAZE_IRQ_H
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#define NR_IRQS 32
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#include <linux/interrupt.h>
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extern unsigned int nr_irq;
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#define NO_IRQ (-1)
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static inline int irq_canonicalize(int irq)
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{
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return irq;
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}
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struct pt_regs;
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extern void do_IRQ(struct pt_regs *regs);
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/* irq_of_parse_and_map - Parse and Map an interrupt into linux virq space
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* @device: Device node of the device whose interrupt is to be mapped
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* @index: Index of the interrupt to map
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*
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* This function is a wrapper that chains of_irq_map_one() and
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* irq_create_of_mapping() to make things easier to callers
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*/
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struct device_node;
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extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
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/** FIXME - not implement
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* irq_dispose_mapping - Unmap an interrupt
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* @virq: linux virq number of the interrupt to unmap
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*/
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static inline void irq_dispose_mapping(unsigned int virq)
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{
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return;
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}
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#endif /* _ASM_MICROBLAZE_IRQ_H */
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@ -0,0 +1,172 @@
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/page.h>
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#include <linux/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#ifdef CONFIG_SELFMOD_INTC
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#include <asm/selfmod.h>
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#define INTC_BASE BARRIER_BASE_ADDR
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#else
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static unsigned int intc_baseaddr;
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#define INTC_BASE intc_baseaddr
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#endif
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unsigned int nr_irq;
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/* No one else should require these constants, so define them locally here. */
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#define ISR 0x00 /* Interrupt Status Register */
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#define IPR 0x04 /* Interrupt Pending Register */
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#define IER 0x08 /* Interrupt Enable Register */
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#define IAR 0x0c /* Interrupt Acknowledge Register */
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#define SIE 0x10 /* Set Interrupt Enable bits */
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#define CIE 0x14 /* Clear Interrupt Enable bits */
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#define IVR 0x18 /* Interrupt Vector Register */
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#define MER 0x1c /* Master Enable Register */
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#define MER_ME (1<<0)
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#define MER_HIE (1<<1)
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static void intc_enable_or_unmask(unsigned int irq)
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{
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pr_debug("enable_or_unmask: %d\n", irq);
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out_be32(INTC_BASE + SIE, 1 << irq);
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}
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static void intc_disable_or_mask(unsigned int irq)
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{
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pr_debug("disable: %d\n", irq);
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out_be32(INTC_BASE + CIE, 1 << irq);
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}
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static void intc_ack(unsigned int irq)
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{
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pr_debug("ack: %d\n", irq);
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out_be32(INTC_BASE + IAR, 1 << irq);
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}
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static void intc_mask_ack(unsigned int irq)
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{
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unsigned long mask = 1 << irq;
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pr_debug("disable_and_ack: %d\n", irq);
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out_be32(INTC_BASE + CIE, mask);
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out_be32(INTC_BASE + IAR, mask);
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}
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static void intc_end(unsigned int irq)
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{
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unsigned long mask = 1 << irq;
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pr_debug("end: %d\n", irq);
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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out_be32(INTC_BASE + SIE, mask);
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/* ack level sensitive intr */
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if (irq_desc[irq].status & IRQ_LEVEL)
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out_be32(INTC_BASE + IAR, mask);
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}
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}
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static struct irq_chip intc_dev = {
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.name = "Xilinx INTC",
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.unmask = intc_enable_or_unmask,
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.mask = intc_disable_or_mask,
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.ack = intc_ack,
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.mask_ack = intc_mask_ack,
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.end = intc_end,
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};
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unsigned int get_irq(struct pt_regs *regs)
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{
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int irq;
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/*
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* NOTE: This function is the one that needs to be improved in
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* order to handle multiple interrupt controllers. It currently
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* is hardcoded to check for interrupts only on the first INTC.
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*/
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irq = in_be32(INTC_BASE + IVR);
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pr_debug("get_irq: %d\n", irq);
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return irq;
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}
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void __init init_IRQ(void)
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{
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u32 i, j, intr_type;
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struct device_node *intc = NULL;
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#ifdef CONFIG_SELFMOD_INTC
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unsigned int intc_baseaddr = 0;
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static int arr_func[] = {
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(int)&get_irq,
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(int)&intc_enable_or_unmask,
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(int)&intc_disable_or_mask,
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(int)&intc_mask_ack,
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(int)&intc_ack,
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(int)&intc_end,
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0
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};
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#endif
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static char *intc_list[] = {
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"xlnx,xps-intc-1.00.a",
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"xlnx,opb-intc-1.00.c",
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"xlnx,opb-intc-1.00.b",
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"xlnx,opb-intc-1.00.a",
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NULL
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};
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for (j = 0; intc_list[j] != NULL; j++) {
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intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
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if (intc)
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break;
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}
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intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
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intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
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nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL);
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intr_type =
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*(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL);
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if (intr_type >= (1 << nr_irq))
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printk(KERN_INFO " ERROR: Mishmash in king-of-intr param\n");
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#ifdef CONFIG_SELFMOD_INTC
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selfmod_function((int *) arr_func, intc_baseaddr);
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#endif
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printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
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intc_list[j], intc_baseaddr, nr_irq, intr_type);
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/*
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* Disable all external interrupts until they are
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* explicity requested.
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*/
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out_be32(intc_baseaddr + IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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out_be32(intc_baseaddr + IAR, 0xffffffff);
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/* Turn on the Master Enable. */
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out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
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for (i = 0; i < nr_irq; ++i) {
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if (intr_type & (0x00000001 << i)) {
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set_irq_chip_and_handler_name(i, &intc_dev,
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handle_edge_irq, intc_dev.name);
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irq_desc[i].status &= ~IRQ_LEVEL;
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} else {
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set_irq_chip_and_handler_name(i, &intc_dev,
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handle_level_irq, intc_dev.name);
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irq_desc[i].status |= IRQ_LEVEL;
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}
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}
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}
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@ -0,0 +1,104 @@
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/hardirq.h>
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#include <linux/interrupt.h>
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#include <linux/irqflags.h>
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#include <linux/seq_file.h>
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#include <linux/kernel_stat.h>
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#include <linux/irq.h>
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#include <asm/prom.h>
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unsigned int irq_of_parse_and_map(struct device_node *dev, int index)
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{
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struct of_irq oirq;
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if (of_irq_map_one(dev, index, &oirq))
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return NO_IRQ;
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return oirq.specifier[0];
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}
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EXPORT_SYMBOL_GPL(irq_of_parse_and_map);
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
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}
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static u32 concurrent_irq;
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void do_IRQ(struct pt_regs *regs)
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{
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unsigned int irq;
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struct pt_regs *old_regs = set_irq_regs(regs);
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irq_enter();
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irq = get_irq(regs);
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next_irq:
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BUG_ON(irq == -1U);
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generic_handle_irq(irq);
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irq = get_irq(regs);
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if (irq != -1U) {
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pr_debug("next irq: %d\n", irq);
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++concurrent_irq;
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goto next_irq;
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}
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irq_exit();
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set_irq_regs(old_regs);
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}
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j;
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struct irqaction *action;
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unsigned long flags;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%-8d", j);
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seq_putc(p, '\n');
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}
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if (i < nr_irq) {
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spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ", i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
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#endif
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seq_printf(p, " %8s", irq_desc[i].status &
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IRQ_LEVEL ? "level" : "edge");
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seq_printf(p, " %8s", irq_desc[i].chip->name);
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seq_printf(p, " %s", action->name);
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for (action = action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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}
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return 0;
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}
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@ -0,0 +1,262 @@
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/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/interrupt.h>
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#include <linux/profile.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/cpuinfo.h>
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#include <asm/setup.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#ifdef CONFIG_SELFMOD_TIMER
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#include <asm/selfmod.h>
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#define TIMER_BASE BARRIER_BASE_ADDR
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#else
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static unsigned int timer_baseaddr;
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#define TIMER_BASE timer_baseaddr
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#endif
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#define TCSR0 (0x00)
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#define TLR0 (0x04)
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#define TCR0 (0x08)
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#define TCSR1 (0x10)
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#define TLR1 (0x14)
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#define TCR1 (0x18)
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#define TCSR_MDT (1<<0)
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#define TCSR_UDT (1<<1)
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#define TCSR_GENT (1<<2)
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#define TCSR_CAPT (1<<3)
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#define TCSR_ARHT (1<<4)
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#define TCSR_LOAD (1<<5)
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#define TCSR_ENIT (1<<6)
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#define TCSR_ENT (1<<7)
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#define TCSR_TINT (1<<8)
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#define TCSR_PWMA (1<<9)
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#define TCSR_ENALL (1<<10)
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static inline void microblaze_timer0_stop(void)
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{
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out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
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}
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static inline void microblaze_timer0_start_periodic(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
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/* load the initial value */
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out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
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/* see timer data sheet for detail
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* !ENALL - don't enable 'em all
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* !PWMA - disable pwm
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* TINT - clear interrupt status
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* ENT- enable timer itself
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* EINT - enable interrupt
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* !LOAD - clear the bit to let go
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* ARHT - auto reload
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* !CAPT - no external trigger
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* !GENT - no external signal
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* UDT - set the timer as down counter
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* !MDT0 - generate mode
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*/
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out_be32(TIMER_BASE + TCSR0,
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TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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}
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static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
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/* load the initial value */
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out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
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out_be32(TIMER_BASE + TCSR0,
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TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
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}
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static int microblaze_timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
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microblaze_timer0_start_oneshot(delta);
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return 0;
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}
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|
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static void microblaze_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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printk(KERN_INFO "%s: periodic\n", __func__);
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microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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printk(KERN_INFO "%s: oneshot\n", __func__);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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printk(KERN_INFO "%s: unused\n", __func__);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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printk(KERN_INFO "%s: shutdown\n", __func__);
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microblaze_timer0_stop();
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break;
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case CLOCK_EVT_MODE_RESUME:
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printk(KERN_INFO "%s: resume\n", __func__);
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break;
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}
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}
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|
||||
static struct clock_event_device clockevent_microblaze_timer = {
|
||||
.name = "microblaze_clockevent",
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
|
||||
.shift = 24,
|
||||
.rating = 300,
|
||||
.set_next_event = microblaze_timer_set_next_event,
|
||||
.set_mode = microblaze_timer_set_mode,
|
||||
};
|
||||
|
||||
static inline void timer_ack(void)
|
||||
{
|
||||
out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
|
||||
}
|
||||
|
||||
static irqreturn_t timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_microblaze_timer;
|
||||
#ifdef CONFIG_HEART_BEAT
|
||||
heartbeat();
|
||||
#endif
|
||||
timer_ack();
|
||||
evt->event_handler(evt);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction timer_irqaction = {
|
||||
.handler = timer_interrupt,
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
.name = "timer",
|
||||
.dev_id = &clockevent_microblaze_timer,
|
||||
};
|
||||
|
||||
static __init void microblaze_clockevent_init(void)
|
||||
{
|
||||
clockevent_microblaze_timer.mult =
|
||||
div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
|
||||
clockevent_microblaze_timer.shift);
|
||||
clockevent_microblaze_timer.max_delta_ns =
|
||||
clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
|
||||
clockevent_microblaze_timer.min_delta_ns =
|
||||
clockevent_delta2ns(1, &clockevent_microblaze_timer);
|
||||
clockevent_microblaze_timer.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&clockevent_microblaze_timer);
|
||||
}
|
||||
|
||||
static cycle_t microblaze_read(void)
|
||||
{
|
||||
/* reading actual value of timer 1 */
|
||||
return (cycle_t) (in_be32(TIMER_BASE + TCR1));
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_microblaze = {
|
||||
.name = "microblaze_clocksource",
|
||||
.rating = 300,
|
||||
.read = microblaze_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.shift = 24, /* I can shift it */
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static int __init microblaze_clocksource_init(void)
|
||||
{
|
||||
clocksource_microblaze.mult =
|
||||
clocksource_hz2mult(cpuinfo.cpu_clock_freq,
|
||||
clocksource_microblaze.shift);
|
||||
if (clocksource_register(&clocksource_microblaze))
|
||||
panic("failed to register clocksource");
|
||||
|
||||
/* stop timer1 */
|
||||
out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
|
||||
/* start timer1 - up counting without interrupt */
|
||||
out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init time_init(void)
|
||||
{
|
||||
u32 irq, i = 0;
|
||||
u32 timer_num = 1;
|
||||
struct device_node *timer = NULL;
|
||||
#ifdef CONFIG_SELFMOD_TIMER
|
||||
unsigned int timer_baseaddr = 0;
|
||||
int arr_func[] = {
|
||||
(int)µblaze_read,
|
||||
(int)&timer_interrupt,
|
||||
(int)µblaze_clocksource_init,
|
||||
(int)µblaze_timer_set_mode,
|
||||
(int)µblaze_timer_set_next_event,
|
||||
0
|
||||
};
|
||||
#endif
|
||||
char *timer_list[] = {
|
||||
"xlnx,xps-timer-1.00.a",
|
||||
"xlnx,opb-timer-1.00.b",
|
||||
"xlnx,opb-timer-1.00.a",
|
||||
NULL
|
||||
};
|
||||
|
||||
for (i = 0; timer_list[i] != NULL; i++) {
|
||||
timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
|
||||
if (timer)
|
||||
break;
|
||||
}
|
||||
|
||||
timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
|
||||
timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
|
||||
irq = *(int *) of_get_property(timer, "interrupts", NULL);
|
||||
timer_num =
|
||||
*(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);
|
||||
if (timer_num) {
|
||||
printk(KERN_EMERG "Please enable two timers in HW\n");
|
||||
BUG();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SELFMOD_TIMER
|
||||
selfmod_function((int *) arr_func, timer_baseaddr);
|
||||
#endif
|
||||
printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
|
||||
timer_list[i], timer_baseaddr, irq);
|
||||
|
||||
cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
|
||||
|
||||
setup_irq(irq, &timer_irqaction);
|
||||
#ifdef CONFIG_HEART_BEAT
|
||||
setup_heartbeat();
|
||||
#endif
|
||||
microblaze_clocksource_init();
|
||||
microblaze_clockevent_init();
|
||||
}
|
||||
Loading…
Reference in New Issue