mirror of https://gitee.com/openkylin/linux.git
Merge branch 'clk-qcom' into clk-next
- Enable CPU clks on Qualcomm IPQ6018 SoCs * clk-qcom: clk: qcom: smd: Add support for MSM8936 rpm clocks dt-bindings: clock: rpmcc: Document MSM8936 compatible clk: qcom: smd: Add support for SDM660 rpm clocks clk: qcom: Add ipq6018 apss clock controller clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq apss pll driver dt-bindings: clock: add ipq6018 a53 pll compatible
This commit is contained in:
Stephen Boyd
commit
ef01ab612b
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@ -15,7 +15,9 @@ description:
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properties:
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compatible:
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const: qcom,msm8916-a53pll
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enum:
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- qcom,ipq6018-a53pll
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- qcom,msm8916-a53pll
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reg:
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maxItems: 1
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@ -23,6 +25,14 @@ properties:
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'#clock-cells':
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const: 0
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clocks:
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items:
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- description: board XO clock
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clock-names:
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items:
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- const: xo
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required:
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- compatible
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- reg
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@ -38,3 +48,12 @@ examples:
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reg = <0xb016000 0x40>;
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#clock-cells = <0>;
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};
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#Example 2 - A53 PLL found on IPQ6018 devices
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- |
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a53pll_ipq: clock-controller@b116000 {
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compatible = "qcom,ipq6018-a53pll";
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reg = <0x0b116000 0x40>;
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#clock-cells = <0>;
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clocks = <&xo>;
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clock-names = "xo";
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};
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@ -13,6 +13,7 @@ Required properties :
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"qcom,rpmcc-msm8660", "qcom,rpmcc"
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"qcom,rpmcc-apq8060", "qcom,rpmcc"
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"qcom,rpmcc-msm8916", "qcom,rpmcc"
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"qcom,rpmcc-msm8936", "qcom,rpmcc"
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"qcom,rpmcc-msm8974", "qcom,rpmcc"
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"qcom,rpmcc-msm8976", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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@ -20,6 +21,7 @@ Required properties :
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"qcom,rpmcc-msm8996", "qcom,rpmcc"
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"qcom,rpmcc-msm8998", "qcom,rpmcc"
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"qcom,rpmcc-qcs404", "qcom,rpmcc"
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"qcom,rpmcc-sdm660", "qcom,rpmcc"
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- #clock-cells : shall contain 1
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@ -89,6 +89,25 @@ config APQ_MMCC_8084
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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config IPQ_APSS_PLL
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tristate "IPQ APSS PLL"
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help
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Support for APSS PLL on ipq devices. The APSS PLL is the main
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clock that feeds the CPUs on ipq based devices.
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Say Y if you want to support CPU frequency scaling on ipq based
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devices.
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config IPQ_APSS_6018
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tristate "IPQ APSS Clock Controller"
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select IPQ_APSS_PLL
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depends on QCOM_APCS_IPC || COMPILE_TEST
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help
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Support for APSS clock controller on IPQ platforms. The
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APSS clock controller manages the Mux and enable block that feeds the
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CPUs.
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Say Y if you want to support CPU frequency scaling on
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ipq based devices.
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config IPQ_GCC_4019
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tristate "IPQ4019 Global Clock Controller"
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help
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@ -19,6 +19,8 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
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# Keep alphabetically sorted by config
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obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
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obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
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obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
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obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
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obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
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@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "clk-alpha-pll.h"
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static const u8 ipq_pll_offsets[] = {
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[PLL_OFF_L_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL] = 0x10,
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[PLL_OFF_USER_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL] = 0x20,
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[PLL_OFF_CONFIG_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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[PLL_OFF_TEST_CTL] = 0x30,
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[PLL_OFF_TEST_CTL_U] = 0x34,
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};
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static struct clk_alpha_pll ipq_pll = {
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.offset = 0x0,
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.regs = ipq_pll_offsets,
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.clkr = {
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.enable_reg = 0x0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "a53pll",
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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},
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};
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static const struct alpha_pll_config ipq_pll_config = {
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.l = 0x37,
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.config_ctl_val = 0x04141200,
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.config_ctl_hi_val = 0x0,
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.early_output_mask = BIT(3),
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.main_output_mask = BIT(0),
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};
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static const struct regmap_config ipq_pll_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x40,
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.fast_io = true,
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};
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static int apss_ipq_pll_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
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ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&ipq_pll.clkr.hw);
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}
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static const struct of_device_id apss_ipq_pll_match_table[] = {
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{ .compatible = "qcom,ipq6018-a53pll" },
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{ }
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};
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static struct platform_driver apss_ipq_pll_driver = {
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.probe = apss_ipq_pll_probe,
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.driver = {
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.name = "qcom-ipq-apss-pll",
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.of_match_table = apss_ipq_pll_match_table,
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},
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};
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module_platform_driver(apss_ipq_pll_driver);
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MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,106 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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#include "clk-regmap-mux.h"
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enum {
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P_XO,
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P_APSS_PLL_EARLY,
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};
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static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
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{ .fw_name = "xo" },
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{ .fw_name = "pll" },
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};
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static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
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{ P_XO, 0 },
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{ P_APSS_PLL_EARLY, 5 },
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};
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static struct clk_regmap_mux apcs_alias0_clk_src = {
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.reg = 0x0050,
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.width = 3,
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.shift = 7,
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.parent_map = parents_apcs_alias0_clk_src_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_clk_src",
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.parent_data = parents_apcs_alias0_clk_src,
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_branch apcs_alias0_core_clk = {
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.halt_reg = 0x0058,
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.clkr = {
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.enable_reg = 0x0058,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_core_clk",
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.parent_hws = (const struct clk_hw *[]){
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&apcs_alias0_clk_src.clkr.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static const struct regmap_config apss_ipq6018_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x1000,
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.fast_io = true,
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};
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static struct clk_regmap *apss_ipq6018_clks[] = {
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[APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
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[APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
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};
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static const struct qcom_cc_desc apss_ipq6018_desc = {
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.config = &apss_ipq6018_regmap_config,
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.clks = apss_ipq6018_clks,
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.num_clks = ARRAY_SIZE(apss_ipq6018_clks),
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};
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static int apss_ipq6018_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
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}
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static struct platform_driver apss_ipq6018_driver = {
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.probe = apss_ipq6018_probe,
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.driver = {
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.name = "qcom,apss-ipq6018-clk",
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},
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};
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module_platform_driver(apss_ipq6018_driver);
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MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
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MODULE_LICENSE("GPL v2");
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@ -452,6 +452,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
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.num_clks = ARRAY_SIZE(msm8916_clks),
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};
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/* msm8936 */
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DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
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DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5);
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static struct clk_smd_rpm *msm8936_clks[] = {
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[RPM_SMD_PCNOC_CLK] = &msm8936_pcnoc_clk,
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[RPM_SMD_PCNOC_A_CLK] = &msm8936_pcnoc_a_clk,
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[RPM_SMD_SNOC_CLK] = &msm8936_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8936_snoc_a_clk,
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[RPM_SMD_BIMC_CLK] = &msm8936_bimc_clk,
|
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[RPM_SMD_BIMC_A_CLK] = &msm8936_bimc_a_clk,
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[RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk,
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[RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk,
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[RPM_SMD_QDSS_CLK] = &msm8936_qdss_clk,
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[RPM_SMD_QDSS_A_CLK] = &msm8936_qdss_a_clk,
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[RPM_SMD_BB_CLK1] = &msm8936_bb_clk1,
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[RPM_SMD_BB_CLK1_A] = &msm8936_bb_clk1_a,
|
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[RPM_SMD_BB_CLK2] = &msm8936_bb_clk2,
|
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[RPM_SMD_BB_CLK2_A] = &msm8936_bb_clk2_a,
|
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[RPM_SMD_RF_CLK1] = &msm8936_rf_clk1,
|
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[RPM_SMD_RF_CLK1_A] = &msm8936_rf_clk1_a,
|
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[RPM_SMD_RF_CLK2] = &msm8936_rf_clk2,
|
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[RPM_SMD_RF_CLK2_A] = &msm8936_rf_clk2_a,
|
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[RPM_SMD_BB_CLK1_PIN] = &msm8936_bb_clk1_pin,
|
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[RPM_SMD_BB_CLK1_A_PIN] = &msm8936_bb_clk1_a_pin,
|
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[RPM_SMD_BB_CLK2_PIN] = &msm8936_bb_clk2_pin,
|
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[RPM_SMD_BB_CLK2_A_PIN] = &msm8936_bb_clk2_a_pin,
|
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[RPM_SMD_RF_CLK1_PIN] = &msm8936_rf_clk1_pin,
|
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[RPM_SMD_RF_CLK1_A_PIN] = &msm8936_rf_clk1_a_pin,
|
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[RPM_SMD_RF_CLK2_PIN] = &msm8936_rf_clk2_pin,
|
||||
[RPM_SMD_RF_CLK2_A_PIN] = &msm8936_rf_clk2_a_pin,
|
||||
};
|
||||
|
||||
static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
|
||||
.clks = msm8936_clks,
|
||||
.num_clks = ARRAY_SIZE(msm8936_clks),
|
||||
};
|
||||
|
||||
/* msm8974 */
|
||||
DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
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DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
||||
|
|
@ -766,13 +815,90 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
|
|||
.num_clks = ARRAY_SIZE(msm8998_clks),
|
||||
};
|
||||
|
||||
/* sdm660 */
|
||||
DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
|
||||
19200000);
|
||||
DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
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DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
|
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DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
|
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QCOM_SMD_RPM_BUS_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
|
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QCOM_SMD_RPM_MMAXI_CLK, 0);
|
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DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
|
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QCOM_SMD_RPM_AGGR_CLK, 2);
|
||||
DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
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QCOM_SMD_RPM_MISC_CLK, 1);
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||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4);
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||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11);
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||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1);
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||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2);
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||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
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||||
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
|
||||
ln_bb_clk1_pin_a, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
|
||||
ln_bb_clk2_pin_a, 2);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
|
||||
ln_bb_clk3_pin_a, 3);
|
||||
static struct clk_smd_rpm *sdm660_clks[] = {
|
||||
[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
|
||||
[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
|
||||
[RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk,
|
||||
[RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk,
|
||||
[RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk,
|
||||
[RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk,
|
||||
[RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk,
|
||||
[RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk,
|
||||
[RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk,
|
||||
[RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk,
|
||||
[RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk,
|
||||
[RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk,
|
||||
[RPM_SMD_IPA_CLK] = &sdm660_ipa_clk,
|
||||
[RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk,
|
||||
[RPM_SMD_CE1_CLK] = &sdm660_ce1_clk,
|
||||
[RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk,
|
||||
[RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk,
|
||||
[RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk,
|
||||
[RPM_SMD_RF_CLK1] = &sdm660_rf_clk1,
|
||||
[RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a,
|
||||
[RPM_SMD_DIV_CLK1] = &sdm660_div_clk1,
|
||||
[RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a,
|
||||
[RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1,
|
||||
[RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a,
|
||||
[RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2,
|
||||
[RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a,
|
||||
[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
|
||||
[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
|
||||
[RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin,
|
||||
[RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin,
|
||||
[RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin,
|
||||
[RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a,
|
||||
[RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin,
|
||||
[RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a,
|
||||
[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
|
||||
[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
|
||||
};
|
||||
|
||||
static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
|
||||
.clks = sdm660_clks,
|
||||
.num_clks = ARRAY_SIZE(sdm660_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id rpm_smd_clk_match_table[] = {
|
||||
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
|
||||
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
|
||||
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
|
||||
{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
|
||||
{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
|
||||
{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
|
||||
{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
|
||||
{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
|
||||
#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
|
||||
|
||||
#define APCS_ALIAS0_CLK_SRC 0
|
||||
#define APCS_ALIAS0_CORE_CLK 1
|
||||
|
||||
#endif
|
||||
|
|
@ -133,5 +133,17 @@
|
|||
#define RPM_SMD_RF_CLK3_A 87
|
||||
#define RPM_SMD_RF_CLK3_PIN 88
|
||||
#define RPM_SMD_RF_CLK3_A_PIN 89
|
||||
#define RPM_SMD_MMSSNOC_AXI_CLK 90
|
||||
#define RPM_SMD_MMSSNOC_AXI_CLK_A 91
|
||||
#define RPM_SMD_CNOC_PERIPH_CLK 92
|
||||
#define RPM_SMD_CNOC_PERIPH_A_CLK 93
|
||||
#define RPM_SMD_LN_BB_CLK3 94
|
||||
#define RPM_SMD_LN_BB_CLK3_A 95
|
||||
#define RPM_SMD_LN_BB_CLK1_PIN 96
|
||||
#define RPM_SMD_LN_BB_CLK1_A_PIN 97
|
||||
#define RPM_SMD_LN_BB_CLK2_PIN 98
|
||||
#define RPM_SMD_LN_BB_CLK2_A_PIN 99
|
||||
#define RPM_SMD_SYSMMNOC_CLK 100
|
||||
#define RPM_SMD_SYSMMNOC_A_CLK 101
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue