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staging: rtlwifi: delete the staging driver 

A "real" driver for this hardware is now in the wireless-drivers-next
tree, to be merged in the next major kernel release, so this staging
driver can now be deleted as it is not needed anymore.

Note, 2 .h files remain for this driver, as they are referenced in a
separate staging driver.  That mess will be cleaned up in a follow-on
patch.

Cc: Ping-Ke Shih <pkshih@realtek.com>
Cc: Tzu-En Huang <tehuang@realtek.com>
Cc: Yan-Hsuan Chuang <yhchuang@realtek.com>
Cc: Stanislaw Gruszka <sgruszka@redhat.com>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman 2019-05-01 10:15:42 +02:00
parent 39e8046240
commit ef4a0c3173
181 changed files with 0 additions and 123321 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/Kconfig
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@ -40,8 +40,6 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rtl8188eu/Kconfig"
source "drivers/staging/rtlwifi/Kconfig"
source "drivers/staging/rts5208/Kconfig"
source "drivers/staging/octeon/Kconfig"

1
drivers/staging/Makefile
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@ -10,7 +10,6 @@ obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_RTL8723BS) += rtl8723bs/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += rtl8188eu/
obj-$(CONFIG_R8822BE) += rtlwifi/
obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_NETLOGIC_XLR_NET) += netlogic/
obj-$(CONFIG_OCTEON_ETHERNET) += octeon/

13
drivers/staging/rtlwifi/Kconfig
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@ -1,13 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config R8822BE
tristate "Realtek RTL8822BE Wireless Network Adapter"
depends on PCI && MAC80211 && m
select FW_LOADER
help
This is the staging driver for Realtek RTL8822BE 802.11ac PCIe
wireless network adapters.
config RTLWIFI_DEBUG_ST
bool
depends on R8822BE
default y

71
drivers/staging/rtlwifi/Makefile
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@ -1,71 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_R8822BE) += r8822be.o
r8822be-objs := \
base.o \
cam.o \
core.o \
debug.o \
efuse.o \
ps.o \
rc.o \
regd.o \
stats.o \
pci.o \
rtl8822be/fw.o \
rtl8822be/hw.o \
rtl8822be/led.o \
rtl8822be/phy.o \
rtl8822be/sw.o \
rtl8822be/trx.o \
btcoexist/halbtc8822b2ant.o \
btcoexist/halbtc8822b1ant.o \
btcoexist/halbtc8822bwifionly.o \
btcoexist/halbtcoutsrc.o \
btcoexist/rtl_btc.o \
halmac/halmac_api.o \
halmac/halmac_88xx/halmac_api_88xx_usb.o \
halmac/halmac_88xx/halmac_api_88xx_sdio.o \
halmac/halmac_88xx/halmac_api_88xx.o \
halmac/halmac_88xx/halmac_api_88xx_pcie.o \
halmac/halmac_88xx/halmac_func_88xx.o \
halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o \
halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \
halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \
halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \
halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.o \
halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \
halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \
halmac/rtl_halmac.o \
phydm/phydm_debug.o \
phydm/phydm_antdiv.o\
phydm/phydm_interface.o\
phydm/phydm_hwconfig.o\
phydm/phydm.o\
phydm/halphyrf_ce.o\
phydm/phydm_edcaturbocheck.o\
phydm/phydm_dig.o\
phydm/phydm_rainfo.o\
phydm/phydm_dynamicbbpowersaving.o\
phydm/phydm_powertracking_ce.o\
phydm/phydm_dynamictxpower.o\
phydm/phydm_adaptivity.o\
phydm/phydm_cfotracking.o\
phydm/phydm_noisemonitor.o\
phydm/phydm_acs.o\
phydm/phydm_psd.o\
phydm/phydm_adc_sampling.o\
phydm/phydm_kfree.o\
phydm/phydm_ccx.o \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/halhwimg8822b_rf.o\
phydm/rtl8822b/halphyrf_8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_iqk_8822b.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o \
phydm/rtl_phydm.o
obj-$(CONFIG_R8822BE) += rtl8822be/

11
drivers/staging/rtlwifi/TODO
View File

@ -1,11 +0,0 @@
TODO:
- find and remove code blocks guarded by never set CONFIG_FOO defines
- convert any remaining unusual variable types
- find codes that can use %pM and %Nph formatting
- checkpatch.pl fixes - most of the remaining ones are lines too long. Many
of them will require refactoring
- merge Realtek's bugfixes and new features into the driver
- address any reviewers comments
Please send any patches to Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
and Larry Finger <Larry.Finger@lwfinger.net>.

2805
drivers/staging/rtlwifi/base.c
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File diff suppressed because it is too large Load Diff

175
drivers/staging/rtlwifi/base.h
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@ -1,175 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BASE_H__
#define __RTL_BASE_H__
enum ap_peer {
PEER_UNKNOWN = 0,
PEER_RTL = 1,
PEER_RTL_92SE = 2,
PEER_BROAD = 3,
PEER_RAL = 4,
PEER_ATH = 5,
PEER_CISCO = 6,
PEER_MARV = 7,
PEER_AIRGO = 9,
PEER_MAX = 10,
};
#define RTL_DUMMY_OFFSET 0
#define RTL_DUMMY_UNIT 8
#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
#define RTL_TX_DESC_SIZE 32
#define RTL_TX_HEADER_SIZE (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS9 867 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_2NSS_80MHZ_MCS7 650 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS9 780 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_2NSS_80MHZ_MCS7 585 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS9 434 /* Mbps */
#define MAX_BIT_RATE_SHORT_GI_1NSS_80MHZ_MCS7 325 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS9 390 /* Mbps */
#define MAX_BIT_RATE_LONG_GI_1NSS_80MHZ_MCS7 293 /* Mbps */
#define FRAME_OFFSET_FRAME_CONTROL 0
#define FRAME_OFFSET_DURATION 2
#define FRAME_OFFSET_ADDRESS1 4
#define FRAME_OFFSET_ADDRESS2 10
#define FRAME_OFFSET_ADDRESS3 16
#define FRAME_OFFSET_SEQUENCE 22
#define FRAME_OFFSET_ADDRESS4 24
#define MAX_LISTEN_INTERVAL 10
#define MAX_RATE_TRIES 4
#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
WRITEEF2BYTE(_hdr, _val)
#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
WRITEEF1BYTE(_hdr, _val)
#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
#define SET_80211_HDR_TO_DS(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
#define SET_80211_PS_POLL_AID(_hdr, _val) \
(*(u16 *)((u8 *)(_hdr) + 2) = _val)
#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
ether_addr_copy(((u8 *)(_hdr)) + 4, (u8 *)(_val))
#define SET_80211_PS_POLL_TA(_hdr, _val) \
ether_addr_copy(((u8 *)(_hdr)) + 10, (u8 *)(_val))
#define SET_80211_HDR_DURATION(_hdr, _val) \
(*(u16 *)((u8 *)(_hdr) + FRAME_OFFSET_DURATION) = le16_to_cpu(_val))
#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS1, (u8 *)(_val))
#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS3, (u8 *)(_val))
#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
WRITEEF2BYTE((u8 *)(_hdr) + FRAME_OFFSET_SEQUENCE, _val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
WRITEEF4BYTE(((u8 *)(__phdr)) + 24, __val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
WRITEEF4BYTE(((u8 *)(__phdr)) + 28, __val)
#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
WRITEEF2BYTE(((u8 *)(__phdr)) + 32, __val)
#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
READEF2BYTE(((u8 *)(__phdr)) + 34)
#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
WRITEEF2BYTE(((u8 *)(__phdr)) + 34, __val)
#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
(GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE((__pdesc) + 8, 19, 1, __val)
#define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 0, 12, __val)
int rtl_init_core(struct ieee80211_hw *hw);
void rtl_deinit_core(struct ieee80211_hw *hw);
void rtl_init_rx_config(struct ieee80211_hw *hw);
void rtl_init_rfkill(struct ieee80211_hw *hw);
void rtl_deinit_rfkill(struct ieee80211_hw *hw);
void rtl_watch_dog_timer_callback(struct timer_list *t);
void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
int rtlwifi_rate_mapping(struct ieee80211_hw *hw, bool isht,
bool isvht, u8 desc_rate);
bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx,
bool is_enc);
bool rtl_is_tx_report_skb(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl_get_tx_report(struct rtl_tcb_desc *ptcb_desc, u8 *pdesc,
struct ieee80211_hw *hw);
void rtl_tx_report_handler(struct ieee80211_hw *hw, u8 *tmp_buf,
u8 c2h_cmd_len);
bool rtl_check_tx_report_acked(struct ieee80211_hw *hw);
void rtl_wait_tx_report_acked(struct ieee80211_hw *hw, u32 wait_ms);
u32 rtl_get_hal_edca_param(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
enum wireless_mode wirelessmode,
struct ieee80211_tx_queue_params *param);
void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl_scan_list_expire(struct ieee80211_hw *hw);
int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid, u16 *ssn);
int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid);
int rtl_tx_agg_oper(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl_rx_agg_start(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl_rx_agg_stop(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
void rtl_rx_ampdu_apply(struct rtl_priv *rtlpriv);
void rtl_watchdog_wq_callback(void *data);
void rtl_fwevt_wq_callback(void *data);
void rtl_c2hcmd_wq_callback(void *data);
void rtl_c2hcmd_launcher(struct ieee80211_hw *hw, int exec);
void rtl_c2hcmd_enqueue(struct ieee80211_hw *hw, u8 tag, u8 len, u8 *val);
u8 rtl_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
u8 rate_index,
enum wireless_mode wirelessmode);
void rtl_get_tcb_desc(struct ieee80211_hw *hw,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
int rtl_send_smps_action(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
enum ieee80211_smps_mode smps);
u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie);
void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
u8 rtl_tid_to_ac(u8 tid);
void rtl_easy_concurrent_retrytimer_callback(struct timer_list *t);
extern struct rtl_global_var rtl_global_var;
void rtl_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation);
bool rtl_check_beacon_key(struct ieee80211_hw *hw, void *data,
unsigned int len);
int rtl_core_module_init(void);
void rtl_core_module_exit(void);
#endif

9
drivers/staging/rtlwifi/btcoexist/Makefile
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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
btcoexist-objs := \
halbtc8822b1ant.o \
halbtc8822b2ant.o \
halbtc8822bwifionly.o \
halbtcoutsrc.o \
rtl_btc.o
obj-$(CONFIG_RTLBTCOEXIST) += btcoexist.o

74
drivers/staging/rtlwifi/btcoexist/halbt_precomp.h
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@ -1,74 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
******************************************************************************/
#ifndef __HALBT_PRECOMP_H__
#define __HALBT_PRECOMP_H__
/*************************************************************
* include files
*************************************************************/
#include "../wifi.h"
#include "../efuse.h"
#include "../base.h"
#include "../regd.h"
#include "../cam.h"
#include "../ps.h"
#include "../pci.h"
#include "halbtcoutsrc.h"
/* Interface type */
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#include "halbtc8822b1ant.h"
#include "halbtc8822b2ant.h"
#include "halbtc8822bwifionly.h"
#define GETDEFAULTADAPTER(padapter) padapter
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#endif /* __HALBT_PRECOMP_H__ */

5233
drivers/staging/rtlwifi/btcoexist/halbtc8822b1ant.c
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File diff suppressed because it is too large Load Diff

433
drivers/staging/rtlwifi/btcoexist/halbtc8822b1ant.h
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@ -1,433 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* *******************************************
* The following is for 8822B 1ANT BT Co-exist definition
* ********************************************/
#define BT_INFO_8822B_1ANT_B_FTP BIT(7)
#define BT_INFO_8822B_1ANT_B_A2DP BIT(6)
#define BT_INFO_8822B_1ANT_B_HID BIT(5)
#define BT_INFO_8822B_1ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8822B_1ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8822B_1ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8822B_1ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8822B_1ANT_B_CONNECTION BIT(0)
#define BT_INFO_8822B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_ & BIT(0))) ? true : false)
#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2
#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */
#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */
/* for Antenna detection */
#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
#define BT_8822B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
#define BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT 35
#define BT_8822B_1ANT_ANTDET_RETRY_INTERVAL \
10 /* retry timer if ant det is fail, unit: second */
#define BT_8822B_1ANT_ANTDET_ENABLE 0
#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
enum bt_8822b_1ant_signal_state {
BT_8822B_1ANT_SIG_STA_SET_TO_LOW = 0x0,
BT_8822B_1ANT_SIG_STA_SET_BY_HW = 0x0,
BT_8822B_1ANT_SIG_STA_SET_TO_HIGH = 0x1,
BT_8822B_1ANT_SIG_STA_MAX
};
enum bt_8822b_1ant_path_ctrl_owner {
BT_8822B_1ANT_PCO_BTSIDE = 0x0,
BT_8822B_1ANT_PCO_WLSIDE = 0x1,
BT_8822B_1ANT_PCO_MAX
};
enum bt_8822b_1ant_gnt_ctrl_type {
BT_8822B_1ANT_GNT_CTRL_BY_PTA = 0x0,
BT_8822B_1ANT_GNT_CTRL_BY_SW = 0x1,
BT_8822B_1ANT_GNT_CTRL_MAX
};
enum bt_8822b_1ant_gnt_ctrl_block {
BT_8822B_1ANT_GNT_BLOCK_RFC_BB = 0x0,
BT_8822B_1ANT_GNT_BLOCK_RFC = 0x1,
BT_8822B_1ANT_GNT_BLOCK_BB = 0x2,
BT_8822B_1ANT_GNT_BLOCK_MAX
};
enum bt_8822b_1ant_lte_coex_table_type {
BT_8822B_1ANT_CTT_WL_VS_LTE = 0x0,
BT_8822B_1ANT_CTT_BT_VS_LTE = 0x1,
BT_8822B_1ANT_CTT_MAX
};
enum bt_8822b_1ant_lte_break_table_type {
BT_8822B_1ANT_LBTT_WL_BREAK_LTE = 0x0,
BT_8822B_1ANT_LBTT_BT_BREAK_LTE = 0x1,
BT_8822B_1ANT_LBTT_LTE_BREAK_WL = 0x2,
BT_8822B_1ANT_LBTT_LTE_BREAK_BT = 0x3,
BT_8822B_1ANT_LBTT_MAX
};
enum bt_info_src_8822b_1ant {
BT_INFO_SRC_8822B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8822B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8822B_1ANT_MAX
};
enum bt_8822b_1ant_bt_status {
BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8822B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8822B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8822B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8822B_1ANT_BT_STATUS_MAX
};
enum bt_8822b_1ant_wifi_status {
BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8822B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8822B_1ANT_WIFI_STATUS_MAX
};
enum bt_8822b_1ant_coex_algo {
BT_8822B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8822B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8822B_1ANT_COEX_ALGO_HID = 0x2,
BT_8822B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8822B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8822B_1ANT_COEX_ALGO_MAX = 0xb,
};
enum bt_8822b_1ant_ext_ant_switch_type {
BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x0,
BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T = 0x1,
BT_8822B_1ANT_EXT_ANT_SWITCH_MAX
};
enum bt_8822b_1ant_ext_ant_switch_ctrl_type {
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_MAX
};
enum bt_8822b_1ant_ext_ant_switch_pos_type {
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX
};
enum bt_8822b_1ant_phase {
BT_8822B_1ANT_PHASE_COEX_INIT = 0x0,
BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1,
BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2,
BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3,
BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4,
BT_8822B_1ANT_PHASE_BTMPMODE = 0x5,
BT_8822B_1ANT_PHASE_MAX
};
/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
enum bt_8822b_1ant_scoreboard {
BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0),
BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1),
BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2),
BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3),
BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6)
};
struct coex_dm_8822b_1ant {
/* hw setting */
u32 pre_ant_pos_type;
u32 cur_ant_pos_type;
/* fw mechanism */
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
/* sw mechanism */
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retry_limit;
u8 backup_ampdu_max_time;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u32 pre_ra_mask;
u32 cur_ra_mask;
u8 pre_arfr_type;
u8 cur_arfr_type;
u8 pre_retry_limit_type;
u8 cur_retry_limit_type;
u8 pre_ampdu_time_type;
u8 cur_ampdu_time_type;
u32 arp_cnt;
u32 pre_ext_ant_switch_status;
u32 cur_ext_ant_switch_status;
u8 error_condition;
};
struct coex_sta_8822b_1ant {
bool bt_disabled;
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
u8 num_of_profile;
bool under_lps;
bool under_ips;
u32 specific_pkt_period_cnt;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
bool is_hi_pri_rx_overhead;
s8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX];
bool bt_whck_test;
bool c2h_bt_inquiry_page;
bool c2h_bt_remote_name_req;
bool c2h_bt_page; /* Add for win8.1 page out issue */
bool wifi_is_high_pri_task; /* Add for win8.1 page out issue */
u8 bt_info_ext;
u8 bt_info_ext2;
u32 pop_event_cnt;
u8 scan_ap_num;
u8 bt_retry_cnt;
u32 crc_ok_cck;
u32 crc_ok_11g;
u32 crc_ok_11n;
u32 crc_ok_11n_vht;
u32 crc_err_cck;
u32 crc_err_11g;
u32 crc_err_11n;
u32 crc_err_11n_vht;
bool cck_lock;
bool pre_ccklock;
bool cck_ever_lock;
u8 coex_table_type;
bool force_lps_ctrl;
bool concurrent_rx_mode_on;
u16 score_board;
u8 isolation_btween_wb; /* 0~ 50 */
u8 a2dp_bit_pool;
u8 cut_version;
bool acl_busy;
bool bt_create_connection;
u32 bt_coex_supported_feature;
u32 bt_coex_supported_version;
u8 bt_ble_scan_type;
u32 bt_ble_scan_para[3];
bool run_time_state;
bool freeze_coexrun_by_btinfo;
bool is_A2DP_3M;
bool voice_over_HOGP;
u8 bt_info;
bool is_autoslot;
u8 forbidden_slot;
u8 hid_busy_num;
u8 hid_pair_cnt;
u32 cnt_remote_name_req;
u32 cnt_setup_link;
u32 cnt_reinit;
u32 cnt_ign_wlan_act;
u32 cnt_page;
u32 cnt_role_switch;
u16 bt_reg_vendor_ac;
u16 bt_reg_vendor_ae;
bool is_setup_link;
u8 wl_noisy_level;
u32 gnt_error_cnt;
u8 bt_afh_map[10];
u8 bt_relink_downcount;
bool is_tdma_btautoslot;
bool is_tdma_btautoslot_hang;
u8 switch_band_notify_to;
bool is_rf_state_off;
bool is_hid_low_pri_tx_overhead;
bool is_bt_multi_link;
bool is_bt_a2dp_sink;
bool rf4ce_enabled;
bool is_set_ps_state_fail;
u8 cnt_set_ps_state_fail;
};
struct rfe_type_8822b_1ant {
u8 rfe_module_type;
bool ext_ant_switch_exist;
u8 ext_ant_switch_type;
/* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */
u8 ext_ant_switch_ctrl_polarity;
};
#define BT_8822B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
#define BT_8822B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
#define BT_8822B_1ANT_ANTDET_BUF_LEN 16
struct psdscan_sta_8822b_1ant {
u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
u32 ant_det_bt_tx_time;
u32 ant_det_pre_psdscan_peak_val;
bool ant_det_is_ant_det_available;
u32 ant_det_psd_scan_peak_val;
bool ant_det_is_btreply_available;
u32 ant_det_psd_scan_peak_freq;
u8 ant_det_result;
u8 ant_det_peak_val[BT_8822B_1ANT_ANTDET_BUF_LEN];
u8 ant_det_peak_freq[BT_8822B_1ANT_ANTDET_BUF_LEN];
u32 ant_det_try_count;
u32 ant_det_fail_count;
u32 ant_det_inteval_count;
u32 ant_det_thres_offset;
u32 real_cent_freq;
s32 real_offset;
u32 real_span;
u32 psd_band_width; /* unit: Hz */
u32 psd_point; /* 128/256/512/1024 */
u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
u32 psd_start_point;
u32 psd_stop_point;
u32 psd_max_value_point;
u32 psd_max_value;
u32 psd_start_base;
u32 psd_avg_num; /* 1/8/16/32 */
u32 psd_gen_count;
bool is_psd_running;
bool is_psd_show_max_only;
bool is_ant_det_running;
};
/* *******************************************
* The following is interface which will notify coex module.
* ********************************************/
void ex_btc8822b1ant_power_on_setting(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_pre_load_firmware(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_init_hw_config(struct btc_coexist *btcoexist,
bool wifi_only);
void ex_btc8822b1ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_scan_notify_without_bt(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b1ant_switchband_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_switchband_notify_without_bt(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b1ant_specific_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b1ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
u8 length);
void ex_btc8822b1ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b1ant_halt_notify(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
void ex_halbtc8822b1ant_score_board_status_notify(struct btc_coexist *btcoexist,
u8 *tmp_buf, u8 length);
void ex_btc8822b1ant_coex_dm_reset(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_periodical(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_display_coex_info(struct btc_coexist *btcoexist,
struct seq_file *m);
void ex_btc8822b1ant_antenna_detection(struct btc_coexist *btcoexist,
u32 cent_freq, u32 offset, u32 span,
u32 seconds);
void ex_btc8822b1ant_antenna_isolation(struct btc_coexist *btcoexist,
u32 cent_freq, u32 offset, u32 span,
u32 seconds);
void ex_btc8822b1ant_psd_scan(struct btc_coexist *btcoexist, u32 cent_freq,
u32 offset, u32 span, u32 seconds);
void ex_btc8822b1ant_display_ant_detection(struct btc_coexist *btcoexist);
void ex_btc8822b1ant_dbg_control(struct btc_coexist *btcoexist, u8 op_code,
u8 op_len, u8 *pdata);

5210
drivers/staging/rtlwifi/btcoexist/halbtc8822b2ant.c
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drivers/staging/rtlwifi/btcoexist/halbtc8822b2ant.h
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@ -1,487 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* *******************************************
* The following is for 8822B 2Ant BT Co-exist definition
* ********************************************/
#define BT_INFO_8822B_2ANT_B_FTP BIT(7)
#define BT_INFO_8822B_2ANT_B_A2DP BIT(6)
#define BT_INFO_8822B_2ANT_B_HID BIT(5)
#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4)
#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3)
#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2)
#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1)
#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0)
#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2
/* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
* (default = 42)
*/
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80
/* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
* (default = 46)
*/
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 80
/* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
* (default = 42)
*/
#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80
/* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
* (default = 46)
*/
#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 80
#define BT_8822B_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */
#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
/* for Antenna detection */
#define BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND 50
#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52
#define BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT 40
#define BT_8822B_2ANT_ANTDET_RETRY_INTERVAL \
10 /* retry timer if ant det is fail, unit: second */
#define BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY 60000
#define BT_8822B_2ANT_ANTDET_ENABLE 0
#define BT_8822B_2ANT_ANTDET_BTTXTIME 100
#define BT_8822B_2ANT_ANTDET_BTTXCHANNEL 39
#define BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT 50
#define BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
enum bt_8822b_2ant_signal_state {
BT_8822B_2ANT_SIG_STA_SET_TO_LOW = 0x0,
BT_8822B_2ANT_SIG_STA_SET_BY_HW = 0x0,
BT_8822B_2ANT_SIG_STA_SET_TO_HIGH = 0x1,
BT_8822B_2ANT_SIG_STA_MAX
};
enum bt_8822b_2ant_path_ctrl_owner {
BT_8822B_2ANT_PCO_BTSIDE = 0x0,
BT_8822B_2ANT_PCO_WLSIDE = 0x1,
BT_8822B_2ANT_PCO_MAX
};
enum bt_8822b_2ant_gnt_ctrl_type {
BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
BT_8822B_2ANT_GNT_TYPE_MAX
};
enum bt_8822b_2ant_gnt_ctrl_block {
BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0,
BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1,
BT_8822B_2ANT_GNT_BLOCK_BB = 0x2,
BT_8822B_2ANT_GNT_BLOCK_MAX
};
enum bt_8822b_2ant_lte_coex_table_type {
BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0,
BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1,
BT_8822B_2ANT_CTT_MAX
};
enum bt_8822b_2ant_lte_break_table_type {
BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0,
BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1,
BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2,
BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3,
BT_8822B_2ANT_LBTT_MAX
};
enum bt_info_src_8822b_2ant {
BT_INFO_SRC_8822B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8822B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8822B_2ANT_MAX
};
enum bt_8822b_2ant_bt_status {
BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8822B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8822B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8822B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8822B_2ANT_BT_STATUS_MAX
};
enum bt_8822b_2ant_coex_algo {
BT_8822B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8822B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8822B_2ANT_COEX_ALGO_HID = 0x2,
BT_8822B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8822B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8822B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8822B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8822B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
BT_8822B_2ANT_COEX_ALGO_A2DPSINK = 0xc,
BT_8822B_2ANT_COEX_ALGO_MAX
};
enum bt_8822b_2ant_ext_ant_switch_type {
BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0,
BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1,
BT_8822B_2ANT_EXT_ANT_SWITCH_NONE = 0x2,
BT_8822B_2ANT_EXT_ANT_SWITCH_MAX
};
enum bt_8822b_2ant_ext_ant_switch_ctrl_type {
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX
};
enum bt_8822b_2ant_ext_ant_switch_pos_type {
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0,
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1,
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2,
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3,
BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX
};
enum bt_8822b_2ant_ext_band_switch_pos_type {
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0,
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1,
BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX
};
enum bt_8822b_2ant_int_block {
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0,
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1,
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2,
BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX
};
enum bt_8822b_2ant_phase {
BT_8822B_2ANT_PHASE_COEX_INIT = 0x0,
BT_8822B_2ANT_PHASE_WLANONLY_INIT = 0x1,
BT_8822B_2ANT_PHASE_WLAN_OFF = 0x2,
BT_8822B_2ANT_PHASE_2G_RUNTIME = 0x3,
BT_8822B_2ANT_PHASE_5G_RUNTIME = 0x4,
BT_8822B_2ANT_PHASE_BTMPMODE = 0x5,
BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6,
BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7,
BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8,
BT_8822B_2ANT_PHASE_MAX
};
/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
enum bt_8822b_2ant_scoreboard {
BT_8822B_2ANT_SCOREBOARD_ACTIVE = BIT(0),
BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1),
BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2),
BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3),
BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6)
};
struct coex_dm_8822b_2ant {
/* hw setting */
u32 pre_ant_pos_type;
u32 cur_ant_pos_type;
/* fw mechanism */
u8 pre_bt_dec_pwr_lvl;
u8 cur_bt_dec_pwr_lvl;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf_0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
bool need_recover0x948;
u32 backup0x948;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
bool is_switch_to_1dot5_ant;
u8 switch_thres_offset;
u32 arp_cnt;
u32 pre_ext_ant_switch_status;
u32 cur_ext_ant_switch_status;
u8 pre_ext_band_switch_status;
u8 cur_ext_band_switch_status;
u8 pre_int_block_status;
u8 cur_int_block_status;
};
struct coex_sta_8822b_2ant {
bool bt_disabled;
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
bool is_hi_pri_rx_overhead;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
u8 bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX];
bool bt_whck_test;
bool c2h_bt_inquiry_page;
bool c2h_bt_remote_name_req;
u8 bt_info_ext;
u8 bt_info_ext2;
u32 pop_event_cnt;
u8 scan_ap_num;
u8 bt_retry_cnt;
u32 crc_ok_cck;
u32 crc_ok_11g;
u32 crc_ok_11n;
u32 crc_ok_11n_vht;
u32 crc_err_cck;
u32 crc_err_11g;
u32 crc_err_11n;
u32 crc_err_11n_vht;
u32 acc_crc_ratio;
u32 now_crc_ratio;
bool cck_lock;
bool pre_ccklock;
bool cck_ever_lock;
u8 coex_table_type;
bool force_lps_ctrl;
u8 dis_ver_info_cnt;
u8 a2dp_bit_pool;
u8 cut_version;
bool concurrent_rx_mode_on;
u16 score_board;
u8 isolation_btween_wb; /* 0~ 50 */
u8 wifi_coex_thres;
u8 bt_coex_thres;
u8 wifi_coex_thres2;
u8 bt_coex_thres2;
u8 num_of_profile;
bool acl_busy;
bool bt_create_connection;
bool wifi_is_high_pri_task;
u32 specific_pkt_period_cnt;
u32 bt_coex_supported_feature;
u32 bt_coex_supported_version;
u8 bt_ble_scan_type;
u32 bt_ble_scan_para[3];
bool run_time_state;
bool freeze_coexrun_by_btinfo;
bool is_A2DP_3M;
bool voice_over_HOGP;
u8 bt_info;
bool is_autoslot;
u8 forbidden_slot;
u8 hid_busy_num;
u8 hid_pair_cnt;
u32 cnt_remote_name_req;
u32 cnt_setup_link;
u32 cnt_reinit;
u32 cnt_ign_wlan_act;
u32 cnt_page;
u32 cnt_role_switch;
u16 bt_reg_vendor_ac;
u16 bt_reg_vendor_ae;
bool is_setup_link;
u8 wl_noisy_level;
u32 gnt_error_cnt;
u8 bt_afh_map[10];
u8 bt_relink_downcount;
bool is_tdma_btautoslot;
bool is_tdma_btautoslot_hang;
bool is_esco_mode;
u8 switch_band_notify_to;
bool is_rf_state_off;
bool is_hid_low_pri_tx_overhead;
bool is_bt_multi_link;
bool is_bt_a2dp_sink;
bool is_set_ps_state_fail;
u8 cnt_set_ps_state_fail;
};
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1
struct rfe_type_8822b_2ant {
u8 rfe_module_type;
bool ext_ant_switch_exist;
u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */
/* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
u8 ext_ant_switch_ctrl_polarity;
bool ext_band_switch_exist;
u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */
u8 ext_band_switch_ctrl_polarity;
/* If true: WLG at BTG, If false: WLG at WLAG */
bool wlg_locate_at_btg;
bool ext_ant_switch_diversity; /* If diversity on */
};
#define BT_8822B_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
#define BT_8822B_2ANT_ANTDET_BUF_LEN 16
struct psdscan_sta_8822b_2ant {
u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
u32 ant_det_bt_tx_time;
u32 ant_det_pre_psdscan_peak_val;
bool ant_det_is_ant_det_available;
u32 ant_det_psd_scan_peak_val;
bool ant_det_is_btreply_available;
u32 ant_det_psd_scan_peak_freq;
u8 ant_det_result;
u8 ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN];
u8 ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN];
u32 ant_det_try_count;
u32 ant_det_fail_count;
u32 ant_det_inteval_count;
u32 ant_det_thres_offset;
u32 real_cent_freq;
s32 real_offset;
u32 real_span;
u32 psd_band_width; /* unit: Hz */
u32 psd_point; /* 128/256/512/1024 */
u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
u32 psd_start_point;
u32 psd_stop_point;
u32 psd_max_value_point;
u32 psd_max_value;
u32 psd_max_value2;
/* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT,
* and average the rest
*/
u32 psd_avg_value;
/*max value in each loop */
u32 psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT];
u32 psd_start_base;
u32 psd_avg_num; /* 1/8/16/32 */
u32 psd_gen_count;
bool is_ant_det_running;
bool is_psd_show_max_only;
};
/* *******************************************
* The following is interface which will notify coex module.
* ********************************************/
void ex_btc8822b2ant_power_on_setting(struct btc_coexist *btcoexist);
void ex_btc8822b2ant_pre_load_firmware(struct btc_coexist *btcoexist);
void ex_btc8822b2ant_init_hw_config(struct btc_coexist *btcoexist,
bool wifi_only);
void ex_btc8822b2ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_btc8822b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_switchband_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b2ant_specific_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_btc8822b2ant_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
u8 length);
void ex_btc8822b2ant_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
void ex_btc8822b2ant_halt_notify(struct btc_coexist *btcoexist);
void ex_btc8822b2ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
void ex_btc8822b2ant_periodical(struct btc_coexist *btcoexist);
void ex_btc8822b2ant_display_coex_info(struct btc_coexist *btcoexist,
struct seq_file *m);
void ex_btc8822b2ant_antenna_detection(struct btc_coexist *btcoexist,
u32 cent_freq, u32 offset, u32 span,
u32 seconds);
void ex_btc8822b2ant_display_ant_detection(struct btc_coexist *btcoexist);

54
drivers/staging/rtlwifi/btcoexist/halbtc8822bwifionly.c
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@ -1,54 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halbt_precomp.h"
void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg)
{
/*BB control*/
halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2);
/*SW control*/
halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77);
/*antenna mux switch */
halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3);
halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0);
halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0);
/*switch to WL side controller and gnt_wl gnt_bt debug signal */
halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e);
/*gnt_wl=1 , gnt_bt=0*/
halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700);
halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
}
void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
u8 is_5g)
{
hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
}
void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
u8 is_5g)
{
hal8822b_wifi_only_switch_antenna(wifionlycfg, is_5g);
}
void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
u8 is_5g)
{
if (is_5g)
halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1);
else
halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x2);
}

24
drivers/staging/rtlwifi/btcoexist/halbtc8822bwifionly.h
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@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_HAL8822BWIFIONLYHWCFG_H
#define __INC_HAL8822BWIFIONLYHWCFG_H
void ex_hal8822b_wifi_only_hw_config(struct wifi_only_cfg *wifionlycfg);
void ex_hal8822b_wifi_only_scannotify(struct wifi_only_cfg *wifionlycfg,
u8 is_5g);
void ex_hal8822b_wifi_only_switchbandnotify(struct wifi_only_cfg *wifionlycfg,
u8 is_5g);
void hal8822b_wifi_only_switch_antenna(struct wifi_only_cfg *wifionlycfg,
u8 is_5g);
#endif

1834
drivers/staging/rtlwifi/btcoexist/halbtcoutsrc.c
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791
drivers/staging/rtlwifi/btcoexist/halbtcoutsrc.h
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@ -1,791 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALBTC_OUT_SRC_H__
#define __HALBTC_OUT_SRC_H__
#include "../wifi.h"
#define BTC_COEX_OFFLOAD 0
#define NORMAL_EXEC false
#define FORCE_EXEC true
#define BTC_RF_OFF 0x0
#define BTC_RF_ON 0x1
#define BTC_RF_A RF90_PATH_A
#define BTC_RF_B RF90_PATH_B
#define BTC_RF_C RF90_PATH_C
#define BTC_RF_D RF90_PATH_D
#define BTC_SMSP SINGLEMAC_SINGLEPHY
#define BTC_DMDP DUALMAC_DUALPHY
#define BTC_DMSP DUALMAC_SINGLEPHY
#define BTC_MP_UNKNOWN 0xff
#define IN
#define OUT
#define BT_TMP_BUF_SIZE 100
#define BT_COEX_ANT_TYPE_PG 0
#define BT_COEX_ANT_TYPE_ANTDIV 1
#define BT_COEX_ANT_TYPE_DETECTED 2
#define BTC_MIMO_PS_STATIC 0
#define BTC_MIMO_PS_DYNAMIC 1
#define BTC_RATE_DISABLE 0
#define BTC_RATE_ENABLE 1
/* single Antenna definition */
#define BTC_ANT_PATH_WIFI 0
#define BTC_ANT_PATH_BT 1
#define BTC_ANT_PATH_PTA 2
#define BTC_ANT_PATH_WIFI5G 3
#define BTC_ANT_PATH_AUTO 4
/* dual Antenna definition */
#define BTC_ANT_WIFI_AT_MAIN 0
#define BTC_ANT_WIFI_AT_AUX 1
#define BTC_ANT_WIFI_AT_DIVERSITY 2
/* coupler Antenna definition */
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
#define BTC_ANT_WIFI_AT_CPL_AUX 1
enum btc_bt_reg_type {
BTC_BT_REG_RF = 0,
BTC_BT_REG_MODEM = 1,
BTC_BT_REG_BLUEWIZE = 2,
BTC_BT_REG_VENDOR = 3,
BTC_BT_REG_LE = 4,
BTC_BT_REG_MAX
};
enum btc_chip_interface {
BTC_INTF_UNKNOWN = 0,
BTC_INTF_PCI = 1,
BTC_INTF_USB = 2,
BTC_INTF_SDIO = 3,
BTC_INTF_GSPI = 4,
BTC_INTF_MAX
};
enum btc_chip_type {
BTC_CHIP_UNDEF = 0,
BTC_CHIP_CSR_BC4 = 1,
BTC_CHIP_CSR_BC8 = 2,
BTC_CHIP_RTL8723A = 3,
BTC_CHIP_RTL8821 = 4,
BTC_CHIP_RTL8723B = 5,
BTC_CHIP_MAX
};
enum btc_msg_type {
BTC_MSG_INTERFACE = 0x0,
BTC_MSG_ALGORITHM = 0x1,
BTC_MSG_MAX
};
/* following is for BTC_MSG_INTERFACE */
#define INTF_INIT BIT0
#define INTF_NOTIFY BIT2
/* following is for BTC_ALGORITHM */
#define ALGO_BT_RSSI_STATE BIT0
#define ALGO_WIFI_RSSI_STATE BIT1
#define ALGO_BT_MONITOR BIT2
#define ALGO_TRACE BIT3
#define ALGO_TRACE_FW BIT4
#define ALGO_TRACE_FW_DETAIL BIT5
#define ALGO_TRACE_FW_EXEC BIT6
#define ALGO_TRACE_SW BIT7
#define ALGO_TRACE_SW_DETAIL BIT8
#define ALGO_TRACE_SW_EXEC BIT9
/* following is for wifi link status */
#define WIFI_STA_CONNECTED BIT0
#define WIFI_AP_CONNECTED BIT1
#define WIFI_HS_CONNECTED BIT2
#define WIFI_P2P_GO_CONNECTED BIT3
#define WIFI_P2P_GC_CONNECTED BIT4
#define BTC_RSSI_HIGH(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_HIGH || \
_rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? true : false)
#define BTC_RSSI_MEDIUM(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_MEDIUM || \
_rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? true : false)
#define BTC_RSSI_LOW(_rssi_) \
((_rssi_ == BTC_RSSI_STATE_LOW || \
_rssi_ == BTC_RSSI_STATE_STAY_LOW) ? true : false)
enum btc_power_save_type {
BTC_PS_WIFI_NATIVE = 0,
BTC_PS_LPS_ON = 1,
BTC_PS_LPS_OFF = 2,
BTC_PS_LPS_MAX
};
struct btc_board_info {
/* The following is some board information */
u8 bt_chip_type;
u8 pg_ant_num; /* pg ant number */
u8 btdm_ant_num; /* ant number for btdm */
u8 btdm_ant_num_by_ant_det;
u8 btdm_ant_pos;
u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */
bool tfbga_package;
bool btdm_ant_det_finish;
u8 rfe_type;
u8 ant_div_cfg;
};
enum btc_dbg_opcode {
BTC_DBG_SET_COEX_NORMAL = 0x0,
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
BTC_DBG_MAX
};
enum btc_rssi_state {
BTC_RSSI_STATE_HIGH = 0x0,
BTC_RSSI_STATE_MEDIUM = 0x1,
BTC_RSSI_STATE_LOW = 0x2,
BTC_RSSI_STATE_STAY_HIGH = 0x3,
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
BTC_RSSI_STATE_STAY_LOW = 0x5,
BTC_RSSI_MAX
};
enum btc_wifi_role {
BTC_ROLE_STATION = 0x0,
BTC_ROLE_AP = 0x1,
BTC_ROLE_IBSS = 0x2,
BTC_ROLE_HS_MODE = 0x3,
BTC_ROLE_MAX
};
enum btc_wireless_freq {
BTC_FREQ_2_4G = 0x0,
BTC_FREQ_5G = 0x1,
BTC_FREQ_MAX
};
enum btc_wifi_bw_mode {
BTC_WIFI_BW_LEGACY = 0x0,
BTC_WIFI_BW_HT20 = 0x1,
BTC_WIFI_BW_HT40 = 0x2,
BTC_WIFI_BW_HT80 = 0x3,
BTC_WIFI_BW_MAX
};
enum btc_wifi_traffic_dir {
BTC_WIFI_TRAFFIC_TX = 0x0,
BTC_WIFI_TRAFFIC_RX = 0x1,
BTC_WIFI_TRAFFIC_MAX
};
enum btc_wifi_pnp {
BTC_WIFI_PNP_WAKE_UP = 0x0,
BTC_WIFI_PNP_SLEEP = 0x1,
BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2,
BTC_WIFI_PNP_MAX
};
enum btc_iot_peer {
BTC_IOT_PEER_UNKNOWN = 0,
BTC_IOT_PEER_REALTEK = 1,
BTC_IOT_PEER_REALTEK_92SE = 2,
BTC_IOT_PEER_BROADCOM = 3,
BTC_IOT_PEER_RALINK = 4,
BTC_IOT_PEER_ATHEROS = 5,
BTC_IOT_PEER_CISCO = 6,
BTC_IOT_PEER_MERU = 7,
BTC_IOT_PEER_MARVELL = 8,
BTC_IOT_PEER_REALTEK_SOFTAP = 9,
BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
BTC_IOT_PEER_AIRGO = 11,
BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 12,
BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 13,
BTC_IOT_PEER_MAX,
};
/* for 8723b-d cut large current issue */
enum bt_wifi_coex_state {
BTC_WIFI_STAT_INIT,
BTC_WIFI_STAT_IQK,
BTC_WIFI_STAT_NORMAL_OFF,
BTC_WIFI_STAT_MP_OFF,
BTC_WIFI_STAT_NORMAL,
BTC_WIFI_STAT_ANT_DIV,
BTC_WIFI_STAT_MAX
};
enum bt_ant_type {
BTC_ANT_TYPE_0,
BTC_ANT_TYPE_1,
BTC_ANT_TYPE_2,
BTC_ANT_TYPE_3,
BTC_ANT_TYPE_4,
BTC_ANT_TYPE_MAX
};
enum btc_get_type {
/* type bool */
BTC_GET_BL_HS_OPERATION,
BTC_GET_BL_HS_CONNECTING,
BTC_GET_BL_WIFI_CONNECTED,
BTC_GET_BL_WIFI_BUSY,
BTC_GET_BL_WIFI_SCAN,
BTC_GET_BL_WIFI_LINK,
BTC_GET_BL_WIFI_DHCP,
BTC_GET_BL_WIFI_SOFTAP_IDLE,
BTC_GET_BL_WIFI_SOFTAP_LINKING,
BTC_GET_BL_WIFI_IN_EARLY_SUSPEND,
BTC_GET_BL_WIFI_ROAM,
BTC_GET_BL_WIFI_4_WAY_PROGRESS,
BTC_GET_BL_WIFI_UNDER_5G,
BTC_GET_BL_WIFI_AP_MODE_ENABLE,
BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
BTC_GET_BL_WIFI_UNDER_B_MODE,
BTC_GET_BL_EXT_SWITCH,
BTC_GET_BL_WIFI_IS_IN_MP_MODE,
BTC_GET_BL_IS_ASUS_8723B,
BTC_GET_BL_FW_READY,
BTC_GET_BL_RF4CE_CONNECTED,
/* type s4Byte */
BTC_GET_S4_WIFI_RSSI,
BTC_GET_S4_HS_RSSI,
/* type u32 */
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_WIFI_LINK_STATUS,
BTC_GET_U4_BT_PATCH_VER,
BTC_GET_U4_VENDOR,
BTC_GET_U4_SUPPORTED_VERSION,
BTC_GET_U4_SUPPORTED_FEATURE,
BTC_GET_U4_WIFI_IQK_TOTAL,
BTC_GET_U4_WIFI_IQK_OK,
BTC_GET_U4_WIFI_IQK_FAIL,
/* type u1Byte */
BTC_GET_U1_WIFI_DOT11_CHNL,
BTC_GET_U1_WIFI_CENTRAL_CHNL,
BTC_GET_U1_WIFI_HS_CHNL,
BTC_GET_U1_MAC_PHY_MODE,
BTC_GET_U1_AP_NUM,
BTC_GET_U1_ANT_TYPE,
BTC_GET_U1_IOT_PEER,
/* for 1Ant */
BTC_GET_U1_LPS_MODE,
BTC_GET_BL_BT_SCO_BUSY,
/* for test mode */
BTC_GET_DRIVER_TEST_CFG,
BTC_GET_MAX
};
enum btc_vendor {
BTC_VENDOR_LENOVO,
BTC_VENDOR_ASUS,
BTC_VENDOR_OTHER
};
enum btc_set_type {
/* type bool */
BTC_SET_BL_BT_DISABLE,
BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
BTC_SET_BL_BT_TRAFFIC_BUSY,
BTC_SET_BL_BT_LIMITED_DIG,
BTC_SET_BL_FORCE_TO_ROAM,
BTC_SET_BL_TO_REJ_AP_AGG_PKT,
BTC_SET_BL_BT_CTRL_AGG_SIZE,
BTC_SET_BL_INC_SCAN_DEV_NUM,
BTC_SET_BL_BT_TX_RX_MASK,
BTC_SET_BL_MIRACAST_PLUS_BT,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
BTC_SET_UI_SCAN_SIG_COMPENSATION,
BTC_SET_U1_AGG_BUF_SIZE,
/* type trigger some action */
BTC_SET_ACT_GET_BT_RSSI,
BTC_SET_ACT_AGGREGATE_CTRL,
BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
/********* for 1Ant **********/
/* type bool */
BTC_SET_BL_BT_SCO_BUSY,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
BTC_SET_U1_LPS_VAL,
BTC_SET_U1_RPWM_VAL,
BTC_SET_U1_1ANT_LPS,
BTC_SET_U1_1ANT_RPWM,
/* type trigger some action */
BTC_SET_ACT_LEAVE_LPS,
BTC_SET_ACT_ENTER_LPS,
BTC_SET_ACT_NORMAL_LPS,
BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT,
BTC_SET_ACT_DISABLE_LOW_POWER,
BTC_SET_ACT_UPDATE_RAMASK,
BTC_SET_ACT_SEND_MIMO_PS,
/* BT Coex related */
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
BTC_SET_ACT_CTRL_8723B_ANT,
/***************************/
BTC_SET_MAX
};
enum btc_dbg_disp_type {
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
BTC_DBG_DISP_BT_FW_VER = 0x2,
BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x3,
BTC_DBG_DISP_WIFI_STATUS = 0x04,
BTC_DBG_DISP_MAX
};
enum btc_notify_type_ips {
BTC_IPS_LEAVE = 0x0,
BTC_IPS_ENTER = 0x1,
BTC_IPS_MAX
};
enum btc_notify_type_lps {
BTC_LPS_DISABLE = 0x0,
BTC_LPS_ENABLE = 0x1,
BTC_LPS_MAX
};
enum btc_notify_type_scan {
BTC_SCAN_FINISH = 0x0,
BTC_SCAN_START = 0x1,
BTC_SCAN_START_2G = 0x2,
BTC_SCAN_MAX
};
enum btc_notify_type_switchband {
BTC_NOT_SWITCH = 0x0,
BTC_SWITCH_TO_24G = 0x1,
BTC_SWITCH_TO_5G = 0x2,
BTC_SWITCH_TO_24G_NOFORSCAN = 0x3,
BTC_SWITCH_MAX
};
enum btc_notify_type_associate {
BTC_ASSOCIATE_FINISH = 0x0,
BTC_ASSOCIATE_START = 0x1,
BTC_ASSOCIATE_5G_FINISH = 0x2,
BTC_ASSOCIATE_5G_START = 0x3,
BTC_ASSOCIATE_MAX
};
enum btc_notify_type_media_status {
BTC_MEDIA_DISCONNECT = 0x0,
BTC_MEDIA_CONNECT = 0x1,
BTC_MEDIA_MAX
};
enum btc_notify_type_special_packet {
BTC_PACKET_UNKNOWN = 0x0,
BTC_PACKET_DHCP = 0x1,
BTC_PACKET_ARP = 0x2,
BTC_PACKET_EAPOL = 0x3,
BTC_PACKET_MAX
};
enum hci_ext_bt_operation {
HCI_BT_OP_NONE = 0x0,
HCI_BT_OP_INQUIRY_START = 0x1,
HCI_BT_OP_INQUIRY_FINISH = 0x2,
HCI_BT_OP_PAGING_START = 0x3,
HCI_BT_OP_PAGING_SUCCESS = 0x4,
HCI_BT_OP_PAGING_UNSUCCESS = 0x5,
HCI_BT_OP_PAIRING_START = 0x6,
HCI_BT_OP_PAIRING_FINISH = 0x7,
HCI_BT_OP_BT_DEV_ENABLE = 0x8,
HCI_BT_OP_BT_DEV_DISABLE = 0x9,
HCI_BT_OP_MAX
};
enum btc_notify_type_stack_operation {
BTC_STACK_OP_NONE = 0x0,
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
BTC_STACK_OP_MAX
};
typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u32 data);
typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
u32 bit_mask, u8 data1b);
typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
typedef void (*bfp_btc_local_reg_w1)(void *btc_context, u32 reg_addr, u8 data);
typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
u8 bit_mask, u8 data);
typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask, u32 data);
typedef u32 (*bfp_btc_get_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask);
typedef void (*bfp_btc_set_rf_reg)(void *btc_context, u8 rf_path, u32 reg_addr,
u32 bit_mask, u32 data);
typedef u32 (*bfp_btc_get_rf_reg)(void *btc_context, u8 rf_path,
u32 reg_addr, u32 bit_mask);
typedef void (*bfp_btc_fill_h2c)(void *btc_context, u8 element_id,
u32 cmd_len, u8 *cmd_buffer);
typedef bool (*bfp_btc_get)(void *btcoexist, u8 get_type, void *out_buf);
typedef bool (*bfp_btc_set)(void *btcoexist, u8 set_type, void *in_buf);
typedef u32 (*bfp_btc_get_bt_coex_supported_feature)(void *btcoexist);
typedef u32 (*bfp_btc_get_bt_coex_supported_version)(void *btcoexist);
typedef u32 (*bfp_btc_get_bt_phydm_version)(void *btcoexist);
typedef void (*bfp_btc_phydm_modify_ra_pcr_threshold)(void *btcoexist,
u8 ra_offset_direction,
u8 ra_threshold_offset);
typedef u32 (*bfp_btc_phydm_query_phy_counter)(void *btcoexist,
const char *info_type);
typedef u8 (*bfp_btc_get_ant_det_val_from_bt)(void *btcoexist);
typedef u8 (*bfp_btc_get_ble_scan_type_from_bt)(void *btcoexist);
typedef u32 (*bfp_btc_get_ble_scan_para_from_bt)(void *btcoexist, u8 scan_type);
typedef bool (*bfp_btc_get_bt_afh_map_from_bt)(void *btcoexist, u8 map_type,
u8 *afh_map);
typedef void (*bfp_btc_set_bt_reg)(void *btc_context, u8 reg_type, u32 offset,
u32 value);
typedef u32 (*bfp_btc_get_bt_reg)(void *btc_context, u8 reg_type, u32 offset);
typedef void (*bfp_btc_disp_dbg_msg)(void *btcoexist, u8 disp_type,
struct seq_file *m);
struct btc_bt_info {
bool bt_disabled;
u8 rssi_adjust_for_agc_table_on;
u8 rssi_adjust_for_1ant_coex_type;
bool pre_bt_ctrl_agg_buf_size;
bool bt_busy;
u8 pre_agg_buf_size;
u8 agg_buf_size;
bool limited_dig;
bool pre_reject_agg_pkt;
bool reject_agg_pkt;
bool bt_ctrl_buf_size;
bool increase_scan_dev_num;
bool miracast_plus_bt;
bool bt_ctrl_agg_buf_size;
bool bt_tx_rx_mask;
u16 bt_hci_ver;
u16 bt_real_fw_ver;
u8 bt_fw_ver;
u32 bt_get_fw_ver;
bool bt_disable_low_pwr;
/* the following is for 1Ant solution */
bool bt_ctrl_lps;
bool bt_pwr_save_mode;
bool bt_lps_on;
bool force_to_roam;
u8 force_exec_pwr_cmd_cnt;
u8 lps_val;
u8 rpwm_val;
u32 ra_mask;
u32 afh_map_l;
u32 afh_map_m;
u16 afh_map_h;
u32 bt_supported_feature;
u32 bt_supported_version;
u8 bt_ant_det_val;
u8 bt_ble_scan_type;
u32 bt_ble_scan_para;
};
struct btc_stack_info {
bool profile_notified;
u16 hci_version; /* stack hci version */
u8 num_of_link;
bool bt_link_exist;
bool sco_exist;
bool acl_exist;
bool a2dp_exist;
bool hid_exist;
u8 num_of_hid;
bool pan_exist;
bool unknown_acl_exist;
s8 min_bt_rssi;
};
struct btc_statistics {
u32 cnt_bind;
u32 cnt_init_hw_config;
u32 cnt_init_coex_dm;
u32 cnt_ips_notify;
u32 cnt_lps_notify;
u32 cnt_scan_notify;
u32 cnt_connect_notify;
u32 cnt_media_status_notify;
u32 cnt_special_packet_notify;
u32 cnt_bt_info_notify;
u32 cnt_periodical;
u32 cnt_coex_dm_switch;
u32 cnt_stack_operation_notify;
u32 cnt_dbg_ctrl;
u32 cnt_pre_load_firmware;
u32 cnt_power_on;
};
struct btc_bt_link_info {
bool bt_link_exist;
bool bt_hi_pri_link_exist;
bool sco_exist;
bool sco_only;
bool a2dp_exist;
bool a2dp_only;
bool hid_exist;
bool hid_only;
bool pan_exist;
bool pan_only;
bool slave_role;
bool acl_busy;
};
enum btc_antenna_pos {
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
BTC_ANTENNA_AT_AUX_PORT = 0x2,
};
enum btc_mp_h2c_op_code {
BT_OP_GET_BT_VERSION = 0,
BT_OP_WRITE_REG_ADDR = 12,
BT_OP_WRITE_REG_VALUE = 13,
BT_OP_READ_REG = 17,
BT_OP_GET_AFH_MAP_L = 30,
BT_OP_GET_AFH_MAP_M = 31,
BT_OP_GET_AFH_MAP_H = 32,
BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 42,
BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 43,
BT_OP_GET_BT_ANT_DET_VAL = 44,
BT_OP_GET_BT_BLE_SCAN_PARA = 45,
BT_OP_GET_BT_BLE_SCAN_TYPE = 46,
BT_OP_MAX
};
enum btc_mp_h2c_req_num {
/* 4 bits only */
BT_SEQ_DONT_CARE = 0,
BT_SEQ_GET_BT_VERSION = 0xE,
BT_SEQ_GET_AFH_MAP_L = 0x5,
BT_SEQ_GET_AFH_MAP_M = 0x6,
BT_SEQ_GET_AFH_MAP_H = 0x9,
BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE = 0x7,
BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION = 0x8,
BT_SEQ_GET_BT_ANT_DET_VAL = 0x2,
BT_SEQ_GET_BT_BLE_SCAN_PARA = 0x3,
BT_SEQ_GET_BT_BLE_SCAN_TYPE = 0x4,
};
struct btc_coexist {
/* make sure only one adapter can bind the data context */
bool binded;
/* default adapter */
void *adapter;
struct btc_board_info board_info;
/* some bt info referenced by non-bt module */
struct btc_bt_info bt_info;
struct btc_stack_info stack_info;
enum btc_chip_interface chip_interface;
struct btc_bt_link_info bt_link_info;
/* boolean variables to replace BT_AUTO_REPORT_ONLY_XXXXY_ZANT
* configuration parameters
*/
bool auto_report_1ant;
bool auto_report_2ant;
bool dbg_mode_1ant;
bool dbg_mode_2ant;
bool initilized;
bool stop_coex_dm;
bool manual_control;
struct btc_statistics statistics;
u8 pwr_mode_val[10];
struct completion bt_mp_comp;
/* function pointers - io related */
bfp_btc_r1 btc_read_1byte;
bfp_btc_w1 btc_write_1byte;
bfp_btc_w1_bit_mak btc_write_1byte_bitmask;
bfp_btc_r2 btc_read_2byte;
bfp_btc_w2 btc_write_2byte;
bfp_btc_r4 btc_read_4byte;
bfp_btc_w4 btc_write_4byte;
bfp_btc_local_reg_w1 btc_write_local_reg_1byte;
bfp_btc_set_bb_reg btc_set_bb_reg;
bfp_btc_get_bb_reg btc_get_bb_reg;
bfp_btc_set_rf_reg btc_set_rf_reg;
bfp_btc_get_rf_reg btc_get_rf_reg;
bfp_btc_fill_h2c btc_fill_h2c;
bfp_btc_disp_dbg_msg btc_disp_dbg_msg;
bfp_btc_get btc_get;
bfp_btc_set btc_set;
bfp_btc_set_bt_reg btc_set_bt_reg;
bfp_btc_get_bt_reg btc_get_bt_reg;
bfp_btc_get_bt_coex_supported_feature btc_get_bt_coex_supported_feature;
bfp_btc_get_bt_coex_supported_version btc_get_bt_coex_supported_version;
bfp_btc_get_bt_phydm_version btc_get_bt_phydm_version;
bfp_btc_phydm_modify_ra_pcr_threshold btc_phydm_modify_ra_pcr_threshold;
bfp_btc_phydm_query_phy_counter btc_phydm_query_phy_counter;
bfp_btc_get_ant_det_val_from_bt btc_get_ant_det_val_from_bt;
bfp_btc_get_ble_scan_type_from_bt btc_get_ble_scan_type_from_bt;
bfp_btc_get_ble_scan_para_from_bt btc_get_ble_scan_para_from_bt;
bfp_btc_get_bt_afh_map_from_bt btc_get_bt_afh_map_from_bt;
};
bool halbtc_is_wifi_uplink(struct rtl_priv *adapter);
#define rtl_btc_coexist(rtlpriv) \
((struct btc_coexist *)((rtlpriv)->btcoexist.btc_context))
#define rtl_btc_wifi_only(rtlpriv) \
((struct wifi_only_cfg *)((rtlpriv)->btcoexist.wifi_only_context))
struct wifi_only_cfg;
bool exhalbtc_initlize_variables(struct rtl_priv *rtlpriv);
bool exhalbtc_initlize_variables_wifi_only(struct rtl_priv *rtlpriv);
bool exhalbtc_bind_bt_coex_withadapter(void *adapter);
void exhalbtc_power_on_setting(struct btc_coexist *btcoexist);
void exhalbtc_pre_load_firmware(struct btc_coexist *btcoexist);
void exhalbtc_init_hw_config(struct btc_coexist *btcoexist, bool wifi_only);
void exhalbtc_init_hw_config_wifi_only(struct wifi_only_cfg *wifionly_cfg);
void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist);
void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_scan_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
u8 is_5g);
void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action);
void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
enum rt_media_status media_status);
void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type);
void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
u8 length);
void exhalbtc_rf_status_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_halt_notify(struct btc_coexist *btcoexist);
void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
void exhalbtc_coex_dm_switch(struct btc_coexist *btcoexist);
void exhalbtc_periodical(struct btc_coexist *btcoexist);
void exhalbtc_dbg_control(struct btc_coexist *btcoexist, u8 code, u8 len,
u8 *data);
void exhalbtc_antenna_detection(struct btc_coexist *btcoexist, u32 cent_freq,
u32 offset, u32 span, u32 seconds);
void exhalbtc_stack_update_profile_info(void);
void exhalbtc_set_hci_version(struct btc_coexist *btcoexist, u16 hci_version);
void exhalbtc_set_bt_patch_version(struct btc_coexist *btcoexist,
u16 bt_hci_version, u16 bt_patch_version);
void exhalbtc_update_min_bt_rssi(struct btc_coexist *btcoexist, s8 bt_rssi);
void exhalbtc_set_bt_exist(struct btc_coexist *btcoexist, bool bt_exist);
void exhalbtc_set_chip_type(struct btc_coexist *btcoexist, u8 chip_type);
void exhalbtc_set_ant_num(struct rtl_priv *rtlpriv, u8 type, u8 ant_num);
void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist,
struct seq_file *m);
void exhalbtc_switch_band_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_switch_band_notify_wifi_only(struct wifi_only_cfg *wifionly_cfg,
u8 is_5g);
void exhalbtc_signal_compensation(struct btc_coexist *btcoexist,
u8 *rssi_wifi, u8 *rssi_bt);
void exhalbtc_lps_leave(struct btc_coexist *btcoexist);
void exhalbtc_low_wifi_traffic_notify(struct btc_coexist *btcoexist);
void exhalbtc_set_single_ant_path(struct btc_coexist *btcoexist,
u8 single_ant_path);
/* The following are used by wifi_only case */
enum wifionly_chip_interface {
WIFIONLY_INTF_UNKNOWN = 0,
WIFIONLY_INTF_PCI = 1,
WIFIONLY_INTF_USB = 2,
WIFIONLY_INTF_SDIO = 3,
WIFIONLY_INTF_MAX
};
enum wifionly_customer_id {
CUSTOMER_NORMAL = 0,
CUSTOMER_HP_1 = 1,
};
struct wifi_only_haldata {
u16 customer_id;
u8 efuse_pg_antnum;
u8 efuse_pg_antpath;
u8 rfe_type;
u8 ant_div_cfg;
};
struct wifi_only_cfg {
void *adapter;
struct wifi_only_haldata haldata_info;
enum wifionly_chip_interface chip_interface;
};
static inline
void halwifionly_phy_set_bb_reg(struct wifi_only_cfg *wifi_conly_cfg,
u32 regaddr, u32 bitmask, u32 data)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)wifi_conly_cfg->adapter;
rtl_set_bbreg(rtlpriv->hw, regaddr, bitmask, data);
}
#endif

517
drivers/staging/rtlwifi/btcoexist/rtl_btc.c
View File

@ -1,517 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2009-2013 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "rtl_btc.h"
#include "halbt_precomp.h"
static struct rtl_btc_ops rtl_btc_operation = {
.btc_init_variables = rtl_btc_init_variables,
.btc_init_variables_wifi_only = rtl_btc_init_variables_wifi_only,
.btc_deinit_variables = rtl_btc_deinit_variables,
.btc_init_hal_vars = rtl_btc_init_hal_vars,
.btc_power_on_setting = rtl_btc_power_on_setting,
.btc_init_hw_config = rtl_btc_init_hw_config,
.btc_init_hw_config_wifi_only = rtl_btc_init_hw_config_wifi_only,
.btc_ips_notify = rtl_btc_ips_notify,
.btc_lps_notify = rtl_btc_lps_notify,
.btc_scan_notify = rtl_btc_scan_notify,
.btc_scan_notify_wifi_only = rtl_btc_scan_notify_wifi_only,
.btc_connect_notify = rtl_btc_connect_notify,
.btc_mediastatus_notify = rtl_btc_mediastatus_notify,
.btc_periodical = rtl_btc_periodical,
.btc_halt_notify = rtl_btc_halt_notify,
.btc_btinfo_notify = rtl_btc_btinfo_notify,
.btc_btmpinfo_notify = rtl_btc_btmpinfo_notify,
.btc_is_limited_dig = rtl_btc_is_limited_dig,
.btc_is_disable_edca_turbo = rtl_btc_is_disable_edca_turbo,
.btc_is_bt_disabled = rtl_btc_is_bt_disabled,
.btc_special_packet_notify = rtl_btc_special_packet_notify,
.btc_switch_band_notify = rtl_btc_switch_band_notify,
.btc_switch_band_notify_wifi_only = rtl_btc_switch_band_notify_wifionly,
.btc_record_pwr_mode = rtl_btc_record_pwr_mode,
.btc_get_lps_val = rtl_btc_get_lps_val,
.btc_get_rpwm_val = rtl_btc_get_rpwm_val,
.btc_is_bt_ctrl_lps = rtl_btc_is_bt_ctrl_lps,
.btc_is_bt_lps_on = rtl_btc_is_bt_lps_on,
.btc_get_ampdu_cfg = rtl_btc_get_ampdu_cfg,
.btc_display_bt_coex_info = rtl_btc_display_bt_coex_info,
};
void rtl_btc_display_bt_coex_info(struct rtl_priv *rtlpriv, struct seq_file *m)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist) {
seq_puts(m, "btc_coexist context is NULL!\n");
return;
}
exhalbtc_display_bt_coex_info(btcoexist, m);
}
void rtl_btc_record_pwr_mode(struct rtl_priv *rtlpriv, u8 *buf, u8 len)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
u8 safe_len;
if (!btcoexist)
return;
safe_len = sizeof(btcoexist->pwr_mode_val);
if (safe_len > len)
safe_len = len;
memcpy(btcoexist->pwr_mode_val, buf, safe_len);
}
u8 rtl_btc_get_lps_val(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return 0;
return btcoexist->bt_info.lps_val;
}
u8 rtl_btc_get_rpwm_val(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return 0;
return btcoexist->bt_info.rpwm_val;
}
bool rtl_btc_is_bt_ctrl_lps(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return false;
return btcoexist->bt_info.bt_ctrl_lps;
}
bool rtl_btc_is_bt_lps_on(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return false;
return btcoexist->bt_info.bt_lps_on;
}
void rtl_btc_get_ampdu_cfg(struct rtl_priv *rtlpriv, u8 *reject_agg,
u8 *ctrl_agg_size, u8 *agg_size)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist) {
*reject_agg = false;
*ctrl_agg_size = false;
return;
}
if (reject_agg)
*reject_agg = btcoexist->bt_info.reject_agg_pkt;
if (ctrl_agg_size)
*ctrl_agg_size = btcoexist->bt_info.bt_ctrl_agg_buf_size;
if (agg_size)
*agg_size = btcoexist->bt_info.agg_buf_size;
}
static void rtl_btc_alloc_variable(struct rtl_priv *rtlpriv, bool wifi_only)
{
if (wifi_only)
rtlpriv->btcoexist.wifi_only_context =
kzalloc(sizeof(struct wifi_only_cfg), GFP_KERNEL);
else
rtlpriv->btcoexist.btc_context =
kzalloc(sizeof(struct btc_coexist), GFP_KERNEL);
}
static void rtl_btc_free_variable(struct rtl_priv *rtlpriv)
{
kfree(rtlpriv->btcoexist.btc_context);
rtlpriv->btcoexist.btc_context = NULL;
kfree(rtlpriv->btcoexist.wifi_only_context);
rtlpriv->btcoexist.wifi_only_context = NULL;
}
void rtl_btc_init_variables(struct rtl_priv *rtlpriv)
{
rtl_btc_alloc_variable(rtlpriv, false);
exhalbtc_initlize_variables(rtlpriv);
exhalbtc_bind_bt_coex_withadapter(rtlpriv);
}
void rtl_btc_init_variables_wifi_only(struct rtl_priv *rtlpriv)
{
rtl_btc_alloc_variable(rtlpriv, true);
exhalbtc_initlize_variables_wifi_only(rtlpriv);
}
void rtl_btc_deinit_variables(struct rtl_priv *rtlpriv)
{
rtl_btc_free_variable(rtlpriv);
}
void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv)
{
/* move ant_num, bt_type and single_ant_path to
* exhalbtc_bind_bt_coex_withadapter()
*/
}
void rtl_btc_power_on_setting(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_power_on_setting(btcoexist);
}
void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
u8 bt_exist;
bt_exist = rtl_get_hwpg_bt_exist(rtlpriv);
RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
"%s, bt_exist is %d\n", __func__, bt_exist);
if (!btcoexist)
return;
exhalbtc_init_hw_config(btcoexist, !bt_exist);
exhalbtc_init_coex_dm(btcoexist);
}
void rtl_btc_init_hw_config_wifi_only(struct rtl_priv *rtlpriv)
{
struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
if (!wifionly_cfg)
return;
exhalbtc_init_hw_config_wifi_only(wifionly_cfg);
}
void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_ips_notify(btcoexist, type);
if (type == ERFON) {
/*
* In some situation, it doesn't scan after leaving IPS, and
* this will cause btcoex in wrong state.
*/
exhalbtc_scan_notify(btcoexist, 1);
exhalbtc_scan_notify(btcoexist, 0);
}
}
void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_lps_notify(btcoexist, type);
}
void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_scan_notify(btcoexist, scantype);
}
void rtl_btc_scan_notify_wifi_only(struct rtl_priv *rtlpriv, u8 scantype)
{
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
u8 is_5g = (rtlhal->current_bandtype == BAND_ON_5G);
if (!wifionly_cfg)
return;
exhalbtc_scan_notify_wifi_only(wifionly_cfg, is_5g);
}
void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_connect_notify(btcoexist, action);
}
void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
enum rt_media_status mstatus)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_mediastatus_notify(btcoexist, mstatus);
}
void rtl_btc_periodical(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
/*rtl_bt_dm_monitor();*/
exhalbtc_periodical(btcoexist);
}
void rtl_btc_halt_notify(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_halt_notify(btcoexist);
}
void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
exhalbtc_bt_info_notify(btcoexist, tmp_buf, length);
}
void rtl_btc_btmpinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
u8 extid, seq, len;
u16 bt_real_fw_ver;
u8 bt_fw_ver;
u8 *data;
if (!btcoexist)
return;
if ((length < 4) || (!tmp_buf))
return;
extid = tmp_buf[0];
/* not response from BT FW then exit*/
if (extid != 1) /* C2H_TRIG_BY_BT_FW = 1 */
return;
len = tmp_buf[1] >> 4;
seq = tmp_buf[2] >> 4;
data = &tmp_buf[3];
/* BT Firmware version response */
switch (seq) {
case BT_SEQ_GET_BT_VERSION:
bt_real_fw_ver = tmp_buf[3] | (tmp_buf[4] << 8);
bt_fw_ver = tmp_buf[5];
btcoexist->bt_info.bt_real_fw_ver = bt_real_fw_ver;
btcoexist->bt_info.bt_fw_ver = bt_fw_ver;
break;
case BT_SEQ_GET_AFH_MAP_L:
btcoexist->bt_info.afh_map_l = le32_to_cpu(*(__le32 *)data);
break;
case BT_SEQ_GET_AFH_MAP_M:
btcoexist->bt_info.afh_map_m = le32_to_cpu(*(__le32 *)data);
break;
case BT_SEQ_GET_AFH_MAP_H:
btcoexist->bt_info.afh_map_h = le16_to_cpu(*(__le16 *)data);
break;
case BT_SEQ_GET_BT_COEX_SUPPORTED_FEATURE:
btcoexist->bt_info.bt_supported_feature = tmp_buf[3] |
(tmp_buf[4] << 8);
break;
case BT_SEQ_GET_BT_COEX_SUPPORTED_VERSION:
btcoexist->bt_info.bt_supported_version = tmp_buf[3] |
(tmp_buf[4] << 8);
break;
case BT_SEQ_GET_BT_ANT_DET_VAL:
btcoexist->bt_info.bt_ant_det_val = tmp_buf[3];
break;
case BT_SEQ_GET_BT_BLE_SCAN_PARA:
btcoexist->bt_info.bt_ble_scan_para = tmp_buf[3] |
(tmp_buf[4] << 8) |
(tmp_buf[5] << 16) |
(tmp_buf[6] << 24);
break;
case BT_SEQ_GET_BT_BLE_SCAN_TYPE:
btcoexist->bt_info.bt_ble_scan_type = tmp_buf[3];
break;
}
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
"btmpinfo complete req_num=%d\n", seq);
complete(&btcoexist->bt_mp_comp);
}
bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return false;
return btcoexist->bt_info.limited_dig;
}
bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
{
bool bt_change_edca = false;
u32 cur_edca_val;
u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
u32 edca_hs;
u32 edca_addr = 0x504;
cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
if (halbtc_is_wifi_uplink(rtlpriv)) {
if (cur_edca_val != edca_bt_hs_uplink) {
edca_hs = edca_bt_hs_uplink;
bt_change_edca = true;
}
} else {
if (cur_edca_val != edca_bt_hs_downlink) {
edca_hs = edca_bt_hs_downlink;
bt_change_edca = true;
}
}
if (bt_change_edca)
rtl_write_dword(rtlpriv, edca_addr, edca_hs);
return true;
}
bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return true;
/* It seems 'bt_disabled' is never be initialized or set. */
if (btcoexist->bt_info.bt_disabled)
return true;
else
return false;
}
void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
if (!btcoexist)
return;
return exhalbtc_special_packet_notify(btcoexist, pkt_type);
}
void rtl_btc_switch_band_notify(struct rtl_priv *rtlpriv, u8 band_type,
bool scanning)
{
struct btc_coexist *btcoexist = rtl_btc_coexist(rtlpriv);
u8 type = BTC_NOT_SWITCH;
if (!btcoexist)
return;
switch (band_type) {
case BAND_ON_2_4G:
if (scanning)
type = BTC_SWITCH_TO_24G;
else
type = BTC_SWITCH_TO_24G_NOFORSCAN;
break;
case BAND_ON_5G:
type = BTC_SWITCH_TO_5G;
break;
}
if (type != BTC_NOT_SWITCH)
exhalbtc_switch_band_notify(btcoexist, type);
}
void rtl_btc_switch_band_notify_wifionly(struct rtl_priv *rtlpriv, u8 band_type,
bool scanning)
{
struct wifi_only_cfg *wifionly_cfg = rtl_btc_wifi_only(rtlpriv);
u8 is_5g = (band_type == BAND_ON_5G);
if (!wifionly_cfg)
return;
exhalbtc_switch_band_notify_wifi_only(wifionly_cfg, is_5g);
}
struct rtl_btc_ops *rtl_btc_get_ops_pointer(void)
{
return &rtl_btc_operation;
}
enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
if (bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED)
m_status = RT_MEDIA_CONNECT;
return m_status;
}
u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv)
{
return rtlpriv->btcoexist.btc_info.btcoexist;
}

64
drivers/staging/rtlwifi/btcoexist/rtl_btc.h
View File

@ -1,64 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BTC_H__
#define __RTL_BTC_H__
#include "halbt_precomp.h"
void rtl_btc_init_variables(struct rtl_priv *rtlpriv);
void rtl_btc_init_variables_wifi_only(struct rtl_priv *rtlpriv);
void rtl_btc_deinit_variables(struct rtl_priv *rtlpriv);
void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv);
void rtl_btc_power_on_setting(struct rtl_priv *rtlpriv);
void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv);
void rtl_btc_init_hw_config_wifi_only(struct rtl_priv *rtlpriv);
void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type);
void rtl_btc_lps_notify(struct rtl_priv *rtlpriv, u8 type);
void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype);
void rtl_btc_scan_notify_wifi_only(struct rtl_priv *rtlpriv, u8 scantype);
void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action);
void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv,
enum rt_media_status mstatus);
void rtl_btc_periodical(struct rtl_priv *rtlpriv);
void rtl_btc_halt_notify(struct rtl_priv *rtlpriv);
void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 *tmpbuf, u8 length);
void rtl_btc_btmpinfo_notify(struct rtl_priv *rtlpriv, u8 *tmp_buf, u8 length);
bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv);
bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv);
bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv);
void rtl_btc_special_packet_notify(struct rtl_priv *rtlpriv, u8 pkt_type);
void rtl_btc_switch_band_notify(struct rtl_priv *rtlpriv, u8 band_type,
bool scanning);
void rtl_btc_switch_band_notify_wifionly(struct rtl_priv *rtlpriv, u8 band_type,
bool scanning);
void rtl_btc_display_bt_coex_info(struct rtl_priv *rtlpriv, struct seq_file *m);
void rtl_btc_record_pwr_mode(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
u8 rtl_btc_get_lps_val(struct rtl_priv *rtlpriv);
u8 rtl_btc_get_rpwm_val(struct rtl_priv *rtlpriv);
bool rtl_btc_is_bt_ctrl_lps(struct rtl_priv *rtlpriv);
bool rtl_btc_is_bt_lps_on(struct rtl_priv *rtlpriv);
void rtl_btc_get_ampdu_cfg(struct rtl_priv *rtlpriv, u8 *reject_agg,
u8 *ctrl_agg_size, u8 *agg_size);
struct rtl_btc_ops *rtl_btc_get_ops_pointer(void);
u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_single_ant_path(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_package_type(struct rtl_priv *rtlpriv);
enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw);
#endif

315
drivers/staging/rtlwifi/cam.c
View File

@ -1,315 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
#include <linux/export.h>
void rtl_cam_reset_sec_info(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->sec.use_defaultkey = false;
rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
rtlpriv->sec.pairwise_key = NULL;
}
static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
u8 *mac_addr, u8 *key_cont_128, u16 us_config)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_command;
u32 target_content = 0;
int entry_i;
RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content :",
key_cont_128, 16);
/* 0-1 config + mac, 2-5 fill 128key,6-7 are reserved */
for (entry_i = CAM_CONTENT_COUNT - 1; entry_i >= 0; entry_i--) {
target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
target_command = target_command | BIT(31) | BIT(16);
if (entry_i == 0) {
target_content = (u32)(*(mac_addr + 0)) << 16 |
(u32)(*(mac_addr + 1)) << 24 |
(u32)us_config;
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE %x: %x\n",
rtlpriv->cfg->maps[WCAMI], target_content);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"The Key ID is %d\n", entry_no);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE %x: %x\n",
rtlpriv->cfg->maps[RWCAM], target_command);
} else if (entry_i == 1) {
target_content = (u32)(*(mac_addr + 5)) << 24 |
(u32)(*(mac_addr + 4)) << 16 |
(u32)(*(mac_addr + 3)) << 8 |
(u32)(*(mac_addr + 2));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE A4: %x\n", target_content);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE A0: %x\n", target_command);
} else {
target_content =
(u32)(*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
24 | (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 2))
<< 16 |
(u32)(*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
| (u32)(*(key_cont_128 + (entry_i * 4 - 8) + 0));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE A4: %x\n", target_content);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"WRITE A0: %x\n", target_command);
}
}
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"after set key, usconfig:%x\n", us_config);
}
u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content)
{
u32 us_config;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n",
ul_entry_idx, ul_key_id, ul_enc_alg,
ul_default_key, mac_addr);
if (ul_key_id == TOTAL_CAM_ENTRY) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"ulKeyId exceed!\n");
return 0;
}
if (ul_default_key == 1)
us_config = CFG_VALID | ((u16)(ul_enc_alg) << 2);
else
us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
(u8 *)key_content, us_config);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "end\n");
return 1;
}
int rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
u8 *mac_addr, u32 ul_key_id)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id);
ul_command = ul_key_id * CAM_CONTENT_COUNT;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"%s(): WRITE A4: %x\n", __func__, 0);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"%s(): WRITE A0: %x\n", __func__, ul_command);
return 0;
}
void rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
ul_command = BIT(31) | BIT(30);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
}
void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_enc_algo;
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
ul_content = (uc_index & 3) | ((u16)(ul_enc_algo) << 2);
ul_content |= BIT(15);
ul_command = CAM_CONTENT_COUNT * uc_index;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"%s(): WRITE A4: %x\n", __func__, ul_content);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"%s(): WRITE A0: %x\n", __func__, ul_command);
}
void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_encalgo;
u8 entry_i;
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
if (entry_i == 0) {
ul_content =
(uc_index & 0x03) | ((u16)(ul_encalgo) << 2);
ul_content |= BIT(15);
} else {
ul_content = 0;
}
ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"%s(): WRITE A4: %x\n", __func__, ul_content);
RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
"%s(): WRITE A0: %x\n", __func__, ul_command);
}
}
u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> 4;
u8 entry_idx = 0;
u8 i, *addr;
if (!sta_addr) {
pr_err("sta_addr is NULL.\n");
return TOTAL_CAM_ENTRY;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
if (ether_addr_equal_unaligned(addr, sta_addr))
return i;
}
/* Get a free CAM entry. */
for (entry_idx = 4; entry_idx < TOTAL_CAM_ENTRY; entry_idx++) {
if ((bitmap & BIT(0)) == 0) {
pr_err("-----hwsec_cam_bitmap: 0x%x entry_idx=%d\n",
rtlpriv->sec.hwsec_cam_bitmap, entry_idx);
rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx;
memcpy(rtlpriv->sec.hwsec_cam_sta_addr[entry_idx],
sta_addr, ETH_ALEN);
return entry_idx;
}
bitmap = bitmap >> 1;
}
return TOTAL_CAM_ENTRY;
}
void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap;
u8 i, *addr;
if (!sta_addr) {
pr_err("sta_addr is NULL.\n");
return;
}
if (is_zero_ether_addr(sta_addr)) {
pr_err("sta_addr is %pM\n", sta_addr);
return;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> i;
if (((bitmap & BIT(0)) == BIT(0)) &&
(ether_addr_equal_unaligned(addr, sta_addr))) {
/* Remove from HW Security CAM */
eth_zero_addr(rtlpriv->sec.hwsec_cam_sta_addr[i]);
rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
"&&&&&&&&&del entry %d\n", i);
}
}
}

39
drivers/staging/rtlwifi/cam.h
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@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CAM_H_
#define __RTL_CAM_H_
#define CAM_CONTENT_COUNT 8
#define CFG_VALID BIT(15)
#define PAIRWISE_KEYIDX 0
#define CAM_PAIRWISE_KEY_POSITION 4
#define CAM_CONFIG_NO_USEDK 0
void rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content);
int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id);
void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
void rtl_cam_reset_sec_info(struct ieee80211_hw *hw);
u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr);
void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr);
#endif

1994
drivers/staging/rtlwifi/core.c
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File diff suppressed because it is too large Load Diff

71
drivers/staging/rtlwifi/core.h
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@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CORE_H__
#define __RTL_CORE_H__
#define RTL_SUPPORTED_FILTERS \
(FIF_ALLMULTI | FIF_CONTROL | \
FIF_OTHER_BSS | \
FIF_FCSFAIL | \
FIF_BCN_PRBRESP_PROMISC)
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX 0x3e
#define DM_DIG_MIN 0x1e
#define DM_DIG_MAX_AP 0x32
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
enum cck_packet_detection_threshold {
CCK_PD_STAGE_LOWRSSI = 0,
CCK_PD_STAGE_HIGHRSSI = 1,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_HIGH = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum dm_dig_connect_e {
DIG_STA_DISCONNECT,
DIG_STA_CONNECT,
DIG_STA_BEFORE_CONNECT,
DIG_MULTISTA_DISCONNECT,
DIG_MULTISTA_CONNECT,
DIG_AP_DISCONNECT,
DIG_AP_CONNECT,
DIG_AP_ADD_STATION,
DIG_CONNECT_MAX
};
extern const struct ieee80211_ops rtl_ops;
void rtl_fw_cb(const struct firmware *firmware, void *context);
void rtl_wowlan_fw_cb(const struct firmware *firmware, void *context);
bool rtl_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
bool rtl_btc_status_false(void);
void rtl_dm_diginit(struct ieee80211_hw *hw, u32 cur_igval);
#endif

624
drivers/staging/rtlwifi/debug.c
View File

@ -1,624 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
#include <linux/moduleparam.h>
#include <linux/vmalloc.h>
#ifdef CONFIG_RTLWIFI_DEBUG_ST
void _rtl_dbg_trace(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *fmt, ...)
{
if (unlikely((comp & rtlpriv->cfg->mod_params->debug_mask) &&
level <= rtlpriv->cfg->mod_params->debug_level)) {
struct va_format vaf;
va_list args;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
pr_info(":<%lx> %pV", in_interrupt(), &vaf);
va_end(args);
}
}
void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *fmt, ...)
{
if (unlikely((comp & rtlpriv->cfg->mod_params->debug_mask) &&
level <= rtlpriv->cfg->mod_params->debug_level)) {
struct va_format vaf;
va_list args;
va_start(args, fmt);
vaf.fmt = fmt;
vaf.va = &args;
pr_info("%pV", &vaf);
va_end(args);
}
}
void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *titlestring,
const void *hexdata, int hexdatalen)
{
if (unlikely(((comp) & rtlpriv->cfg->mod_params->debug_mask) &&
((level) <= rtlpriv->cfg->mod_params->debug_level))) {
pr_info("In process \"%s\" (pid %i): %s\n",
current->comm, current->pid, titlestring);
print_hex_dump_bytes("", DUMP_PREFIX_NONE,
hexdata, hexdatalen);
}
}
struct rtl_debugfs_priv {
struct rtl_priv *rtlpriv;
int (*cb_read)(struct seq_file *m, void *v);
ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
size_t count, loff_t *loff);
u32 cb_data;
};
static struct dentry *debugfs_topdir;
static int rtl_debug_get_common(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
return debugfs_priv->cb_read(m, v);
}
static int dl_debug_open_common(struct inode *inode, struct file *file)
{
return single_open(file, rtl_debug_get_common, inode->i_private);
}
static const struct file_operations file_ops_common = {
.open = dl_debug_open_common,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int rtl_debug_get_mac_page(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
u32 page = debugfs_priv->cb_data;
int i, n;
int max = 0xff;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
#define RTL_DEBUG_IMPL_MAC_SERIES(page, addr) \
static struct rtl_debugfs_priv rtl_debug_priv_mac_ ##page = { \
.cb_read = rtl_debug_get_mac_page, \
.cb_data = addr, \
}
RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
RTL_DEBUG_IMPL_MAC_SERIES(4, 0x0400);
RTL_DEBUG_IMPL_MAC_SERIES(5, 0x0500);
RTL_DEBUG_IMPL_MAC_SERIES(6, 0x0600);
RTL_DEBUG_IMPL_MAC_SERIES(7, 0x0700);
RTL_DEBUG_IMPL_MAC_SERIES(10, 0x1000);
RTL_DEBUG_IMPL_MAC_SERIES(11, 0x1100);
RTL_DEBUG_IMPL_MAC_SERIES(12, 0x1200);
RTL_DEBUG_IMPL_MAC_SERIES(13, 0x1300);
RTL_DEBUG_IMPL_MAC_SERIES(14, 0x1400);
RTL_DEBUG_IMPL_MAC_SERIES(15, 0x1500);
RTL_DEBUG_IMPL_MAC_SERIES(16, 0x1600);
RTL_DEBUG_IMPL_MAC_SERIES(17, 0x1700);
static int rtl_debug_get_bb_page(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
struct ieee80211_hw *hw = rtlpriv->hw;
u32 page = debugfs_priv->cb_data;
int i, n;
int max = 0xff;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
#define RTL_DEBUG_IMPL_BB_SERIES(page, addr) \
static struct rtl_debugfs_priv rtl_debug_priv_bb_ ##page = { \
.cb_read = rtl_debug_get_bb_page, \
.cb_data = addr, \
}
RTL_DEBUG_IMPL_BB_SERIES(8, 0x0800);
RTL_DEBUG_IMPL_BB_SERIES(9, 0x0900);
RTL_DEBUG_IMPL_BB_SERIES(a, 0x0a00);
RTL_DEBUG_IMPL_BB_SERIES(b, 0x0b00);
RTL_DEBUG_IMPL_BB_SERIES(c, 0x0c00);
RTL_DEBUG_IMPL_BB_SERIES(d, 0x0d00);
RTL_DEBUG_IMPL_BB_SERIES(e, 0x0e00);
RTL_DEBUG_IMPL_BB_SERIES(f, 0x0f00);
RTL_DEBUG_IMPL_BB_SERIES(18, 0x1800);
RTL_DEBUG_IMPL_BB_SERIES(19, 0x1900);
RTL_DEBUG_IMPL_BB_SERIES(1a, 0x1a00);
RTL_DEBUG_IMPL_BB_SERIES(1b, 0x1b00);
RTL_DEBUG_IMPL_BB_SERIES(1c, 0x1c00);
RTL_DEBUG_IMPL_BB_SERIES(1d, 0x1d00);
RTL_DEBUG_IMPL_BB_SERIES(1e, 0x1e00);
RTL_DEBUG_IMPL_BB_SERIES(1f, 0x1f00);
static int rtl_debug_get_reg_rf(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
struct ieee80211_hw *hw = rtlpriv->hw;
enum radio_path rfpath = debugfs_priv->cb_data;
int i, n;
int max = 0x40;
if (IS_HARDWARE_TYPE_8822B(rtlpriv))
max = 0xff;
seq_printf(m, "\nPATH(%d)", rfpath);
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n);
for (i = 0; i < 4 && n <= max; n += 1, i++)
seq_printf(m, "%8.8x ",
rtl_get_rfreg(hw, rfpath, n, 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
#define RTL_DEBUG_IMPL_RF_SERIES(page, addr) \
static struct rtl_debugfs_priv rtl_debug_priv_rf_ ##page = { \
.cb_read = rtl_debug_get_reg_rf, \
.cb_data = addr, \
}
RTL_DEBUG_IMPL_RF_SERIES(a, RF90_PATH_A);
RTL_DEBUG_IMPL_RF_SERIES(b, RF90_PATH_B);
static int rtl_debug_get_cam_register(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
int start = debugfs_priv->cb_data;
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
int end = (start + 11 > TOTAL_CAM_ENTRY ? TOTAL_CAM_ENTRY : start + 11);
/* This dump the current register page */
seq_printf(m,
"\n#################### SECURITY CAM (%d-%d) ##################\n",
start, end - 1);
for (j = start; j < end; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
/* polling bit, and No Write enable, and address */
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
/* Check polling bit is clear */
while ((i--) >= 0) {
ulstatus = rtl_read_dword(
rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31))
continue;
else
break;
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
#define RTL_DEBUG_IMPL_CAM_SERIES(page, addr) \
static struct rtl_debugfs_priv rtl_debug_priv_cam_ ##page = { \
.cb_read = rtl_debug_get_cam_register, \
.cb_data = addr, \
}
RTL_DEBUG_IMPL_CAM_SERIES(1, 0);
RTL_DEBUG_IMPL_CAM_SERIES(2, 11);
RTL_DEBUG_IMPL_CAM_SERIES(3, 22);
static int rtl_debug_get_btcoex(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
if (rtlpriv->cfg->ops->get_btc_status())
rtlpriv->btcoexist.btc_ops->btc_display_bt_coex_info(rtlpriv,
m);
seq_puts(m, "\n");
return 0;
}
static struct rtl_debugfs_priv rtl_debug_priv_btcoex = {
.cb_read = rtl_debug_get_btcoex,
.cb_data = 0,
};
static ssize_t rtl_debugfs_set_write_reg(struct file *filp,
const char __user *buffer,
size_t count, loff_t *loff)
{
struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
char tmp[32 + 1];
int tmp_len;
u32 addr, val, len;
int num;
if (count < 3)
return -EFAULT;
tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
if (!buffer || copy_from_user(tmp, buffer, tmp_len))
return count;
tmp[tmp_len] = '\0';
/* write BB/MAC register */
num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
if (num != 3)
return count;
switch (len) {
case 1:
rtl_write_byte(rtlpriv, addr, (u8)val);
break;
case 2:
rtl_write_word(rtlpriv, addr, (u16)val);
break;
case 4:
rtl_write_dword(rtlpriv, addr, val);
break;
default:
/*printk("error write length=%d", len);*/
break;
}
return count;
}
static struct rtl_debugfs_priv rtl_debug_priv_write_reg = {
.cb_write = rtl_debugfs_set_write_reg,
};
static ssize_t rtl_debugfs_set_write_h2c(struct file *filp,
const char __user *buffer,
size_t count, loff_t *loff)
{
struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
struct ieee80211_hw *hw = rtlpriv->hw;
char tmp[32 + 1];
int tmp_len;
u8 h2c_len, h2c_data_packed[8];
int h2c_data[8]; /* idx 0: cmd */
int i;
if (count < 3)
return -EFAULT;
tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
if (!buffer || copy_from_user(tmp, buffer, tmp_len))
return count;
tmp[tmp_len] = '\0';
h2c_len = sscanf(tmp, "%X %X %X %X %X %X %X %X",
&h2c_data[0], &h2c_data[1],
&h2c_data[2], &h2c_data[3],
&h2c_data[4], &h2c_data[5],
&h2c_data[6], &h2c_data[7]);
if (h2c_len <= 0)
return count;
for (i = 0; i < h2c_len; i++)
h2c_data_packed[i] = (u8)h2c_data[i];
rtlpriv->cfg->ops->fill_h2c_cmd(hw, h2c_data_packed[0],
h2c_len - 1,
&h2c_data_packed[1]);
return count;
}
static struct rtl_debugfs_priv rtl_debug_priv_write_h2c = {
.cb_write = rtl_debugfs_set_write_h2c,
};
static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp,
const char __user *buffer,
size_t count, loff_t *loff)
{
struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
struct ieee80211_hw *hw = rtlpriv->hw;
char tmp[32 + 1];
int tmp_len;
int num;
int path;
u32 addr, bitmask, data;
if (count < 3)
return -EFAULT;
tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count);
if (!buffer || copy_from_user(tmp, buffer, tmp_len))
return count;
tmp[tmp_len] = '\0';
num = sscanf(tmp, "%X %X %X %X",
&path, &addr, &bitmask, &data);
if (num != 4) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
"Format is <path> <addr> <mask> <data>\n");
return count;
}
rtl_set_rfreg(hw, path, addr, bitmask, data);
return count;
}
static struct rtl_debugfs_priv rtl_debug_priv_write_rfreg = {
.cb_write = rtl_debugfs_set_write_rfreg,
};
static int rtl_debugfs_close(struct inode *inode, struct file *filp)
{
return 0;
}
static ssize_t rtl_debugfs_common_write(struct file *filp,
const char __user *buffer,
size_t count, loff_t *loff)
{
struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
return debugfs_priv->cb_write(filp, buffer, count, loff);
}
static const struct file_operations file_ops_common_write = {
.owner = THIS_MODULE,
.write = rtl_debugfs_common_write,
.open = simple_open,
.release = rtl_debugfs_close,
};
static ssize_t rtl_debugfs_phydm_cmd(struct file *filp,
const char __user *buffer,
size_t count, loff_t *loff)
{
struct rtl_debugfs_priv *debugfs_priv = filp->private_data;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
char tmp[64];
if (!rtlpriv->dbg.msg_buf)
return -ENOMEM;
if (!rtlpriv->phydm.ops)
return -EFAULT;
if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
tmp[count] = '\0';
rtlpriv->phydm.ops->phydm_debug_cmd(rtlpriv, tmp, count,
rtlpriv->dbg.msg_buf,
80 * 25);
}
return count;
}
static int rtl_debug_get_phydm_cmd(struct seq_file *m, void *v)
{
struct rtl_debugfs_priv *debugfs_priv = m->private;
struct rtl_priv *rtlpriv = debugfs_priv->rtlpriv;
if (rtlpriv->dbg.msg_buf)
seq_puts(m, rtlpriv->dbg.msg_buf);
return 0;
}
static int rtl_debugfs_open_rw(struct inode *inode, struct file *filp)
{
int ret = 0;
if (filp->f_mode & FMODE_READ)
ret = single_open(filp, rtl_debug_get_common, inode->i_private);
else
filp->private_data = inode->i_private;
return ret;
}
static int rtl_debugfs_close_rw(struct inode *inode, struct file *filp)
{
if (filp->f_mode == FMODE_READ)
single_release(inode, filp);
return 0;
}
static struct rtl_debugfs_priv rtl_debug_priv_phydm_cmd = {
.cb_read = rtl_debug_get_phydm_cmd,
.cb_write = rtl_debugfs_phydm_cmd,
.cb_data = 0,
};
static const struct file_operations file_ops_common_rw = {
.owner = THIS_MODULE,
.open = rtl_debugfs_open_rw,
.release = rtl_debugfs_close_rw,
.read = seq_read,
.llseek = seq_lseek,
.write = rtl_debugfs_common_write,
};
#define RTL_DEBUGFS_ADD_CORE(name, mode, fopname) \
do { \
rtl_debug_priv_ ##name.rtlpriv = rtlpriv; \
debugfs_create_file(#name, mode, parent, \
&rtl_debug_priv_ ##name, \
&file_ops_ ##fopname); \
} while (0)
#define RTL_DEBUGFS_ADD(name) \
RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0444, common)
#define RTL_DEBUGFS_ADD_W(name) \
RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0222, common_write)
#define RTL_DEBUGFS_ADD_RW(name) \
RTL_DEBUGFS_ADD_CORE(name, S_IFREG | 0666, common_rw)
void rtl_debug_add_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct dentry *parent;
rtlpriv->dbg.msg_buf = vzalloc(80 * 25);
snprintf(rtlpriv->dbg.debugfs_name, 18, "%pMF", rtlefuse->dev_addr);
rtlpriv->dbg.debugfs_dir =
debugfs_create_dir(rtlpriv->dbg.debugfs_name, debugfs_topdir);
if (!rtlpriv->dbg.debugfs_dir) {
pr_err("Unable to init debugfs:/%s/%s\n", rtlpriv->cfg->name,
rtlpriv->dbg.debugfs_name);
return;
}
parent = rtlpriv->dbg.debugfs_dir;
RTL_DEBUGFS_ADD(mac_0);
RTL_DEBUGFS_ADD(mac_1);
RTL_DEBUGFS_ADD(mac_2);
RTL_DEBUGFS_ADD(mac_3);
RTL_DEBUGFS_ADD(mac_4);
RTL_DEBUGFS_ADD(mac_5);
RTL_DEBUGFS_ADD(mac_6);
RTL_DEBUGFS_ADD(mac_7);
RTL_DEBUGFS_ADD(bb_8);
RTL_DEBUGFS_ADD(bb_9);
RTL_DEBUGFS_ADD(bb_a);
RTL_DEBUGFS_ADD(bb_b);
RTL_DEBUGFS_ADD(bb_c);
RTL_DEBUGFS_ADD(bb_d);
RTL_DEBUGFS_ADD(bb_e);
RTL_DEBUGFS_ADD(bb_f);
RTL_DEBUGFS_ADD(mac_10);
RTL_DEBUGFS_ADD(mac_11);
RTL_DEBUGFS_ADD(mac_12);
RTL_DEBUGFS_ADD(mac_13);
RTL_DEBUGFS_ADD(mac_14);
RTL_DEBUGFS_ADD(mac_15);
RTL_DEBUGFS_ADD(mac_16);
RTL_DEBUGFS_ADD(mac_17);
RTL_DEBUGFS_ADD(bb_18);
RTL_DEBUGFS_ADD(bb_19);
RTL_DEBUGFS_ADD(bb_1a);
RTL_DEBUGFS_ADD(bb_1b);
RTL_DEBUGFS_ADD(bb_1c);
RTL_DEBUGFS_ADD(bb_1d);
RTL_DEBUGFS_ADD(bb_1e);
RTL_DEBUGFS_ADD(bb_1f);
RTL_DEBUGFS_ADD(rf_a);
RTL_DEBUGFS_ADD(rf_b);
RTL_DEBUGFS_ADD(cam_1);
RTL_DEBUGFS_ADD(cam_2);
RTL_DEBUGFS_ADD(cam_3);
RTL_DEBUGFS_ADD(btcoex);
RTL_DEBUGFS_ADD_W(write_reg);
RTL_DEBUGFS_ADD_W(write_h2c);
RTL_DEBUGFS_ADD_W(write_rfreg);
RTL_DEBUGFS_ADD_RW(phydm_cmd);
}
void rtl_debug_remove_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
debugfs_remove_recursive(rtlpriv->dbg.debugfs_dir);
rtlpriv->dbg.debugfs_dir = NULL;
vfree(rtlpriv->dbg.msg_buf);
}
void rtl_debugfs_add_topdir(void)
{
debugfs_topdir = debugfs_create_dir("rtlwifi", NULL);
}
void rtl_debugfs_remove_topdir(void)
{
debugfs_remove_recursive(debugfs_topdir);
}
#endif

223
drivers/staging/rtlwifi/debug.h
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@ -1,223 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*****************************************************************************/
#ifndef __RTL_DEBUG_H__
#define __RTL_DEBUG_H__
/*--------------------------------------------------------------
* Debug level
*------------------------------------------------------------
*
*Fatal bug.
*For example, Tx/Rx/IO locked up,
*memory access violation,
*resource allocation failed,
*unexpected HW behavior, HW BUG
*and so on.
*/
/*#define DBG_EMERG 0 */
/*Abnormal, rare, or unexpected cases.
*For example, Packet/IO Ctl canceled,
*device surprisingly removed and so on.
*/
#define DBG_WARNING 2
/*Normal case driver developer should
*open, we can see link status like
*assoc/AddBA/DHCP/adapter start and
*so on basic and useful infromations.
*/
#define DBG_DMESG 3
/*Normal case with useful information
*about current SW or HW state.
*For example, Tx/Rx descriptor to fill,
*Tx/Rx descriptor completed status,
*SW protocol state change, dynamic
*mechanism state change and so on.
*/
#define DBG_LOUD 4
/*Normal case with detail execution
*flow or information.
*/
#define DBG_TRACE 5
/*--------------------------------------------------------------
* Define the rt_trace components
*--------------------------------------------------------------
*/
#define COMP_ERR BIT(0)
#define COMP_FW BIT(1)
#define COMP_INIT BIT(2) /*For init/deinit */
#define COMP_RECV BIT(3) /*For Rx. */
#define COMP_SEND BIT(4) /*For Tx. */
#define COMP_MLME BIT(5) /*For MLME. */
#define COMP_SCAN BIT(6) /*For Scan. */
#define COMP_INTR BIT(7) /*For interrupt Related. */
#define COMP_LED BIT(8) /*For LED. */
#define COMP_SEC BIT(9) /*For sec. */
#define COMP_BEACON BIT(10) /*For beacon. */
#define COMP_RATE BIT(11) /*For rate. */
#define COMP_RXDESC BIT(12) /*For rx desc. */
#define COMP_DIG BIT(13) /*For DIG */
#define COMP_TXAGC BIT(14) /*For Tx power */
#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
#define COMP_BB_POWERSAVING BIT(18)
#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
#define COMP_RF BIT(20) /*For RF. */
#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
#define COMP_RATR BIT(22)
#define COMP_CMD BIT(23)
#define COMP_EFUSE BIT(24)
#define COMP_QOS BIT(25)
#define COMP_MAC80211 BIT(26)
#define COMP_REGD BIT(27)
#define COMP_CHAN BIT(28)
#define COMP_USB BIT(29)
#define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
#define COMP_BT_COEXIST BIT(30)
#define COMP_IQK BIT(31)
#define COMP_TX_REPORT BIT_ULL(32)
#define COMP_HALMAC BIT_ULL(34)
#define COMP_PHYDM BIT_ULL(35)
/*--------------------------------------------------------------
* Define the rt_print components
*--------------------------------------------------------------
*/
/* Define EEPROM and EFUSE check module bit*/
#define EEPROM_W BIT(0)
#define EFUSE_PG BIT(1)
#define EFUSE_READ_ALL BIT(2)
/* Define init check for module bit*/
#define INIT_EEPROM BIT(0)
#define INIT_TXPOWER BIT(1)
#define INIT_IQK BIT(2)
#define INIT_RF BIT(3)
/* Define PHY-BB/RF/MAC check module bit */
#define PHY_BBR BIT(0)
#define PHY_BBW BIT(1)
#define PHY_RFR BIT(2)
#define PHY_RFW BIT(3)
#define PHY_MACR BIT(4)
#define PHY_MACW BIT(5)
#define PHY_ALLR BIT(6)
#define PHY_ALLW BIT(7)
#define PHY_TXPWR BIT(8)
#define PHY_PWRDIFF BIT(9)
/* Define Dynamic Mechanism check module bit --> FDM */
#define WA_IOT BIT(0)
#define DM_PWDB BIT(1)
#define DM_MONITOR BIT(2)
#define DM_DIG BIT(3)
#define DM_EDCA_TURBO BIT(4)
#define DM_PWDB BIT(1)
enum dbgp_flag_e {
FQOS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBGCTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
DBGP_TYPE_MAX
};
#ifdef CONFIG_RTLWIFI_DEBUG_ST
struct rtl_priv;
__printf(4, 5)
void _rtl_dbg_trace(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *fmt, ...);
__printf(4, 5)
void _rtl_dbg_print(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *fmt, ...);
void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level,
const char *titlestring,
const void *hexdata, int hexdatalen);
#define RT_TRACE(rtlpriv, comp, level, fmt, ...) \
_rtl_dbg_trace(rtlpriv, comp, level, \
fmt, ##__VA_ARGS__)
#define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
_rtl_dbg_print(rtlpriv, dbgtype, dbgflag, fmt, ##__VA_ARGS__)
#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
_hexdatalen) \
_rtl_dbg_print_data(rtlpriv, _comp, _level, \
_titlestring, _hexdata, _hexdatalen)
#else
struct rtl_priv;
__printf(4, 5)
static inline void RT_TRACE(struct rtl_priv *rtlpriv,
u64 comp, int level,
const char *fmt, ...)
{
}
__printf(4, 5)
static inline void RTPRINT(struct rtl_priv *rtlpriv,
int dbgtype, int dbgflag,
const char *fmt, ...)
{
}
static inline void RT_PRINT_DATA(struct rtl_priv *rtlpriv,
u64 comp, int level,
const char *titlestring,
const void *hexdata, size_t hexdatalen)
{
}
#endif
#ifdef CONFIG_RTLWIFI_DEBUG_ST
void rtl_debug_add_one(struct ieee80211_hw *hw);
void rtl_debug_remove_one(struct ieee80211_hw *hw);
void rtl_debugfs_add_topdir(void);
void rtl_debugfs_remove_topdir(void);
#else
#define rtl_debug_add_one(hw)
#define rtl_debug_remove_one(hw)
#define rtl_debugfs_add_topdir()
#define rtl_debugfs_remove_topdir()
#endif
#endif

1329
drivers/staging/rtlwifi/efuse.c
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File diff suppressed because it is too large Load Diff

109
drivers/staging/rtlwifi/efuse.h
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@ -1,109 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_EFUSE_H_
#define __RTL_EFUSE_H_
#define EFUSE_IC_ID_OFFSET 506
#define EFUSE_MAX_WORD_UNIT 4
#define EFUSE_INIT_MAP 0
#define EFUSE_MODIFY_MAP 1
#define PG_STATE_HEADER 0x01
#define PG_STATE_WORD_0 0x02
#define PG_STATE_WORD_1 0x04
#define PG_STATE_WORD_2 0x08
#define PG_STATE_WORD_3 0x10
#define PG_STATE_DATA 0x20
#define EFUSE_REPEAT_THRESHOLD_ 3
#define EFUSE_ERROE_HANDLE 1
struct efuse_map {
u8 offset;
u8 word_start;
u8 byte_start;
u8 byte_cnts;
};
struct pgpkt_struct {
u8 offset;
u8 word_en;
u8 data[8];
};
enum efuse_data_item {
EFUSE_CHIP_ID = 0,
EFUSE_LDO_SETTING,
EFUSE_CLK_SETTING,
EFUSE_SDIO_SETTING,
EFUSE_CCCR,
EFUSE_SDIO_MODE,
EFUSE_OCR,
EFUSE_F0CIS,
EFUSE_F1CIS,
EFUSE_MAC_ADDR,
EFUSE_EEPROM_VER,
EFUSE_CHAN_PLAN,
EFUSE_TXPW_TAB
};
enum {
VOLTAGE_V25 = 0x03,
LDOE25_SHIFT = 28,
};
struct efuse_priv {
u8 id[2];
u8 ldo_setting[2];
u8 clk_setting[2];
u8 cccr;
u8 sdio_mode;
u8 ocr[3];
u8 cis0[17];
u8 cis1[48];
u8 mac_addr[6];
u8 eeprom_verno;
u8 channel_plan;
u8 tx_power_b[14];
u8 tx_power_g[14];
};
void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
void efuse_initialize(struct ieee80211_hw *hw);
u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
void read_efuse(struct ieee80211_hw *hw, u16 _offset,
u16 _size_byte, u8 *pbuf);
void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 *value);
void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 value);
bool efuse_shadow_update(struct ieee80211_hw *hw);
bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
void efuse_force_write_vendor_id(struct ieee80211_hw *hw);
void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate);
int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv,
int max_size, u8 *hwinfo, int *params);
void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, const u8 *buffer,
u32 size);
void rtl_fw_block_write(struct ieee80211_hw *hw, const u8 *buffer, u32 size);
#endif

41
drivers/staging/rtlwifi/halmac/halmac_2_platform.h
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@ -1,41 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_2_PLATFORM_H_
#define _HALMAC_2_PLATFORM_H_
#include "../wifi.h"
#include <asm/byteorder.h>
#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
#define HALMAC_PLATFORM_BIG_ENDIAN 0
/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN
* is not mandatory. But Little endian must be '1'. Big endian must be '0'
*/
#if defined(__LITTLE_ENDIAN)
#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN
#elif defined(__BIG_ENDIAN)
#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN
#else
#error
#endif
/* define the Platform SDIO Bus CLK */
#define PLATFORM_SD_CLK 50000000 /*50MHz*/
/* define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
/* Should be 8 Byte alignment */
#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 16 /*Bytes*/
#endif /* _HALMAC_2_PLATFORM_H_ */

121
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
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@ -1,121 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_8822B_CFG_H_
#define _HALMAC_8822B_CFG_H_
#include "halmac_8822b_pwr_seq.h"
#include "halmac_api_8822b.h"
#include "halmac_api_8822b_usb.h"
#include "halmac_api_8822b_sdio.h"
#include "halmac_api_8822b_pcie.h"
#include "../../halmac_bit2.h"
#include "../../halmac_reg2.h"
#include "../../halmac_api.h"
#define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */
#define HALMAC_TX_FIFO_SIZE_LA_8822B 131072 /* 128k */
#define HALMAC_RX_FIFO_SIZE_8822B 24576 /* 24k */
#define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */
#define HALMAC_TX_ALIGN_SIZE_8822B 8
#define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */
#define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry size */
#define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8
#define HALMAC_TX_DESC_SIZE_8822B 48
#define HALMAC_RX_DESC_SIZE_8822B 24
#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B 120
#define HALMAC_C2H_PKT_BUF_8822B 256
#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* align 8 Byte*/
#define HALMAC_RX_FIFO_EXPANDING_UNIT_8822B \
(HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* align 8 Byte*/
#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B \
(HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) /* align 8 Byte*/
#define HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B 196608 /* 192k */
#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B \
((((HALMAC_RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) \
<< 10) /* < 56k*/
#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B \
((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B << 8) - 1) >> 10) \
<< 10) /* 55k*/
#define HALMAC_TX_FIFO_SIZE_EX_2_BLK_8822B 131072 /* 128k */
#define HALMAC_RX_FIFO_SIZE_EX_2_BLK_8822B 155648 /* 152k */
#define HALMAC_TX_FIFO_SIZE_EX_3_BLK_8822B 65536 /* 64k */
#define HALMAC_RX_FIFO_SIZE_EX_3_BLK_8822B 221184 /* 216k */
/* TXFIFO LAYOUT
* HIGH_QUEUE
* NORMAL_QUEUE
* LOW_QUEUE
* EXTRA_QUEUE
* PUBLIC_QUEUE -- decided after all other queue are defined
* GAP_QUEUE -- Used to separate AC queue and Rsvd page
*
* RSVD_DRIVER -- Driver used rsvd page area
* RSVD_H2C_EXTRAINFO -- Extra Information for h2c
* RSVD_H2C_QUEUE -- h2c queue in rsvd page
* RSVD_CPU_INSTRUCTION -- extend fw code
* RSVD_FW_TXBUFF -- fw used this area to send packet
*
* Symbol: HALMAC_MODE_QUEUE_UNIT_CHIP, ex: HALMAC_LB_2BULKOUT_FWCMD_PGNUM_8822B
*/
#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_8822B \
16384 /*16K, only used in init case*/
#define HALMAC_RSVD_DRV_PGNUM_8822B 16 /*2048*/
#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B 32 /*4096*/
#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B 8 /*1024*/
#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/
#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/
#define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */
#define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */
#define HALMAC_EEPROM_SIZE_8822B 0x300
#define HALMAC_CR_TRX_ENABLE_8822B \
(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | BIT_RXDMA_EN | \
BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | BIT_MACTXEN | BIT_MACRXEN)
#define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */
/* AMPDU max time (unit : 32us) */
#define HALMAC_AMPDU_MAX_TIME_8822B 0x70
/* Protect mode control */
#define HALMAC_PROT_RTS_LEN_TH_8822B 0xFF
#define HALMAC_PROT_RTS_TX_TIME_TH_8822B 0x08
#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B 0x20
#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B 0x20
/* Fast EDCA setting */
#define HALMAC_FAST_EDCA_VO_TH_8822B 0x06
#define HALMAC_FAST_EDCA_VI_TH_8822B 0x06
#define HALMAC_FAST_EDCA_BE_TH_8822B 0x06
#define HALMAC_FAST_EDCA_BK_TH_8822B 0x06
/* BAR setting */
#define HALMAC_BAR_RETRY_LIMIT_8822B 0x01
#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B 0x08
enum halmac_normal_rxagg_th_to_8822b {
HALMAC_NORMAL_RXAGG_THRESHOLD_8822B = 0xFF,
HALMAC_NORMAL_RXAGG_TIMEOUT_8822B = 0x01,
};
enum halmac_loopback_rxagg_th_to_8822b {
HALMAC_LOOPBACK_RXAGG_THRESHOLD_8822B = 0xFF,
HALMAC_LOOPBACK_RXAGG_TIMEOUT_8822B = 0x01,
};
#endif

95
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c
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// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
/**
* ============ip sel item list============
* HALMAC_IP_SEL_INTF_PHY
* USB2 : usb2 phy, 1byte value
* USB3 : usb3 phy, 2byte value
* PCIE1 : pcie gen1 mdio, 2byte value
* PCIE2 : pcie gen2 mdio, 2byte value
* HALMAC_IP_SEL_MAC
* USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
* HALMAC_IP_SEL_PCIE_DBI
* USB2 USB3 : none
* PCIE1, PCIE2 : pcie dbi, 1byte value
*/
struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};

552
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c
View File

@ -1,552 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/
{0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/
{0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1,
HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/
{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
(BIT(4) | BIT(3) | BIT(2)),
0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/
{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* Disable USB suspend */
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /* wait till 0x04[17] = 1 power ready*/
{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /* Enable USB suspend */
{0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0xFF1A = 0 to release resume signals*/
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
(BIT(4) | BIT(3)), 0}, /* disable WL suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* polling until return 0*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(0), 0},
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Enable XTAL_CLK*/
{0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*NFC pad enabled*/
{0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xef}, /*NFC pad enabled*/
{0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x0c}, /*NFC pad enabled*/
{0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/
{0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xF9}, /*PLL seting*/
{0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), 0}, /*Improve TX EVM of CH13 and some 5G channles */
{0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/
{0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/
{0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/
{0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/
{0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Enable rising edge triggering interrupt*/
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /* Whole BB is reset */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(1),
0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), 0}, /* XTAL_CLK gated*/
{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4) | BIT(3),
(BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4),
BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /*wait power state to suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(7),
BIT(7)}, /*suspend enable and power down enable*/
{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF,
0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/
{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(5),
0}, /* 0: BT PAPE control ; 1: WL BB LNAON control*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4),
0}, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/
{0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0: BT Control*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(1),
0}, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */
{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)}, /* GPIO[6] : Output mode*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /* turn off BT_GPIO[16] */
{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* GPIO[7] : Output mode*/
{0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* GPIO[12] : Output mode */
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1),
0}, /*0x90[1]=0 , disable 32k clock*/
{0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), 0}, /*0x80[15]clean fw init ready bit*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /*wait power state to suspend*/
{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4) | BIT(7),
0}, /*clear suspend enable and power down enable*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0},
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable 32K CLK*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x42}, /* LPS Option MAC OFF enable*/
{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*PCIe DMA stop*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*Tx Pause*/
{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Whole BB is reset*/
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x3F}, /*Reset MAC TRX*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*check if removed later*/
{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7),
BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable 32K CLK*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x40}, /* LPS Option MAC OFF enable*/
{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*PCIe DMA stop*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*Tx Pause*/
{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Whole BB is reset*/
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x3F}, /*Reset MAC TRX*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*check if removed later*/
{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7),
BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/
{0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x84}, /*USB RPWM*/
{0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x84}, /*PCIe RPWM*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), 0}, /* switch TSF to 40M*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)},
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*nable WMAC TRX*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0},
{0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x03}, /*clear RPWM INT*/
{0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /* disable reg use 32K CLK*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), 0}, /*disable 32k calibration and thermal meter*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
/* Card Enable Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[] = {
HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
/* Card Disable Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, NULL};
/* Suspend Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, NULL};
/* Resume Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[] = {
HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
/* HWPDN Array - HW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[] = {NULL};
/* Enter LPS - FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_LPS, NULL};
/* Enter Deep LPS - FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, NULL};
/* Leave LPS -FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[] = {
HALMAC_RTL8822B_TRANS_LPS_TO_ACT, NULL};

29
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h
View File

@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_POWER_SEQUENCE_8822B
#define HALMAC_POWER_SEQUENCE_8822B
#include "../../halmac_pwr_seq_cmd.h"
#define HALMAC_8822B_PWR_SEQ_VER "V17"
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[];
#endif

332
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c
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@ -1,332 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
#include "halmac_func_8822b.h"
#include "../halmac_func_88xx.h"
/**
* halmac_mount_api_8822b() - attach functions to function pointer
* @halmac_adapter
*
* SD1 internal use
*
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
*/
enum halmac_ret_status
halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter)
{
struct halmac_api *halmac_api =
(struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
halmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8822B;
halmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8822B;
halmac_adapter->hw_config_info.bt_efuse_size =
HALMAC_BT_EFUSE_SIZE_8822B;
halmac_adapter->hw_config_info.cam_entry_num =
HALMAC_SECURITY_CAM_ENTRY_NUM_8822B;
halmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8822B;
halmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B;
halmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B;
halmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B;
halmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8822B;
halmac_adapter->hw_config_info.tx_align_size =
HALMAC_TX_ALIGN_SIZE_8822B;
halmac_adapter->hw_config_info.page_size_2_power =
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_adapter->txff_allocation.rsvd_drv_pg_num =
HALMAC_RSVD_DRV_PGNUM_8822B;
halmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b;
halmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8822b;
halmac_api->halmac_init_h2c = halmac_init_h2c_8822b;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
halmac_api->halmac_tx_allowed_sdio =
halmac_tx_allowed_sdio_88xx;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_sdio_not_support_88xx;
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_sdio;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_sdio;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_sdio;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_usb;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_usb_not_support_88xx;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_usb;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_usb;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_pcie;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_pcie_not_support_88xx;
halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_pcie;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_pcie;
} else {
halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b_nc;
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_trx_cfg_8822b() - config trx dma register
* @halmac_adapter : the adapter of halmac
* @halmac_trx_mode : trx mode selection
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u8 value8;
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_TRX_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->trx_mode = halmac_trx_mode;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n",
halmac_trx_mode);
status = halmac_txdma_queue_mapping_8822b(halmac_adapter,
halmac_trx_mode);
if (status != HALMAC_RET_SUCCESS) {
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_txdma_queue_mapping fail!\n");
return status;
}
value8 = 0;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value8 = HALMAC_CR_TRX_ENABLE_8822B;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2CQ_CSR, BIT(31));
status = halmac_priority_queue_config_8822b(halmac_adapter,
halmac_trx_mode);
if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode !=
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
HALMAC_REG_WRITE_8(halmac_adapter, REG_RX_DRVINFO_SZ, 0xF);
if (status != HALMAC_RET_SUCCESS) {
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_txdma_queue_mapping fail!\n");
return status;
}
/* Config H2C packet buffer */
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
value32 = (value32 & 0xFFFC0000) |
((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
(HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFC) | 0x01);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFB) | 0x04);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
value8 = (u8)((value8 & 0x7f) | 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
if (halmac_adapter->h2c_buff_size !=
halmac_adapter->h2c_buf_free_space) {
pr_err("get h2c free space error!\n");
return HALMAC_RET_GET_H2C_SPACE_ERR;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_trx_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_protocol_cfg_8822b() - config protocol register
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter)
{
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PROTOCOL_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]%s ==========>\n", __func__);
HALMAC_REG_WRITE_8(halmac_adapter, REG_AMPDU_MAX_TIME_V1,
HALMAC_AMPDU_MAX_TIME_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
value32 = HALMAC_PROT_RTS_LEN_TH_8822B |
(HALMAC_PROT_RTS_TX_TIME_TH_8822B << 8) |
(HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B << 16) |
(HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B << 24);
HALMAC_REG_WRITE_32(halmac_adapter, REG_PROT_MODE_CTRL, value32);
HALMAC_REG_WRITE_16(halmac_adapter, REG_BAR_MODE_CTRL + 2,
HALMAC_BAR_RETRY_LIMIT_8822B |
HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B << 8);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING,
HALMAC_FAST_EDCA_VO_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2,
HALMAC_FAST_EDCA_VI_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING,
HALMAC_FAST_EDCA_BE_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2,
HALMAC_FAST_EDCA_BK_TH_8822B);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_h2c_8822b() - config h2c packet buffer
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter)
{
u8 value8;
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value8 = 0;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value8 = HALMAC_CR_TRX_ENABLE_8822B;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
value32 = (value32 & 0xFFFC0000) |
((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
(HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFC) | 0x01);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFB) | 0x04);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
value8 = (u8)((value8 & 0x7f) | 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
if (halmac_adapter->h2c_buff_size !=
halmac_adapter->h2c_buf_free_space) {
pr_err("get h2c free space error!\n");
return HALMAC_RET_GET_H2C_SPACE_ERR;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"h2c free space : %d\n",
halmac_adapter->h2c_buf_free_space);
return HALMAC_RET_SUCCESS;
}

33
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h
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@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_H_
#define _HALMAC_API_8822B_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
enum halmac_ret_status
halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_H_ */

312
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c
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@ -1,312 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "../halmac_api_88xx_pcie.h"
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_pcie() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n",
halmac_power);
interface_mask = HALMAC_PWR_INTF_PCI_MSK;
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA)
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
/* Check if power switch is needed */
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power off cmd error\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power on cmd error\n");
return HALMAC_RET_POWER_ON_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_pcie <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
* @halmac_adapter : the adapter of halmac
* @pcie_cfg : gen1/gen2 selection
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
u8 current_link_speed = 0;
u32 count = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s ==========>\n", __func__);
/* Link Control 2 Register[3:0] Target Link Speed
* Defined encodings are:
* 0001b Target Link 2.5 GT/s
* 0010b Target Link 5.0 GT/s
* 0100b Target Link 8.0 GT/s
*/
if (pcie_cfg == HALMAC_PCIE_GEN1) {
/* cfg 0xA0[3:0]=4'b0001 */
halmac_dbi_write8_88xx(
halmac_adapter, LINK_CTRL2_REG_OFFSET,
(halmac_dbi_read8_88xx(halmac_adapter,
LINK_CTRL2_REG_OFFSET) &
0xF0) | BIT(0));
/* cfg 0x80C[17]=1 //PCIe DesignWave */
halmac_dbi_write32_88xx(
halmac_adapter, GEN2_CTRL_OFFSET,
halmac_dbi_read32_88xx(halmac_adapter,
GEN2_CTRL_OFFSET) |
BIT(17));
/* check link speed if GEN1 */
/* cfg 0x82[3:0]=4'b0001 */
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count = 2000;
while (current_link_speed != GEN1_SPEED && count != 0) {
usleep_range(50, 60);
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count--;
}
if (current_link_speed != GEN1_SPEED) {
pr_err("Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else if (pcie_cfg == HALMAC_PCIE_GEN2) {
/* cfg 0xA0[3:0]=4'b0010 */
halmac_dbi_write8_88xx(
halmac_adapter, LINK_CTRL2_REG_OFFSET,
(halmac_dbi_read8_88xx(halmac_adapter,
LINK_CTRL2_REG_OFFSET) &
0xF0) | BIT(1));
/* cfg 0x80C[17]=1 //PCIe DesignWave */
halmac_dbi_write32_88xx(
halmac_adapter, GEN2_CTRL_OFFSET,
halmac_dbi_read32_88xx(halmac_adapter,
GEN2_CTRL_OFFSET) |
BIT(17));
/* check link speed if GEN2 */
/* cfg 0x82[3:0]=4'b0010 */
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count = 2000;
while (current_link_speed != GEN2_SPEED && count != 0) {
usleep_range(50, 60);
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count--;
}
if (current_link_speed != GEN2_SPEED) {
pr_err("Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else {
pr_err("Error Speed !\n");
return HALMAC_RET_FAIL;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_pcie() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_PCIE_PHY_GEN1,
platform, HAL_INTF_PHY_PCIE_GEN1);
if (status != HALMAC_RET_SUCCESS)
return status;
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_PCIE_PHY_GEN2,
platform, HAL_INTF_PHY_PCIE_GEN2);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_pcie() - pcie interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Rick Liu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}

42
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h
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@ -1,42 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_PCIE_H_
#define _HALMAC_API_8822B_PCIE_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[];
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[];
enum halmac_ret_status
halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg);
enum halmac_ret_status
halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg);
enum halmac_ret_status
halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_PCIE_H_ */

173
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c
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@ -1,173 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_sdio() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
u8 rpwm;
u32 imr_backup;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_mac_power_switch_88xx_sdio==========>\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_power = %x ==========>\n", halmac_power);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]8822B pwr seq ver = %s\n",
HALMAC_8822B_PWR_SEQ_VER);
interface_mask = HALMAC_PWR_INTF_SDIO_MSK;
halmac_adapter->rpwm_record =
HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HRPWM1);
/* Check FW still exist or not */
if (HALMAC_REG_READ_16(halmac_adapter, REG_MCUFW_CTRL) == 0xC078) {
/* Leave 32K */
rpwm = (u8)((halmac_adapter->rpwm_record ^ BIT(7)) & 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_SDIO_HRPWM1, rpwm);
}
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA)
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
/*Check if power switch is needed*/
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"[WARN]halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
imr_backup = HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_HIMR);
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, 0);
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("[ERR]Handle power off cmd error\n");
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
imr_backup);
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("[ERR]Handle power on cmd error\n");
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
imr_backup);
return HALMAC_RET_POWER_ON_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, imr_backup);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_sdio() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"sdio no phy\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_sdio() - sdio interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Ivan
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}

31
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h
View File

@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_SDIO_H_
#define _HALMAC_API_8822B_SDIO_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_SDIO_H_ */

174
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c
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@ -1,174 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_usb() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n",
halmac_power);
interface_mask = HALMAC_PWR_INTF_USB_MSK;
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA) {
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
} else {
if (BIT(0) ==
(HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
BIT(0)))
halmac_adapter->halmac_state.mac_power =
HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power =
HALMAC_MAC_POWER_ON;
}
/*Check if power switch is needed*/
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power off cmd error\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power on cmd error\n");
return HALMAC_RET_POWER_ON_FAIL;
}
HALMAC_REG_WRITE_8(
halmac_adapter, REG_SYS_STATUS1 + 1,
HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
~(BIT(0)));
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_usb <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_usb() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_USB2_PHY, platform,
HAL_INTF_PHY_USB2);
if (status != HALMAC_RET_SUCCESS)
return status;
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_USB3_PHY, platform,
HAL_INTF_PHY_USB3);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_usb() - usb interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Ivan
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}

34
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h
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@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_USB_H_
#define _HALMAC_API_8822B_USB_H_
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[];
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[];
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_USB_H_ */

403
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c
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@ -1,403 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
#include "halmac_func_8822b.h"
/*SDIO RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_SDIO_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*PCIE RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_PCIE_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*USB 2 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_2BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
};
/*USB 3 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_3BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
};
/*USB 4 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_4BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*SDIO Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_SDIO_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
/*PCIE Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_PCIE_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
/*USB 2 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_2BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
};
/*USB 3 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_3BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
};
/*USB 4 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_4BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
enum halmac_ret_status
halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u16 value16;
void *driver_adapter = NULL;
struct halmac_rqpn_ *curr_rqpn_sel = NULL;
enum halmac_ret_status status;
struct halmac_api *halmac_api;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
curr_rqpn_sel = HALMAC_RQPN_SDIO_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
curr_rqpn_sel = HALMAC_RQPN_PCIE_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
if (halmac_adapter->halmac_bulkout_num == 2) {
curr_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 3) {
curr_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 4) {
curr_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B;
} else {
pr_err("[ERR]interface not support\n");
return HALMAC_RET_NOT_SUPPORT;
}
} else {
return HALMAC_RET_NOT_SUPPORT;
}
status = halmac_rqpn_parser_88xx(halmac_adapter, halmac_trx_mode,
curr_rqpn_sel);
if (status != HALMAC_RET_SUCCESS)
return status;
value16 = 0;
value16 |= BIT_TXDMA_HIQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]);
value16 |= BIT_TXDMA_MGQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]);
value16 |= BIT_TXDMA_BKQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]);
value16 |= BIT_TXDMA_BEQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]);
value16 |= BIT_TXDMA_VIQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]);
value16 |= BIT_TXDMA_VOQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]);
HALMAC_REG_WRITE_16(halmac_adapter, REG_TXDMA_PQ_MAP, value16);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u8 transfer_mode = 0;
u8 value8;
u32 counter;
enum halmac_ret_status status;
struct halmac_pg_num_ *curr_pg_num = NULL;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if (halmac_adapter->txff_allocation.la_mode == HALMAC_LA_MODE_DISABLE) {
if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode ==
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
} else if (halmac_adapter->txff_allocation
.rx_fifo_expanding_mode ==
HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_adapter->hw_config_info.tx_fifo_size =
HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B;
if (HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B <=
HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B)
halmac_adapter->hw_config_info.rx_fifo_size =
HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B;
else
halmac_adapter->hw_config_info.rx_fifo_size =
HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B;
} else {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
pr_err("[ERR]rx_fifo_expanding_mode = %d not support\n",
halmac_adapter->txff_allocation
.rx_fifo_expanding_mode);
}
} else {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_LA_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
}
halmac_adapter->txff_allocation.rsvd_pg_num =
(halmac_adapter->txff_allocation.rsvd_drv_pg_num +
HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B +
HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B +
HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B +
HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B);
if (halmac_adapter->txff_allocation.rsvd_pg_num >
halmac_adapter->txff_allocation.tx_fifo_pg_num)
return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
halmac_adapter->txff_allocation.ac_q_pg_num =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
halmac_adapter->txff_allocation.rsvd_pg_num;
halmac_adapter->txff_allocation.rsvd_pg_bndy =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
halmac_adapter->txff_allocation.rsvd_pg_num;
halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy =
halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy -
HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy =
halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy -
HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy =
halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy -
HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_drv_pg_bndy =
halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy -
halmac_adapter->txff_allocation.rsvd_drv_pg_num;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
curr_pg_num = HALMAC_PG_NUM_SDIO_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
curr_pg_num = HALMAC_PG_NUM_PCIE_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
if (halmac_adapter->halmac_bulkout_num == 2) {
curr_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 3) {
curr_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 4) {
curr_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B;
} else {
pr_err("[ERR]interface not support\n");
return HALMAC_RET_NOT_SUPPORT;
}
} else {
return HALMAC_RET_NOT_SUPPORT;
}
status = halmac_pg_num_parser_88xx(halmac_adapter, halmac_trx_mode,
curr_pg_num);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_1,
halmac_adapter->txff_allocation.high_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_2,
halmac_adapter->txff_allocation.low_queue_pg_num);
HALMAC_REG_WRITE_16(
halmac_adapter, REG_FIFOPAGE_INFO_3,
halmac_adapter->txff_allocation.normal_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_4,
halmac_adapter->txff_allocation.extra_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_5,
halmac_adapter->txff_allocation.pub_queue_pg_num);
halmac_adapter->sdio_free_space.high_queue_number =
halmac_adapter->txff_allocation.high_queue_pg_num;
halmac_adapter->sdio_free_space.normal_queue_number =
halmac_adapter->txff_allocation.normal_queue_pg_num;
halmac_adapter->sdio_free_space.low_queue_number =
halmac_adapter->txff_allocation.low_queue_pg_num;
halmac_adapter->sdio_free_space.public_queue_number =
halmac_adapter->txff_allocation.pub_queue_pg_num;
halmac_adapter->sdio_free_space.extra_queue_number =
halmac_adapter->txff_allocation.extra_queue_pg_num;
HALMAC_REG_WRITE_32(
halmac_adapter, REG_RQPN_CTRL_2,
HALMAC_REG_READ_32(halmac_adapter, REG_RQPN_CTRL_2) | BIT(31));
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCN_HEAD_1_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ_BDNY_V1,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCNQ_PGBNDY_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 2,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCN_HEAD_1_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ1_BDNY_V1,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCNQ_PGBNDY_V1));
HALMAC_REG_WRITE_32(halmac_adapter, REG_RXFF_BNDY,
halmac_adapter->hw_config_info.rx_fifo_size -
HALMAC_C2H_PKT_BUF_8822B - 1);
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
value8 = (u8)(
HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM));
value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B
<< BIT_SHIFT_BLK_DESC_NUM));
HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1, value8);
HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1 + 3,
HALMAC_BLK_DESC_NUM_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1,
HALMAC_REG_READ_8(halmac_adapter,
REG_TXDMA_OFFSET_CHK + 1) |
BIT(1));
}
HALMAC_REG_WRITE_8(
halmac_adapter, REG_AUTO_LLT_V1,
(u8)(HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) |
BIT_AUTO_INIT_LLT_V1));
counter = 1000;
while (HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
BIT_AUTO_INIT_LLT_V1) {
counter--;
if (counter == 0)
return HALMAC_RET_INIT_LLT_FAIL;
}
if (halmac_trx_mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
HALMAC_REG_WRITE_16(
halmac_adapter, REG_WMAC_LBK_BUF_HD_V1,
(u16)halmac_adapter->txff_allocation.rsvd_pg_bndy);
} else if (halmac_trx_mode == HALMAC_TRX_MODE_LOOPBACK) {
transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
} else {
transfer_mode = HALMAC_TRNSFER_NORMAL;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 3, (u8)transfer_mode);
return HALMAC_RET_SUCCESS;
}

27
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h
View File

@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FUNC_8822B_H_
#define _HALMAC_FUNC_8822B_H_
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
enum halmac_ret_status
halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
#endif /* _HALMAC_FUNC_8822B_H_ */

160
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_88xx_cfg.h
View File

@ -1,160 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_88XX_CFG_H_
#define _HALMAC_88XX_CFG_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
#include "../halmac_api.h"
#include "../halmac_bit2.h"
#include "../halmac_reg2.h"
#include "../halmac_pwr_seq_cmd.h"
#include "halmac_func_88xx.h"
#include "halmac_api_88xx.h"
#include "halmac_api_88xx_usb.h"
#include "halmac_api_88xx_pcie.h"
#include "halmac_api_88xx_sdio.h"
#define HALMAC_SVN_VER_88XX "13359M"
#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */
/* For halmac_api num change or prototype change, increment prototype version.
* Otherwise, increase minor version
*/
#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* prototype version */
#define HALMAC_MINOR_VER_88XX 0x0005 /* minor version */
#define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */
#define HALMAC_C2H_DATA_OFFSET_88XX 10
#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8
#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8
#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768
#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/
#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/
#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX \
12 /*Fw config parameter cmd size, each 12 byte*/
#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8
#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */
#define HALMAC_NLO_INFO_SIZE_88XX 1024
/* Download FW */
#define HALMAC_FW_SIZE_MAX_88XX 0x40000
#define HALMAC_FWHDR_SIZE_88XX 64
#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8
#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */
/* Max dlfw size can not over 31K, because SDIO HW restriction */
#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00
#define DLFW_RESTORE_REG_NUM_88XX 9
#define ID_INFORM_DLEMEM_RDY 0x80
/* FW header information */
#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4
#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6
#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7
#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24
#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28
#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32
#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36
#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48
#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52
#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56
#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60
/* HW memory address */
#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000
#define HALMAC_OCPBASE_DMEM_88XX 0x00200000
#define HALMAC_OCPBASE_IMEM_88XX 0x00000000
/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that
* result from SDIO CLK sync to ana_clk fail
*/
#define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */
/* MAC clock */
#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */
/* H2C/C2H*/
#define HALMAC_H2C_CMD_SIZE_88XX 32
#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8
#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60
/* Function enable */
#define HALMAC_FUNCTION_ENABLE_88XX 0xDC
/* FIFO size & packet size */
/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */
/* CFEND rate */
#define HALMAC_BASIC_CFEND_RATE_88XX 0x5
#define HALMAC_STBC_CFEND_RATE_88XX 0xF
/* Response rate */
#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF
#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX
/* Spec SIFS */
#define HALMAC_SIFS_CCK_PTCL_88XX 16
#define HALMAC_SIFS_OFDM_PTCL_88XX 16
/* Retry limit */
#define HALMAC_LONG_RETRY_LIMIT_88XX 8
#define HALMAC_SHORT_RETRY_LIMIT_88XX 7
/* Slot, SIFS, PIFS time */
#define HALMAC_SLOT_TIME_88XX 0x05
#define HALMAC_PIFS_TIME_88XX 0x19
#define HALMAC_SIFS_CCK_CTX_88XX 0xA
#define HALMAC_SIFS_OFDM_CTX_88XX 0xA
#define HALMAC_SIFS_CCK_TRX_88XX 0x10
#define HALMAC_SIFS_OFDM_TRX_88XX 0x10
/* TXOP limit */
#define HALMAC_VO_TXOP_LIMIT_88XX 0x186
#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC
/* NAV */
#define HALMAC_RDG_NAV_88XX 0x05
#define HALMAC_TXOP_NAV_88XX 0x1B
/* TSF */
#define HALMAC_CCK_RX_TSF_88XX 0x30
#define HALMAC_OFDM_RX_TSF_88XX 0x30
/* Send beacon related */
#define HALMAC_TBTT_PROHIBIT_88XX 0x04
#define HALMAC_TBTT_HOLD_TIME_88XX 0x064
#define HALMAC_DRIVER_EARLY_INT_88XX 0x04
#define HALMAC_BEACON_DMA_TIM_88XX 0x02
/* RX filter */
#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF
#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX
#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF
#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX
/* RCR */
#define HALMAC_RCR_CONFIG_88XX 0xE400631E
/* Security config */
#define HALMAC_SECURITY_CONFIG_88XX 0x01CC
/* CCK rate ACK timeout */
#define HALMAC_ACK_TO_CCK_88XX 0x40
#endif

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drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.c
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drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_H_
#define _HALMAC_API_88XX_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
void halmac_init_state_machine_88xx(struct halmac_adapter *halmac_adapter);
void halmac_init_adapter_para_88xx(struct halmac_adapter *halmac_adapter);
void halmac_init_adapter_dynamic_para_88xx(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_mount_api_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
u8 *hamacl_fw, u32 halmac_fw_size);
enum halmac_ret_status
halmac_free_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
u32 halmac_fw_size);
enum halmac_ret_status
halmac_get_fw_version_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fw_version *fw_version);
enum halmac_ret_status
halmac_cfg_mac_addr_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_cfg_bssid_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_cfg_multicast_addr_88xx(struct halmac_adapter *halmac_adapter,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_pre_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg halmac_rxagg_cfg);
enum halmac_ret_status
halmac_init_edca_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_operation_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_wireless_mode wireless_mode);
enum halmac_ret_status
halmac_cfg_ch_bw_88xx(struct halmac_adapter *halmac_adapter, u8 channel,
enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
enum halmac_ret_status halmac_cfg_ch_88xx(struct halmac_adapter *halmac_adapter,
u8 channel);
enum halmac_ret_status
halmac_cfg_pri_ch_idx_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_pri_ch_idx pri_ch_idx);
enum halmac_ret_status halmac_cfg_bw_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_bw bw);
enum halmac_ret_status
halmac_init_wmac_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_mac_cfg_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode mode);
enum halmac_ret_status
halmac_dump_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_dump_efuse_map_bt_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank halmac_efuse_bank,
u32 bt_efuse_map_size, u8 *bt_efuse_map);
enum halmac_ret_status
halmac_write_efuse_bt_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_value,
enum halmac_efuse_bank halmac_efuse_bank);
enum halmac_ret_status
halmac_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_pg_efuse_info *pg_efuse_info,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_get_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_get_efuse_available_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_get_c2h_info_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status
halmac_get_logical_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_dump_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_value);
enum halmac_ret_status
halmac_read_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 *value);
enum halmac_ret_status
halmac_cfg_fwlps_option_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwlps_option *lps_option);
enum halmac_ret_status
halmac_cfg_fwips_option_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwips_option *ips_option);
enum halmac_ret_status
halmac_enter_wowlan_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_wowlan_option *wowlan_option);
enum halmac_ret_status
halmac_leave_wowlan_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_enter_ps_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_ps_state ps_state);
enum halmac_ret_status
halmac_leave_ps_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_h2c_lb_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_debug_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_parameter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_phy_parameter_info *para_info,
u8 full_fifo);
enum halmac_ret_status
halmac_update_packet_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
enum halmac_ret_status
halmac_bcn_ie_filter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_bcn_ie_info *bcn_ie_info);
enum halmac_ret_status
halmac_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
u8 *original_h2c, u16 *seq, u8 ack);
enum halmac_ret_status
halmac_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type,
struct halmac_phy_parameter_info *para_info);
enum halmac_ret_status
halmac_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type);
enum halmac_ret_status
halmac_cfg_drv_info_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_drv_info halmac_drv_info);
enum halmac_ret_status
halmac_send_bt_coex_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
u32 bt_size, u8 ack);
enum halmac_ret_status
halmac_verify_platform_api_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_timer_2s_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_fill_txdesc_check_sum_88xx(struct halmac_adapter *halmac_adapter,
u8 *cur_desc);
enum halmac_ret_status
halmac_dump_fifo_88xx(struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
u32 halmac_fifo_dump_size, u8 *fifo_map);
u32 halmac_get_fifo_size_88xx(struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel);
enum halmac_ret_status
halmac_cfg_txbf_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
enum halmac_bw bw, u8 txbf_en);
enum halmac_ret_status
halmac_cfg_mumimo_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_cfg_mumimo_para *cfgmu);
enum halmac_ret_status
halmac_cfg_sounding_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role,
enum halmac_data_rate datarate);
enum halmac_ret_status
halmac_del_sounding_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role);
enum halmac_ret_status
halmac_su_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
u16 paid);
enum halmac_ret_status
halmac_su_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_su_bfer_init_para *su_bfer_init);
enum halmac_ret_status
halmac_mu_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfee_init_para *mu_bfee_init);
enum halmac_ret_status
halmac_mu_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfer_init_para *mu_bfer_init);
enum halmac_ret_status
halmac_su_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_su_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_mu_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_mu_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_add_ch_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_info *ch_info);
enum halmac_ret_status
halmac_add_extra_ch_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_extra_info *ch_extra_info);
enum halmac_ret_status
halmac_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_switch_option *cs_option);
enum halmac_ret_status halmac_p2pps_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_p2pps *p2p_ps);
enum halmac_ret_status
halmac_func_p2pps_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_p2pps *p2p_ps);
enum halmac_ret_status
halmac_clear_ch_info_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_general_info *general_info);
enum halmac_ret_status
halmac_start_iqk_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_iqk_para_ *iqk_para);
enum halmac_ret_status halmac_ctrl_pwr_tracking_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_pwr_tracking_option *pwr_tracking_opt);
enum halmac_ret_status
halmac_query_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status
halmac_reset_feature_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id);
enum halmac_ret_status
halmac_check_fw_status_88xx(struct halmac_adapter *halmac_adapter,
bool *fw_status);
enum halmac_ret_status
halmac_dump_fw_dmem_88xx(struct halmac_adapter *halmac_adapter, u8 *dmem,
u32 *size);
enum halmac_ret_status
halmac_cfg_max_dl_size_88xx(struct halmac_adapter *halmac_adapter, u32 size);
enum halmac_ret_status halmac_psd_88xx(struct halmac_adapter *halmac_adapter,
u16 start_psd, u16 end_psd);
enum halmac_ret_status
halmac_cfg_la_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_la_mode la_mode);
enum halmac_ret_status halmac_cfg_rx_fifo_expanding_mode_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
enum halmac_ret_status
halmac_config_security_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_security_setting *sec_setting);
u8 halmac_get_used_cam_entry_num_88xx(struct halmac_adapter *halmac_adapter,
enum hal_security_type sec_type);
enum halmac_ret_status
halmac_write_cam_88xx(struct halmac_adapter *halmac_adapter, u32 entry_index,
struct halmac_cam_entry_info *cam_entry_info);
enum halmac_ret_status
halmac_read_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
u32 entry_index,
struct halmac_cam_entry_format *content);
enum halmac_ret_status
halmac_clear_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
u32 entry_index);
enum halmac_ret_status
halmac_get_hw_value_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_hw_id hw_id, void *pvalue);
enum halmac_ret_status
halmac_set_hw_value_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_hw_id hw_id, void *pvalue);
enum halmac_ret_status
halmac_cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_drv_rsvd_pg_num pg_num);
enum halmac_ret_status
halmac_get_chip_version_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ver *version);
enum halmac_ret_status
halmac_chk_txdesc_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status
halmac_dl_drv_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
u8 pg_offset, u8 *halmac_buf, u32 halmac_size);
enum halmac_ret_status
halmac_cfg_csi_rate_88xx(struct halmac_adapter *halmac_adapter, u8 rssi,
u8 current_rate, u8 fixrate_en, u8 *new_rate);
enum halmac_ret_status halmac_sdio_cmd53_4byte_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
enum halmac_ret_status
halmac_txfifo_is_empty_88xx(struct halmac_adapter *halmac_adapter, u32 chk_num);
#endif /* _HALMAC_API_H_ */

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drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_pcie.c
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@ -1,318 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_pcie_cfg_88xx() - init PCIe
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PCIE_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_pcie_cfg_88xx() - deinit PCIE
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_PCIE_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_pcie_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_8_pcie_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_pcie_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_16_pcie_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_pcie_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_32_pcie_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}

60
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_pcie.h
View File

@ -1,60 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_PCIE_H_
#define _HALMAC_API_88XX_PCIE_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
#define LINK_CTRL2_REG_OFFSET 0xA0
#define GEN2_CTRL_OFFSET 0x80C
#define LINK_STATUS_REG_OFFSET 0x82
#define GEN1_SPEED 0x01
#define GEN2_SPEED 0x02
enum halmac_ret_status
halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
#endif /* _HALMAC_API_88XX_PCIE_H_ */

960
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_sdio.c
View File

@ -1,960 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_sdio_cfg_88xx() - init SDIO
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_SDIO_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_FREE_TXPG);
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_sdio_cfg_88xx() - deinit SDIO
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_SDIO_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
u8 value8;
u8 size = 0, timeout = 0, agg_enable = 0;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
switch (phalmac_rxagg_cfg->mode) {
case HALMAC_RX_AGG_MODE_NONE:
agg_enable &= ~(BIT_RXDMA_AGG_EN);
break;
case HALMAC_RX_AGG_MODE_DMA:
case HALMAC_RX_AGG_MODE_USB:
agg_enable |= BIT_RXDMA_AGG_EN;
break;
default:
pr_err("halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
}
if (!phalmac_rxagg_cfg->threshold.drv_define) {
size = 0xFF;
timeout = 0x01;
} else {
size = phalmac_rxagg_cfg->threshold.size;
timeout = phalmac_rxagg_cfg->threshold.timeout;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_MODE);
if ((agg_enable & BIT_RXDMA_AGG_EN) != 0)
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
value8 | BIT_DMA_MODE);
else
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
value8 & ~(BIT_DMA_MODE));
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_sdio_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
return PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_8_sdio_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_sdio_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u16 word;
u8 byte[2];
__le16 le_word;
} value16 = {0x0000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (2 - 1)) != 0 ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
value16.byte[0] =
PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
value16.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 1);
value16.word = le16_to_cpu(value16.le_word);
} else {
#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
if ((halmac_offset & 0xffffef00) == 0x00000000) {
value16.byte[0] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset);
value16.byte[1] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 1);
value16.word = le16_to_cpu(value16.word);
} else {
value16.word = PLATFORM_SDIO_CMD53_READ_16(
driver_adapter, halmac_offset);
}
#else
value16.word = PLATFORM_SDIO_CMD53_READ_16(driver_adapter,
halmac_offset);
#endif
}
return value16.word;
}
/**
* halmac_reg_write_16_sdio_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (2 - 1)) != 0 ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
(u8)(halmac_data & 0xFF));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
(u8)((halmac_data & 0xFF00) >> 8));
} else {
PLATFORM_SDIO_CMD53_WRITE_16(driver_adapter, halmac_offset,
halmac_data);
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_sdio_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u32 halmac_offset_old = 0;
union {
u32 dword;
u8 byte[4];
__le32 le_dword;
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_offset_old = halmac_offset;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (4 - 1)) != 0) {
value32.byte[0] =
PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
value32.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 1);
value32.byte[2] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 2);
value32.byte[3] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 3);
value32.dword = le32_to_cpu(value32.le_dword);
} else {
#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
if ((halmac_offset_old & 0xffffef00) == 0x00000000) {
value32.byte[0] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset);
value32.byte[1] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 1);
value32.byte[2] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 2);
value32.byte[3] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 3);
value32.dword = le32_to_cpu(value32.dword);
} else {
value32.dword = PLATFORM_SDIO_CMD53_READ_32(
driver_adapter, halmac_offset);
}
#else
value32.dword = PLATFORM_SDIO_CMD53_READ_32(driver_adapter,
halmac_offset);
#endif
}
return value32.dword;
}
/**
* halmac_reg_write_32_sdio_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (4 - 1)) != 0) {
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
(u8)(halmac_data & 0xFF));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
(u8)((halmac_data & 0xFF00) >> 8));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 2,
(u8)((halmac_data & 0xFF0000) >> 16));
PLATFORM_SDIO_CMD52_WRITE(
driver_adapter, halmac_offset + 3,
(u8)((halmac_data & 0xFF000000) >> 24));
} else {
PLATFORM_SDIO_CMD53_WRITE_32(driver_adapter, halmac_offset,
halmac_data);
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_nbyte_sdio_88xx() - read n byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_size : register value size
* @halmac_data : register value
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_size,
u8 *halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0) {
pr_err("halmac_offset error = 0x%x\n", halmac_offset);
return HALMAC_RET_FAIL;
}
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) {
pr_err("halmac_state error = 0x%x\n",
halmac_adapter->halmac_state.mac_power);
return HALMAC_RET_FAIL;
}
PLATFORM_SDIO_CMD53_READ_N(driver_adapter, halmac_offset, halmac_size,
halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size
* @pcmd53_addr : cmd53 addr value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr)
{
u32 four_byte_len;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_queue_select queue_sel;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if (!halmac_buf) {
pr_err("halmac_buf is NULL!!\n");
return HALMAC_RET_DATA_BUF_NULL;
}
if (halmac_size == 0) {
pr_err("halmac_size is 0!!\n");
return HALMAC_RET_DATA_SIZE_INCORRECT;
}
queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
switch (queue_sel) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
break;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0);
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
break;
case HALMAC_DMA_MAPPING_LOW:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
*pcmd53_addr = (*pcmd53_addr << 13) |
(four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
u8 i, align_size_ok = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if ((align_size & 0xF000) != 0) {
pr_err("Align size is out of range\n");
return HALMAC_RET_FAIL;
}
for (i = 3; i <= 11; i++) {
if (align_size == 1 << i) {
align_size_ok = 1;
break;
}
}
if (align_size_ok == 0) {
pr_err("Align size is not 2^3 ~ 2^11\n");
return HALMAC_RET_FAIL;
}
/*Keep sdio tx agg alignment size for driver query*/
halmac_adapter->hw_config_info.tx_align_size = align_size;
if (enable)
HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
0x8000 | align_size);
else
HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
align_size);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_tx_allowed_sdio_88xx() - check tx status
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size, include txdesc
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size)
{
u8 *curr_packet;
u16 *curr_free_space;
u32 i, counter;
u32 tx_agg_num, packet_size = 0;
u32 tx_required_page_num, total_required_page_num = 0;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
void *driver_adapter = NULL;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_TX_ALLOWED_SDIO);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(halmac_buf);
curr_packet = halmac_buf;
tx_agg_num = tx_agg_num == 0 ? 1 : tx_agg_num;
switch ((enum halmac_queue_select)GET_TX_DESC_QSEL(curr_packet)) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
break;
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
return HALMAC_RET_SUCCESS;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
curr_free_space =
&halmac_adapter->sdio_free_space.high_queue_number;
break;
case HALMAC_DMA_MAPPING_NORMAL:
curr_free_space =
&halmac_adapter->sdio_free_space.normal_queue_number;
break;
case HALMAC_DMA_MAPPING_LOW:
curr_free_space =
&halmac_adapter->sdio_free_space.low_queue_number;
break;
case HALMAC_DMA_MAPPING_EXTRA:
curr_free_space =
&halmac_adapter->sdio_free_space.extra_queue_number;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
for (i = 0; i < tx_agg_num; i++) {
packet_size = GET_TX_DESC_TXPKTSIZE(curr_packet) +
GET_TX_DESC_OFFSET(curr_packet) +
(GET_TX_DESC_PKT_OFFSET(curr_packet) << 3);
tx_required_page_num =
(packet_size >>
halmac_adapter->hw_config_info.page_size_2_power) +
((packet_size &
(halmac_adapter->hw_config_info.page_size - 1)) ?
1 :
0);
total_required_page_num += tx_required_page_num;
packet_size = HALMAC_ALIGN(packet_size, 8);
curr_packet += packet_size;
}
counter = 10;
do {
if ((u32)(*curr_free_space +
halmac_adapter->sdio_free_space.public_queue_number) >
total_required_page_num) {
if (*curr_free_space >= total_required_page_num) {
*curr_free_space -=
(u16)total_required_page_num;
} else {
halmac_adapter->sdio_free_space
.public_queue_number -=
(u16)(total_required_page_num -
*curr_free_space);
*curr_free_space = 0;
}
status = halmac_check_oqt_88xx(halmac_adapter,
tx_agg_num, halmac_buf);
if (status != HALMAC_RET_SUCCESS)
return status;
break;
}
halmac_update_sdio_free_page_88xx(halmac_adapter);
counter--;
if (counter == 0)
return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
} while (1);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
u8 rtemp;
u32 counter = 1000;
void *driver_adapter = NULL;
union {
u32 dword;
u8 byte[4];
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
PLATFORM_SDIO_CMD53_WRITE_32(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK),
halmac_offset | BIT(19) | BIT(17));
do {
rtemp = PLATFORM_SDIO_CMD52_READ(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
((REG_SDIO_INDIRECT_REG_CFG + 2) &
HALMAC_SDIO_LOCAL_MSK));
counter--;
} while ((rtemp & BIT(4)) != 0 && counter > 0);
value32.dword = PLATFORM_SDIO_CMD53_READ_32(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK));
return value32.dword;
}

73
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_sdio.h
View File

@ -1,73 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_SDIO_H_
#define _HALMAC_API_88XX_SDIO_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
enum halmac_ret_status
halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status
halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
enum halmac_ret_status
halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 enable, u16 align_size);
enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
enum halmac_ret_status
halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size);
u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_size,
u8 *halmac_data);
#endif /* _HALMAC_API_88XX_SDIO_H_ */

540
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_usb.c
View File

@ -1,540 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_usb_cfg_88xx() - init USB
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
u8 value8 = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_USB_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
value8 |= (BIT_DMA_MODE |
(0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */
if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
0x20) { /* usb3.0 */
value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
} else {
if ((PLATFORM_REG_READ_8(driver_adapter, REG_USB_USBSTAT) &
0x3) == 0x1) /* usb2.0 */
value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED
<< BIT_SHIFT_BURST_SIZE;
else /* usb1.1 */
value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED
<< BIT_SHIFT_BURST_SIZE;
}
PLATFORM_REG_WRITE_8(driver_adapter, REG_RXDMA_MODE, value8);
PLATFORM_REG_WRITE_16(
driver_adapter, REG_TXDMA_OFFSET_CHK,
PLATFORM_REG_READ_16(driver_adapter, REG_TXDMA_OFFSET_CHK) |
BIT_DROP_DATA_EN);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_usb_cfg_88xx() - deinit USB
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_USB_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
u8 dma_usb_agg;
u8 size = 0, timeout = 0, agg_enable = 0;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
dma_usb_agg =
HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
switch (phalmac_rxagg_cfg->mode) {
case HALMAC_RX_AGG_MODE_NONE:
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
case HALMAC_RX_AGG_MODE_DMA:
agg_enable |= BIT_RXDMA_AGG_EN;
dma_usb_agg |= BIT(7);
break;
case HALMAC_RX_AGG_MODE_USB:
agg_enable |= BIT_RXDMA_AGG_EN;
dma_usb_agg &= ~BIT(7);
break;
default:
pr_err("%s switch case not support\n", __func__);
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
}
if (!phalmac_rxagg_cfg->threshold.drv_define) {
if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
0x20) {
/* usb3.0 */
size = 0x5;
timeout = 0xA;
} else {
/* usb2.0 */
size = 0x5;
timeout = 0x20;
}
} else {
size = phalmac_rxagg_cfg->threshold.size;
timeout = phalmac_rxagg_cfg->threshold.timeout;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3,
dma_usb_agg);
HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_usb_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_8_usb_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_usb_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
union {
u16 word;
u8 byte[2];
} value16 = {0x0000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value16.word = PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
return value16.word;
}
/**
* halmac_reg_write_16_usb_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_usb_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
union {
u32 dword;
u8 byte[4];
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value32.dword = PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
return value32.dword;
}
/**
* halmac_reg_write_32_usb_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_set_bulkout_num_usb_88xx() - inform bulk-out num
* @halmac_adapter : the adapter of halmac
* @bulkout_num : usb bulk-out number
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
u8 bulkout_num)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SET_BULKOUT_NUM);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->halmac_bulkout_num = bulkout_num;
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size
* @bulkout_id : usb bulk-out id
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_queue_select queue_sel;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_GET_USB_BULKOUT_ID);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if (!halmac_buf) {
pr_err("halmac_buf is NULL!!\n");
return HALMAC_RET_DATA_BUF_NULL;
}
if (halmac_size == 0) {
pr_err("halmac_size is 0!!\n");
return HALMAC_RET_DATA_SIZE_INCORRECT;
}
queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
switch (queue_sel) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
dma_mapping = HALMAC_DMA_MAPPING_HIGH;
break;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*bulkout_id = 0;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*bulkout_id = 1;
break;
case HALMAC_DMA_MAPPING_LOW:
*bulkout_id = 2;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*bulkout_id = 3;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}

62
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_usb.h
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@ -1,62 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_USB_H_
#define _HALMAC_API_88XX_USB_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
enum halmac_ret_status
halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status
halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
u8 bulkout_num);
enum halmac_ret_status
halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
#endif /* _HALMAC_API_88XX_USB_H_ */

4465
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.c
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File diff suppressed because it is too large Load Diff

310
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.h
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@ -1,310 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FUNC_88XX_H_
#define _HALMAC_FUNC_88XX_H_
#include "../halmac_type.h"
void halmac_init_offload_feature_state_machine_88xx(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_h2c_pkt_88xx(struct halmac_adapter *halmac_adapter, u8 *hal_buff,
u32 size, bool ack);
enum halmac_ret_status
halmac_download_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
u8 *hal_buf, u32 size);
enum halmac_ret_status
halmac_set_h2c_header_88xx(struct halmac_adapter *halmac_adapter,
u8 *hal_h2c_hdr, u16 *seq, bool ack);
enum halmac_ret_status halmac_set_fw_offload_h2c_header_88xx(
struct halmac_adapter *halmac_adapter, u8 *hal_h2c_hdr,
struct halmac_h2c_header_info *h2c_header_info, u16 *seq_num);
enum halmac_ret_status
halmac_dump_efuse_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_func_read_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, u8 *efuse_map);
enum halmac_ret_status
halmac_func_write_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u8 value);
enum halmac_ret_status
halmac_func_switch_efuse_bank_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank efuse_bank);
enum halmac_ret_status
halmac_read_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
u8 *map);
enum halmac_ret_status
halmac_func_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 offset, u8 value);
enum halmac_ret_status
halmac_func_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_pg_efuse_info *pg_efuse_info,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_eeprom_parser_88xx(struct halmac_adapter *halmac_adapter,
u8 *physical_efuse_map, u8 *logical_efuse_map);
enum halmac_ret_status
halmac_read_hw_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, u8 *efuse_map);
enum halmac_ret_status
halmac_dlfw_to_mem_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
u32 dest, u32 code_size);
enum halmac_ret_status
halmac_send_fwpkt_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
u32 code_size);
enum halmac_ret_status
halmac_iddma_dlfw_88xx(struct halmac_adapter *halmac_adapter, u32 source,
u32 dest, u32 length, u8 first);
enum halmac_ret_status
halmac_check_fw_chksum_88xx(struct halmac_adapter *halmac_adapter,
u32 memory_address);
enum halmac_ret_status
halmac_dlfw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_free_dl_fw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_pwr_seq_parser_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
u8 fab, u8 intf,
struct halmac_wl_pwr_cfg_ **pp_pwr_seq_cfg
);
enum halmac_ret_status
halmac_get_h2c_buff_free_space_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_h2c_set_pwr_mode_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwlps_option *hal_fw_lps_opt);
enum halmac_ret_status
halmac_func_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
u8 *original_h2c, u16 *seq, u8 ack);
enum halmac_ret_status
halmac_media_status_rpt_88xx(struct halmac_adapter *halmac_adapter, u8 op_mode,
u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
enum halmac_ret_status halmac_send_h2c_update_datapack_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type,
struct halmac_phy_parameter_info *para_info);
enum halmac_ret_status
halmac_send_h2c_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type);
enum halmac_ret_status
halmac_send_bt_coex_cmd_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
u32 bt_size, u8 ack);
enum halmac_ret_status
halmac_func_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_switch_option *cs_option);
enum halmac_ret_status
halmac_func_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_general_info *general_info);
enum halmac_ret_status
halmac_send_h2c_ps_tuning_para_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_parse_c2h_packet_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size);
enum halmac_ret_status
halmac_send_h2c_update_packet_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_packet_id pkt_id, u8 *pkt,
u32 pkt_size);
enum halmac_ret_status
halmac_send_h2c_phy_parameter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_phy_parameter_info *para_info,
bool full_fifo);
enum halmac_ret_status
halmac_dump_physical_efuse_fw_88xx(struct halmac_adapter *halmac_adapter,
u32 offset, u32 size, u8 *efuse_map);
enum halmac_ret_status halmac_send_h2c_update_bcn_parse_info_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_bcn_ie_info *bcn_ie_info);
enum halmac_ret_status
halmac_convert_to_sdio_bus_offset_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_offset);
enum halmac_ret_status
halmac_update_sdio_free_page_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_update_oqt_free_space_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_efuse_cmd_construct_state
halmac_query_efuse_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_efuse_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_cmd_construct_state dest_state);
enum halmac_cfg_para_cmd_construct_state
halmac_query_cfg_para_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_cfg_para_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cfg_para_cmd_construct_state dest_state);
enum halmac_scan_cmd_construct_state
halmac_query_scan_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_scan_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_scan_cmd_construct_state dest_state);
enum halmac_ret_status halmac_query_cfg_para_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_dump_physical_efuse_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_dump_logical_efuse_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_channel_switch_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_update_packet_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status
halmac_query_iqk_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status halmac_query_power_tracking_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status
halmac_query_psd_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status
halmac_verify_io_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_verify_send_rsvd_page_88xx(struct halmac_adapter *halmac_adapter);
void halmac_power_save_cb_88xx(void *cb_data);
enum halmac_ret_status
halmac_buffer_read_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, enum hal_fifo_sel halmac_fifo_sel,
u8 *fifo_map);
void halmac_restore_mac_register_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_restore_info *restore_info,
u32 restore_num);
void halmac_api_record_id_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_api_id api_id);
enum halmac_ret_status
halmac_set_usb_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_usb_mode usb_mode);
void halmac_enable_bb_rf_88xx(struct halmac_adapter *halmac_adapter, u8 enable);
void halmac_config_sdio_tx_page_threshold_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_tx_page_threshold_info *threshold_info);
enum halmac_ret_status
halmac_rqpn_parser_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode,
struct halmac_rqpn_ *pwr_seq_cfg);
enum halmac_ret_status
halmac_check_oqt_88xx(struct halmac_adapter *halmac_adapter, u32 tx_agg_num,
u8 *halmac_buf);
enum halmac_ret_status
halmac_pg_num_parser_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode,
struct halmac_pg_num_ *pg_num_table);
enum halmac_ret_status
halmac_parse_intf_phy_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_intf_phy_para_ *intf_phy_para,
enum halmac_intf_phy_platform platform,
enum hal_intf_phy intf_phy);
enum halmac_ret_status
halmac_dbi_write32_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
u32 data);
u32 halmac_dbi_read32_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
enum halmac_ret_status
halmac_dbi_write8_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
u8 data);
u8 halmac_dbi_read8_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
u16 halmac_mdio_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u8 speed
);
enum halmac_ret_status
halmac_mdio_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr, u16 data,
u8 speed);
void halmac_config_ampdu_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ampdu_config *ampdu_config);
enum halmac_ret_status
halmac_usbphy_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u16 data, u8 speed);
u16 halmac_usbphy_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u8 speed);
#endif /* _HALMAC_FUNC_88XX_H_ */

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drivers/staging/rtlwifi/halmac/halmac_api.c
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@ -1,412 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_2_platform.h"
#include "halmac_type.h"
#include "halmac_88xx/halmac_api_88xx.h"
#include "halmac_88xx/halmac_88xx_cfg.h"
#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
static enum halmac_ret_status
halmac_check_platform_api(void *driver_adapter,
enum halmac_interface halmac_interface,
struct halmac_platform_api *halmac_platform_api)
{
void *adapter_local = NULL;
adapter_local = driver_adapter;
if (!halmac_platform_api)
return HALMAC_RET_PLATFORM_API_NULL;
if (halmac_interface == HALMAC_INTERFACE_SDIO) {
if (!halmac_platform_api->SDIO_CMD52_READ) {
pr_err("(!halmac_platform_api->SDIO_CMD52_READ)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_8) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_16) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_32) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_N) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_N)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD52_WRITE) {
pr_err("(!halmac_platform_api->SDIO_CMD52_WRITE)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_8) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_16) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_32) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
if (halmac_interface == HALMAC_INTERFACE_USB ||
halmac_interface == HALMAC_INTERFACE_PCIE) {
if (!halmac_platform_api->REG_READ_8) {
pr_err("(!halmac_platform_api->REG_READ_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_READ_16) {
pr_err("(!halmac_platform_api->REG_READ_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_READ_32) {
pr_err("(!halmac_platform_api->REG_READ_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_8) {
pr_err("(!halmac_platform_api->REG_WRITE_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_16) {
pr_err("(!halmac_platform_api->REG_WRITE_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_32) {
pr_err("(!halmac_platform_api->REG_WRITE_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
if (!halmac_platform_api->EVENT_INDICATION) {
pr_err("(!halmac_platform_api->EVENT_INDICATION)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
halmac_convert_to_sdio_bus_offset(u32 *halmac_offset)
{
switch ((*halmac_offset) & 0xFFFF0000) {
case WLAN_IOREG_OFFSET:
*halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) |
(*halmac_offset & HALMAC_WLAN_MAC_REG_MSK);
break;
case SDIO_LOCAL_OFFSET:
*halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
break;
default:
*halmac_offset = 0xFFFFFFFF;
return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
static u8
platform_reg_read_8_sdio(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
u32 offset)
{
u32 halmac_offset = offset;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
return halmac_platform_api->SDIO_CMD52_READ(driver_adapter,
halmac_offset);
}
static enum halmac_ret_status
platform_reg_write_8_sdio(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
u32 offset, u8 data)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u32 halmac_offset = offset;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("halmac_reg_write_8_sdio_88xx error = %x\n", status);
return status;
}
halmac_platform_api->SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
data);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
halmac_get_chip_info(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter *halmac_adapter)
{
struct halmac_api *halmac_api = (struct halmac_api *)NULL;
u8 chip_id, chip_version;
u32 polling_count;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
/* Get Chip_id and Chip_version */
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
platform_reg_write_8_sdio(
driver_adapter, halmac_platform_api, REG_SDIO_HSUS_CTRL,
platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SDIO_HSUS_CTRL) &
~(BIT(0)));
polling_count = 10000;
while (!(platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SDIO_HSUS_CTRL) &
0x02)) {
polling_count--;
if (polling_count == 0)
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
}
chip_id = platform_reg_read_8_sdio(
driver_adapter, halmac_platform_api, REG_SYS_CFG2);
chip_version = platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SYS_CFG1 + 1) >>
4;
} else {
chip_id = halmac_platform_api->REG_READ_8(driver_adapter,
REG_SYS_CFG2);
chip_version = halmac_platform_api->REG_READ_8(
driver_adapter, REG_SYS_CFG1 + 1) >>
4;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]Chip id : 0x%X\n", chip_id);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]Chip version : 0x%X\n", chip_version);
halmac_adapter->chip_version = (enum halmac_chip_ver)chip_version;
if (chip_id == HALMAC_CHIP_ID_HW_DEF_8822B)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8821C)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8821C;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8814B)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8814B;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8197F)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8197F;
else
halmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
if (halmac_adapter->chip_id == HALMAC_CHIP_ID_UNDEFINE)
return HALMAC_RET_CHIP_NOT_SUPPORT;
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_adapter() - init halmac_adapter
* @driver_adapter : the adapter of caller
* @halmac_platform_api : the platform APIs which is used in halmac APIs
* @halmac_interface : bus interface
* @pp_halmac_adapter : the adapter of halmac
* @pp_halmac_api : the function pointer of APIs, caller shall call APIs by
* function pointer
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_adapter(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter **pp_halmac_adapter,
struct halmac_api **pp_halmac_api)
{
struct halmac_adapter *halmac_adapter = (struct halmac_adapter *)NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 i;
u8 x[4];
} ENDIAN_CHECK = {0x01000000};
status = halmac_check_platform_api(driver_adapter, halmac_interface,
halmac_platform_api);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
HALMAC_SVN_VER "\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_adapter_88xx ==========>\n");
/* Check endian setting - Little endian : 1, Big endian : 0*/
if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
pr_err("Endian setting Err!!\n");
return HALMAC_RET_ENDIAN_ERR;
}
halmac_adapter = kzalloc(sizeof(*halmac_adapter), GFP_KERNEL);
if (!halmac_adapter) {
/* out of memory */
return HALMAC_RET_MALLOC_FAIL;
}
/* return halmac adapter address to caller */
*pp_halmac_adapter = halmac_adapter;
/* Record caller info */
halmac_adapter->halmac_platform_api = halmac_platform_api;
halmac_adapter->driver_adapter = driver_adapter;
halmac_interface = halmac_interface == HALMAC_INTERFACE_AXI ?
HALMAC_INTERFACE_PCIE :
halmac_interface;
halmac_adapter->halmac_interface = halmac_interface;
spin_lock_init(&halmac_adapter->efuse_lock);
spin_lock_init(&halmac_adapter->h2c_seq_lock);
/*Get Chip*/
if (halmac_get_chip_info(driver_adapter, halmac_platform_api,
halmac_interface,
halmac_adapter) != HALMAC_RET_SUCCESS) {
pr_err("HALMAC_RET_CHIP_NOT_SUPPORT\n");
return HALMAC_RET_CHIP_NOT_SUPPORT;
}
/* Assign function pointer to halmac API */
halmac_init_adapter_para_88xx(halmac_adapter);
status = halmac_mount_api_88xx(halmac_adapter);
/* Return halmac API function pointer */
*pp_halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_adapter_88xx <==========\n");
return status;
}
/**
* halmac_halt_api() - stop halmac_api action
* @halmac_adapter : the adapter of halmac
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
struct halmac_platform_api *halmac_platform_api =
(struct halmac_platform_api *)NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_platform_api = halmac_adapter->halmac_platform_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
halmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_adapter() - deinit halmac adapter
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_adapter(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]halmac_deinit_adapter_88xx ==========>\n");
kfree(halmac_adapter->hal_efuse_map);
halmac_adapter->hal_efuse_map = (u8 *)NULL;
kfree(halmac_adapter->halmac_state.psd_set.data);
halmac_adapter->halmac_state.psd_set.data = (u8 *)NULL;
kfree(halmac_adapter->halmac_api);
halmac_adapter->halmac_api = NULL;
halmac_adapter->hal_adapter_backup = NULL;
kfree(halmac_adapter);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_version() - get HALMAC version
* @version : return version of major, prototype and minor information
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_get_version(struct halmac_ver *version)
{
version->major_ver = (u8)HALMAC_MAJOR_VER;
version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
version->minor_ver = (u8)HALMAC_MINOR_VER;
return HALMAC_RET_SUCCESS;
}

70
drivers/staging/rtlwifi/halmac/halmac_api.h
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@ -1,70 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_H_
#define _HALMAC_API_H_
#define HALMAC_SVN_VER "13348M"
#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */
/* For halmac_api num change or prototype change, increment prototype version.
* Otherwise, increase minor version
*/
#define HALMAC_PROTOTYPE_VER 0x0003 /* prototype version */
#define HALMAC_MINOR_VER 0x0005 /* minor version */
#define HALMAC_PATCH_VER 0x0000 /* patch version */
#include "halmac_2_platform.h"
#include "halmac_type.h"
#include "halmac_usb_reg.h"
#include "halmac_sdio_reg.h"
#include "halmac_bit2.h"
#include "halmac_reg2.h"
#include "halmac_tx_desc_nic.h"
#include "halmac_rx_desc_nic.h"
#include "halmac_tx_bd_nic.h"
#include "halmac_rx_bd_nic.h"
#include "halmac_fw_offload_c2h_nic.h"
#include "halmac_fw_offload_h2c_nic.h"
#include "halmac_h2c_extra_info_nic.h"
#include "halmac_original_c2h_nic.h"
#include "halmac_original_h2c_nic.h"
#include "halmac_tx_desc_chip.h"
#include "halmac_rx_desc_chip.h"
#include "halmac_tx_bd_chip.h"
#include "halmac_rx_bd_chip.h"
#include "halmac_88xx/halmac_88xx_cfg.h"
#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
#include "halmac_reg_8822b.h"
#include "halmac_bit_8822b.h"
enum halmac_ret_status
halmac_init_adapter(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter **pp_halmac_adapter,
struct halmac_api **pp_halmac_api);
enum halmac_ret_status
halmac_deinit_adapter(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_get_version(struct halmac_ver *version);
#endif

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drivers/staging/rtlwifi/halmac/halmac_bit2.h
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12092
drivers/staging/rtlwifi/halmac/halmac_bit_8822b.h
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111
drivers/staging/rtlwifi/halmac/halmac_fw_info.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FW_INFO_H_
#define _HALMAC_FW_INFO_H_
#define H2C_FORMAT_VERSION 6
#define H2C_ACK_HDR_CONTENT_LENGTH 8
#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
#define C2H_DBG_HEADER_LENGTH 4
#define C2H_DBG_CONTENT_MAX_LENGTH 228
#define C2H_DBG_CONTENT_SEQ_OFFSET 1
/* Rename from FW SysHalCom_Debug_RAM.h */
#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
#define fw_reg_wow_reason 0x1C7
enum halmac_data_type {
HALMAC_DATA_TYPE_MAC_REG = 0x00,
HALMAC_DATA_TYPE_BB_REG = 0x01,
HALMAC_DATA_TYPE_RADIO_A = 0x02,
HALMAC_DATA_TYPE_RADIO_B = 0x03,
HALMAC_DATA_TYPE_RADIO_C = 0x04,
HALMAC_DATA_TYPE_RADIO_D = 0x05,
HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,
HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,
HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_packet_id {
HALMAC_PACKET_PROBE_REQ = 0x00,
HALMAC_PACKET_SYNC_BCN = 0x01,
HALMAC_PACKET_DISCOVERY_BCN = 0x02,
HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
};
/* Channel Switch Action ID */
enum halmac_cs_action_id {
HALMAC_CS_ACTION_NONE = 0x00,
HALMAC_CS_ACTIVE_SCAN = 0x01,
HALMAC_CS_NAN_NONMASTER_DW = 0x02,
HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
HALMAC_CS_NAN_MASTER_NONDW = 0x04,
HALMAC_CS_NAN_MASTER_DW = 0x05,
HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
};
/* Channel Switch Extra Action ID */
enum halmac_cs_extra_action_id {
HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_h2c_return_code {
HALMAC_H2C_RETURN_SUCCESS = 0x00,
HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */
HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */
HALMAC_H2C_RETURN_RUN_ERR_EMPTY =
0x06, /* No data in dedicated buffer */
HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */
HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */
HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */
HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */
HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */
HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */
HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_scan_report_code {
HALMAC_SCAN_REPORT_DONE = 0x00,
HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */
HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */
HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */
HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
};
#endif

173
drivers/staging/rtlwifi/halmac/halmac_fw_offload_c2h_nic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
#define C2H_SUB_CMD_ID_C2H_DBG 0X00
#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define C2H_HDR_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_HDR_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_HDR_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_HDR_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_HDR_GET_C2H_SUB_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_HDR_SET_C2H_SUB_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_HDR_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_HDR_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_DBG_GET_DBG_MSG(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_DBG_SET_DBG_MSG(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define BT_COEX_INFO_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define BT_COEX_INFO_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define SCAN_STATUS_RPT_GET_H2C_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define SCAN_STATUS_RPT_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define H2C_ACK_HDR_GET_H2C_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define H2C_ACK_HDR_SET_H2C_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define H2C_ACK_HDR_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 16)
#define H2C_ACK_HDR_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 16, __value)
#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 32)
#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 32, __value)
#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X10, 0, 32)
#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X10, 0, 32, __value)
#define BT_COEX_ACK_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 8)
#define BT_COEX_ACK_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 8, __value)
#define PSD_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define PSD_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define PSD_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define PSD_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define PSD_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define PSD_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define PSD_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define PSD_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define PSD_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define PSD_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define PSD_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define PSD_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define EFUSE_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define EFUSE_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define EFUSE_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define EFUSE_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define EFUSE_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define EFUSE_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define EFUSE_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define EFUSE_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define EFUSE_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define EFUSE_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define EFUSE_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define EFUSE_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define IQK_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define IQK_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define IQK_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define IQK_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define IQK_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define IQK_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define IQK_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define IQK_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define IQK_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define IQK_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define IQK_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define IQK_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define CCX_RPT_GET_CCX_RPT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X4, 0, 129)
#define CCX_RPT_SET_CCX_RPT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X4, 0, 129, __value)
#endif

504
drivers/staging/rtlwifi/halmac/halmac_fw_offload_h2c_nic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
#define CMD_ID_CHANNEL_SWITCH 0XFF
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
#define CMD_ID_CFG_PARAMETER 0XFF
#define CMD_ID_UPDATE_DATAPACK 0XFF
#define CMD_ID_RUN_DATAPACK 0XFF
#define CMD_ID_DOWNLOAD_FLASH 0XFF
#define CMD_ID_UPDATE_PACKET 0XFF
#define CMD_ID_GENERAL_INFO 0XFF
#define CMD_ID_IQK 0XFF
#define CMD_ID_POWER_TRACKING 0XFF
#define CMD_ID_PSD 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_CHANNEL_SWITCH 0X01
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
#define CATEGORY_CFG_PARAMETER 0X01
#define CATEGORY_UPDATE_DATAPACK 0X01
#define CATEGORY_RUN_DATAPACK 0X01
#define CATEGORY_DOWNLOAD_FLASH 0X01
#define CATEGORY_UPDATE_PACKET 0X01
#define CATEGORY_GENERAL_INFO 0X01
#define CATEGORY_IQK 0X01
#define CATEGORY_POWER_TRACKING 0X01
#define CATEGORY_PSD 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define SUB_CMD_ID_CHANNEL_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
#define SUB_CMD_ID_CFG_PARAMETER 0X08
#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
#define SUB_CMD_ID_RUN_DATAPACK 0X0A
#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
#define SUB_CMD_ID_UPDATE_PACKET 0X0C
#define SUB_CMD_ID_GENERAL_INFO 0X0D
#define SUB_CMD_ID_IQK 0X0E
#define SUB_CMD_ID_POWER_TRACKING 0X0F
#define SUB_CMD_ID_PSD 0X10
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define H2C_CMD_HEADER_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
#define H2C_CMD_HEADER_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
#define H2C_CMD_HEADER_SET_ACK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
#define H2C_CMD_HEADER_GET_TOTAL_LEN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
#define H2C_CMD_HEADER_SET_TOTAL_LEN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
#define H2C_CMD_HEADER_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
#define H2C_CMD_HEADER_SET_SEQ_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
#define FW_OFFLOAD_H2C_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
#define FW_OFFLOAD_H2C_SET_CATEGORY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
#define FW_OFFLOAD_H2C_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
#define FW_OFFLOAD_H2C_SET_ACK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
#define FW_OFFLOAD_H2C_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define FW_OFFLOAD_H2C_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 16)
#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 16, __value)
#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
#define CHANNEL_SWITCH_GET_SWITCH_START(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define CHANNEL_SWITCH_SET_SWITCH_START(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define CHANNEL_SWITCH_GET_DEST_CH_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define CHANNEL_SWITCH_SET_DEST_CH_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 2)
#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 2, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 4)
#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 4, __value)
#define CHANNEL_SWITCH_GET_DEST_BW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 28, 4)
#define CHANNEL_SWITCH_SET_DEST_BW(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 28, 4, __value)
#define CHANNEL_SWITCH_GET_DEST_CH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define CHANNEL_SWITCH_SET_DEST_CH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 24, 8)
#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 24, 8, __value)
#define CHANNEL_SWITCH_GET_TSF_HIGH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define CHANNEL_SWITCH_SET_TSF_HIGH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define CHANNEL_SWITCH_GET_TSF_LOW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define CHANNEL_SWITCH_SET_TSF_LOW(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 16)
#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 16, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 4)
#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 4, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 12, 4)
#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 12, 4, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
#define CFG_PARAMETER_GET_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define CFG_PARAMETER_SET_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define CFG_PARAMETER_GET_INIT_CASE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 1)
#define CFG_PARAMETER_SET_INIT_CASE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 1, __value)
#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define UPDATE_DATAPACK_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define UPDATE_DATAPACK_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define UPDATE_DATAPACK_GET_END_SEGMENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 1)
#define UPDATE_DATAPACK_SET_END_SEGMENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 1, __value)
#define RUN_DATAPACK_GET_DATAPACK_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define RUN_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define DOWNLOAD_FLASH_GET_SPI_CMD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define DOWNLOAD_FLASH_SET_SPI_CMD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define DOWNLOAD_FLASH_GET_LOCATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 16)
#define DOWNLOAD_FLASH_SET_LOCATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 16, __value)
#define DOWNLOAD_FLASH_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
#define DOWNLOAD_FLASH_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
#define DOWNLOAD_FLASH_GET_START_ADDR(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define DOWNLOAD_FLASH_SET_START_ADDR(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define UPDATE_PACKET_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define UPDATE_PACKET_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define UPDATE_PACKET_GET_PACKET_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define UPDATE_PACKET_SET_PACKET_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define UPDATE_PACKET_GET_PACKET_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define UPDATE_PACKET_SET_PACKET_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define GENERAL_INFO_GET_REF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define GENERAL_INFO_SET_REF_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define GENERAL_INFO_GET_RF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 9)
#define GENERAL_INFO_SET_RF_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 9, __value)
#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define IQK_GET_CLEAR(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define IQK_SET_CLEAR(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define IQK_GET_SEGMENT_IQK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define IQK_SET_SEGMENT_IQK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define POWER_TRACKING_GET_ENABLE_A(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define POWER_TRACKING_SET_ENABLE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define POWER_TRACKING_GET_ENABLE_B(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define POWER_TRACKING_SET_ENABLE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define POWER_TRACKING_GET_ENABLE_C(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define POWER_TRACKING_SET_ENABLE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define POWER_TRACKING_GET_ENABLE_D(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
#define POWER_TRACKING_SET_ENABLE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
#define POWER_TRACKING_GET_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 3)
#define POWER_TRACKING_SET_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 3, __value)
#define POWER_TRACKING_GET_BBSWING_INDEX(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define POWER_TRACKING_SET_BBSWING_INDEX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 16, 8, __value)
#define PSD_GET_START_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define PSD_SET_START_PSD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define PSD_GET_END_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 16)
#define PSD_SET_END_PSD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 16, __value)
#define P2PPS_GET_OFFLOAD_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define P2PPS_GET_ROLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define P2PPS_SET_ROLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define P2PPS_GET_CTWINDOW_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define P2PPS_SET_CTWINDOW_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define P2PPS_GET_NOA_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
#define P2PPS_SET_NOA_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
#define P2PPS_GET_NOA_SEL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 1)
#define P2PPS_SET_NOA_SEL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 1, __value)
#define P2PPS_GET_ALLSTASLEEP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 5, 1)
#define P2PPS_SET_ALLSTASLEEP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 5, 1, __value)
#define P2PPS_GET_DISCOVERY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 6, 1)
#define P2PPS_SET_DISCOVERY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 6, 1, __value)
#define P2PPS_GET_P2P_PORT_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define P2PPS_SET_P2P_PORT_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define P2PPS_GET_P2P_GROUP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define P2PPS_SET_P2P_GROUP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define P2PPS_GET_P2P_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define P2PPS_SET_P2P_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define P2PPS_GET_CTWINDOW_LENGTH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define P2PPS_SET_CTWINDOW_LENGTH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define P2PPS_GET_NOA_DURATION_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define P2PPS_SET_NOA_DURATION_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define P2PPS_GET_NOA_INTERVAL_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define P2PPS_SET_NOA_INTERVAL_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define P2PPS_GET_NOA_START_TIME_PARA(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
#define P2PPS_SET_NOA_START_TIME_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
#define P2PPS_GET_NOA_COUNT_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
#define P2PPS_SET_NOA_COUNT_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
#define BT_COEX_GET_DATA_START(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define BT_COEX_SET_DATA_START(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CTRL_GET_NAN_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 2)
#define NAN_CTRL_SET_NAN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 2, __value)
#define NAN_CTRL_GET_SUPPORT_BAND(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 2)
#define NAN_CTRL_SET_SUPPORT_BAND(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 2, __value)
#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 10, 1)
#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 10, 1, __value)
#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 11, 1)
#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 11, 1, __value)
#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define NAN_CTRL_GET_CHANNEL_2G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define NAN_CTRL_SET_CHANNEL_2G(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define NAN_CTRL_GET_CHANNEL_5G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define NAN_CTRL_SET_CHANNEL_5G(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
#endif

104
drivers/staging/rtlwifi/halmac/halmac_h2c_extra_info_nic.h
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@ -1,104 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
#define PHY_PARAMETER_INFO_GET_LENGTH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
#define PHY_PARAMETER_INFO_SET_LENGTH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
#define PHY_PARAMETER_INFO_GET_IO_CMD(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 7)
#define PHY_PARAMETER_INFO_SET_IO_CMD(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 7, __value)
#define PHY_PARAMETER_INFO_GET_MSK_EN(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 15, 1)
#define PHY_PARAMETER_INFO_SET_MSK_EN(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 15, 1, __value)
#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_RF_ADDR(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_RF_ADDR(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_IO_ADDR(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
#define PHY_PARAMETER_INFO_SET_IO_ADDR(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
#define PHY_PARAMETER_INFO_GET_RF_PATH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 8)
#define PHY_PARAMETER_INFO_SET_RF_PATH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 8, __value)
#define PHY_PARAMETER_INFO_GET_DATA(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X04, 0, 32)
#define PHY_PARAMETER_INFO_SET_DATA(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X04, 0, 32, __value)
#define PHY_PARAMETER_INFO_GET_MASK(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X08, 0, 32)
#define PHY_PARAMETER_INFO_SET_MASK(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X08, 0, 32, __value)
#define CHANNEL_INFO_GET_CHANNEL(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
#define CHANNEL_INFO_SET_CHANNEL(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
#define CHANNEL_INFO_GET_PRI_CH_IDX(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 4)
#define CHANNEL_INFO_SET_PRI_CH_IDX(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 4, __value)
#define CHANNEL_INFO_GET_BANDWIDTH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 12, 4)
#define CHANNEL_INFO_SET_BANDWIDTH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 12, 4, __value)
#define CHANNEL_INFO_GET_TIMEOUT(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define CHANNEL_INFO_SET_TIMEOUT(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define CHANNEL_INFO_GET_ACTION_ID(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 7)
#define CHANNEL_INFO_SET_ACTION_ID(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 7, __value)
#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 31, 1)
#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 31, 1, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 7)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 7, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 7, 1)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 7, 1, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 8)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 8, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 1)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 1, __value)
#endif

43
drivers/staging/rtlwifi/halmac/halmac_intf_phy_cmd.h
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@ -1,43 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_INTF_PHY_CMD
#define HALMAC_INTF_PHY_CMD
/* Cut mask */
enum halmac_intf_phy_cut {
HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
HALMAC_INTF_PHY_CUT_A = BIT(1),
HALMAC_INTF_PHY_CUT_B = BIT(2),
HALMAC_INTF_PHY_CUT_C = BIT(3),
HALMAC_INTF_PHY_CUT_D = BIT(4),
HALMAC_INTF_PHY_CUT_E = BIT(5),
HALMAC_INTF_PHY_CUT_F = BIT(6),
HALMAC_INTF_PHY_CUT_G = BIT(7),
HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
};
/* IP selection */
enum halmac_ip_sel {
HALMAC_IP_SEL_INTF_PHY = 0,
HALMAC_IP_SEL_MAC = 1,
HALMAC_IP_SEL_PCIE_DBI = 2,
HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
};
/* Platform mask */
enum halmac_intf_phy_platform {
HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
};
#endif

392
drivers/staging/rtlwifi/halmac/halmac_original_c2h_nic.h
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@ -1,392 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_C2H 0X00
#define CMD_ID_DBG 0X00
#define CMD_ID_C2H_LB 0X01
#define CMD_ID_C2H_SND_TXBF 0X02
#define CMD_ID_C2H_CCX_RPT 0X03
#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
#define CMD_ID_C2H_RA_RPT 0X0C
#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define C2H_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define DBG_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define DBG_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define DBG_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define DBG_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define DBG_GET_DBG_STR1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define DBG_SET_DBG_STR1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define DBG_GET_DBG_STR2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define DBG_SET_DBG_STR2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define DBG_GET_DBG_STR3(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define DBG_SET_DBG_STR3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define DBG_GET_DBG_STR4(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define DBG_SET_DBG_STR4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define DBG_GET_DBG_STR5(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define DBG_SET_DBG_STR5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define DBG_GET_DBG_STR6(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define DBG_SET_DBG_STR6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define DBG_GET_DBG_STR7(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define DBG_SET_DBG_STR7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define DBG_GET_DBG_STR8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define DBG_SET_DBG_STR8(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define DBG_GET_DBG_STR9(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define DBG_SET_DBG_STR9(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define DBG_GET_DBG_STR10(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
#define DBG_SET_DBG_STR10(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
#define DBG_GET_DBG_STR11(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
#define DBG_SET_DBG_STR11(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
#define DBG_GET_DBG_STR12(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
#define DBG_SET_DBG_STR12(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
#define DBG_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define DBG_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define DBG_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define DBG_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_LB_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_LB_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_LB_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_LB_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_LB_GET_PAYLOAD1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 16)
#define C2H_LB_SET_PAYLOAD1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 16, __value)
#define C2H_LB_GET_PAYLOAD2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 32)
#define C2H_LB_SET_PAYLOAD2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 32, __value)
#define C2H_LB_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_LB_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_LB_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_LB_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_SND_TXBF_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SND_TXBF_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_SND_TXBF_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SND_TXBF_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_SND_TXBF_GET_SND_RESULT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 1)
#define C2H_SND_TXBF_SET_SND_RESULT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 1, __value)
#define C2H_SND_TXBF_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_SND_TXBF_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_SND_TXBF_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_SND_TXBF_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_CCX_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_CCX_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_CCX_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_CCX_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_CCX_RPT_GET_QSEL(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 5)
#define C2H_CCX_RPT_SET_QSEL(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 5, __value)
#define C2H_CCX_RPT_GET_BMC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 21, 1)
#define C2H_CCX_RPT_SET_BMC(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 21, 1, __value)
#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 22, 1)
#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 22, 1, __value)
#define C2H_CCX_RPT_GET_RETRY_OVER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 23, 1)
#define C2H_CCX_RPT_SET_RETRY_OVER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 23, 1, __value)
#define C2H_CCX_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_CCX_RPT_SET_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 6)
#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 6, __value)
#define C2H_CCX_RPT_GET_QUEUE7_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_CCX_RPT_SET_QUEUE7_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_CCX_RPT_GET_QUEUE15_8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_CCX_RPT_SET_QUEUE15_8(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_CCX_RPT_GET_SW_DEFINE_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_CCX_RPT_SET_SW_DEFINE_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_CCX_RPT_GET_SW_DEFINE_1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 4)
#define C2H_CCX_RPT_SET_SW_DEFINE_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 4, __value)
#define C2H_CCX_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_CCX_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_CCX_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_CCX_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 7)
#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 7, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_RA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_RA_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_RA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_RA_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_RA_RPT_GET_RATE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_RA_RPT_SET_RATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_RA_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_RA_RPT_SET_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_RA_RPT_GET_USE_LDPC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 1)
#define C2H_RA_RPT_SET_USE_LDPC(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 1, __value)
#define C2H_RA_RPT_GET_USE_TXBF(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 1, 1)
#define C2H_RA_RPT_SET_USE_TXBF(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 1, 1, __value)
#define C2H_RA_RPT_GET_COLLISION_STATE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_RA_RPT_SET_COLLISION_STATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_RA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_RA_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_RA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_RA_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA3(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA4(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA5(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA6(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA7(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_LEN(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_RA_PARA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_RA_PARA_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_RA_PARA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_RA_PARA_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_RA_PARA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_RA_PARA_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_RA_PARA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_RA_PARA_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_CUR_CHANNEL_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_CUR_CHANNEL_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_CUR_CHANNEL_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_CUR_CHANNEL_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_CUR_CHANNEL_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_CUR_CHANNEL_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_CUR_CHANNEL_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_CUR_CHANNEL_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_GPIO_WAKEUP_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_GPIO_WAKEUP_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_GPIO_WAKEUP_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_GPIO_WAKEUP_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_GPIO_WAKEUP_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_GPIO_WAKEUP_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_GPIO_WAKEUP_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_GPIO_WAKEUP_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#endif

1000
drivers/staging/rtlwifi/halmac/halmac_original_h2c_nic.h
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105
drivers/staging/rtlwifi/halmac/halmac_pwr_seq_cmd.h
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@ -1,105 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_POWER_SEQUENCE_CMD
#define HALMAC_POWER_SEQUENCE_CMD
#include "halmac_2_platform.h"
#include "halmac_type.h"
#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000
/* The value of cmd : 4 bits */
/* offset : the read register offset
* msk : the mask of the read value
* value : N/A, left by 0
* Note : dirver shall implement this function by read & msk
*/
#define HALMAC_PWR_CMD_READ 0x00
/*
* offset: the read register offset
* msk: the mask of the write bits
* value: write value
* Note: driver shall implement this cmd by read & msk after write
*/
#define HALMAC_PWR_CMD_WRITE 0x01
/* offset: the read register offset
* msk: the mask of the polled value
* value: the value to be polled, masked by the msd field.
* Note: driver shall implement this cmd by
* do{
* if( (Read(offset) & msk) == (value & msk) )
* break;
* } while(not timeout);
*/
#define HALMAC_PWR_CMD_POLLING 0x02
/* offset: the value to delay
* msk: N/A
* value: the unit of delay, 0: us, 1: ms
*/
#define HALMAC_PWR_CMD_DELAY 0x03
/* offset: N/A
* msk: N/A
* value: N/A
*/
#define HALMAC_PWR_CMD_END 0x04
/* The value of base : 4 bits */
/* define the base address of each block */
#define HALMAC_PWR_BASEADDR_MAC 0x00
#define HALMAC_PWR_BASEADDR_USB 0x01
#define HALMAC_PWR_BASEADDR_PCIE 0x02
#define HALMAC_PWR_BASEADDR_SDIO 0x03
/* The value of interface_msk : 4 bits */
#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
#define HALMAC_PWR_INTF_USB_MSK BIT(1)
#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/* The value of fab_msk : 4 bits */
#define HALMAC_PWR_FAB_TSMC_MSK BIT(0)
#define HALMAC_PWR_FAB_UMC_MSK BIT(1)
#define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/* The value of cut_msk : 8 bits */
#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
#define HALMAC_PWR_CUT_A_MSK BIT(1)
#define HALMAC_PWR_CUT_B_MSK BIT(2)
#define HALMAC_PWR_CUT_C_MSK BIT(3)
#define HALMAC_PWR_CUT_D_MSK BIT(4)
#define HALMAC_PWR_CUT_E_MSK BIT(5)
#define HALMAC_PWR_CUT_F_MSK BIT(6)
#define HALMAC_PWR_CUT_G_MSK BIT(7)
#define HALMAC_PWR_CUT_ALL_MSK 0xFF
enum halmac_pwrseq_cmd_delay_unit_ {
HALMAC_PWRSEQ_DELAY_US,
HALMAC_PWRSEQ_DELAY_MS,
};
/*Don't care endian issue, because element of pwer seq vector is fixed address*/
struct halmac_wl_pwr_cfg_ {
u16 offset;
u8 cut_msk;
u8 fab_msk : 4;
u8 interface_msk : 4;
u8 base : 4;
u8 cmd : 4;
u8 msk;
u8 value;
};
#endif

1121
drivers/staging/rtlwifi/halmac/halmac_reg2.h
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717
drivers/staging/rtlwifi/halmac/halmac_reg_8822b.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_HALMAC_REG_8822B_H
#define __INC_HALMAC_REG_8822B_H
#define REG_SYS_ISO_CTRL_8822B 0x0000
#define REG_SYS_FUNC_EN_8822B 0x0002
#define REG_SYS_PW_CTRL_8822B 0x0004
#define REG_SYS_CLK_CTRL_8822B 0x0008
#define REG_SYS_EEPROM_CTRL_8822B 0x000A
#define REG_EE_VPD_8822B 0x000C
#define REG_SYS_SWR_CTRL1_8822B 0x0010
#define REG_SYS_SWR_CTRL2_8822B 0x0014
#define REG_SYS_SWR_CTRL3_8822B 0x0018
#define REG_RSV_CTRL_8822B 0x001C
#define REG_RF_CTRL_8822B 0x001F
#define REG_AFE_LDO_CTRL_8822B 0x0020
#define REG_AFE_CTRL1_8822B 0x0024
#define REG_AFE_CTRL2_8822B 0x0028
#define REG_AFE_CTRL3_8822B 0x002C
#define REG_EFUSE_CTRL_8822B 0x0030
#define REG_LDO_EFUSE_CTRL_8822B 0x0034
#define REG_PWR_OPTION_CTRL_8822B 0x0038
#define REG_CAL_TIMER_8822B 0x003C
#define REG_ACLK_MON_8822B 0x003E
#define REG_GPIO_MUXCFG_8822B 0x0040
#define REG_GPIO_PIN_CTRL_8822B 0x0044
#define REG_GPIO_INTM_8822B 0x0048
#define REG_LED_CFG_8822B 0x004C
#define REG_FSIMR_8822B 0x0050
#define REG_FSISR_8822B 0x0054
#define REG_HSIMR_8822B 0x0058
#define REG_HSISR_8822B 0x005C
#define REG_GPIO_EXT_CTRL_8822B 0x0060
#define REG_PAD_CTRL1_8822B 0x0064
#define REG_WL_BT_PWR_CTRL_8822B 0x0068
#define REG_SDM_DEBUG_8822B 0x006C
#define REG_SYS_SDIO_CTRL_8822B 0x0070
#define REG_HCI_OPT_CTRL_8822B 0x0074
#define REG_AFE_CTRL4_8822B 0x0078
#define REG_LDO_SWR_CTRL_8822B 0x007C
#define REG_MCUFW_CTRL_8822B 0x0080
#define REG_MCU_TST_CFG_8822B 0x0084
#define REG_HMEBOX_E0_E1_8822B 0x0088
#define REG_HMEBOX_E2_E3_8822B 0x008C
#define REG_WLLPS_CTRL_8822B 0x0090
#define REG_AFE_CTRL5_8822B 0x0094
#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098
#define REG_RPWM2_8822B 0x009C
#define REG_SYSON_FSM_MON_8822B 0x00A0
#define REG_AFE_CTRL6_8822B 0x00A4
#define REG_PMC_DBG_CTRL1_8822B 0x00A8
#define REG_AFE_CTRL7_8822B 0x00AC
#define REG_HIMR0_8822B 0x00B0
#define REG_HISR0_8822B 0x00B4
#define REG_HIMR1_8822B 0x00B8
#define REG_HISR1_8822B 0x00BC
#define REG_DBG_PORT_SEL_8822B 0x00C0
#define REG_PAD_CTRL2_8822B 0x00C4
#define REG_PMC_DBG_CTRL2_8822B 0x00CC
#define REG_BIST_CTRL_8822B 0x00D0
#define REG_BIST_RPT_8822B 0x00D4
#define REG_MEM_CTRL_8822B 0x00D8
#define REG_AFE_CTRL8_8822B 0x00DC
#define REG_USB_SIE_INTF_8822B 0x00E0
#define REG_PCIE_MIO_INTF_8822B 0x00E4
#define REG_PCIE_MIO_INTD_8822B 0x00E8
#define REG_WLRF1_8822B 0x00EC
#define REG_SYS_CFG1_8822B 0x00F0
#define REG_SYS_STATUS1_8822B 0x00F4
#define REG_SYS_STATUS2_8822B 0x00F8
#define REG_SYS_CFG2_8822B 0x00FC
#define REG_SYS_CFG3_8822B 0x1000
#define REG_SYS_CFG4_8822B 0x1034
#define REG_SYS_CFG5_8822B 0x1070
#define REG_CPU_DMEM_CON_8822B 0x1080
#define REG_BOOT_REASON_8822B 0x1088
#define REG_NFCPAD_CTRL_8822B 0x10A8
#define REG_HIMR2_8822B 0x10B0
#define REG_HISR2_8822B 0x10B4
#define REG_HIMR3_8822B 0x10B8
#define REG_HISR3_8822B 0x10BC
#define REG_SW_MDIO_8822B 0x10C0
#define REG_SW_FLUSH_8822B 0x10C4
#define REG_H2C_PKT_READADDR_8822B 0x10D0
#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4
#define REG_MEM_PWR_CRTL_8822B 0x10D8
#define REG_FW_DBG0_8822B 0x10E0
#define REG_FW_DBG1_8822B 0x10E4
#define REG_FW_DBG2_8822B 0x10E8
#define REG_FW_DBG3_8822B 0x10EC
#define REG_FW_DBG4_8822B 0x10F0
#define REG_FW_DBG5_8822B 0x10F4
#define REG_FW_DBG6_8822B 0x10F8
#define REG_FW_DBG7_8822B 0x10FC
#define REG_CR_8822B 0x0100
#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106
#define REG_TSF_CLK_STATE_8822B 0x0108
#define REG_TXDMA_PQ_MAP_8822B 0x010C
#define REG_TRXFF_BNDY_8822B 0x0114
#define REG_PTA_I2C_MBOX_8822B 0x0118
#define REG_RXFF_BNDY_8822B 0x011C
#define REG_FE1IMR_8822B 0x0120
#define REG_FE1ISR_8822B 0x0124
#define REG_CPWM_8822B 0x012C
#define REG_FWIMR_8822B 0x0130
#define REG_FWISR_8822B 0x0134
#define REG_FTIMR_8822B 0x0138
#define REG_FTISR_8822B 0x013C
#define REG_PKTBUF_DBG_CTRL_8822B 0x0140
#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144
#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148
#define REG_CPWM2_8822B 0x014C
#define REG_TC0_CTRL_8822B 0x0150
#define REG_TC1_CTRL_8822B 0x0154
#define REG_TC2_CTRL_8822B 0x0158
#define REG_TC3_CTRL_8822B 0x015C
#define REG_TC4_CTRL_8822B 0x0160
#define REG_TCUNIT_BASE_8822B 0x0164
#define REG_TC5_CTRL_8822B 0x0168
#define REG_TC6_CTRL_8822B 0x016C
#define REG_MBIST_FAIL_8822B 0x0170
#define REG_MBIST_START_PAUSE_8822B 0x0174
#define REG_MBIST_DONE_8822B 0x0178
#define REG_MBIST_FAIL_NRML_8822B 0x017C
#define REG_AES_DECRPT_DATA_8822B 0x0180
#define REG_AES_DECRPT_CFG_8822B 0x0184
#define REG_TMETER_8822B 0x0190
#define REG_OSC_32K_CTRL_8822B 0x0194
#define REG_32K_CAL_REG1_8822B 0x0198
#define REG_C2HEVT_8822B 0x01A0
#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
#define REG_MCUTST_I_8822B 0x01C0
#define REG_MCUTST_II_8822B 0x01C4
#define REG_FMETHR_8822B 0x01C8
#define REG_HMETFR_8822B 0x01CC
#define REG_HMEBOX0_8822B 0x01D0
#define REG_HMEBOX1_8822B 0x01D4
#define REG_HMEBOX2_8822B 0x01D8
#define REG_HMEBOX3_8822B 0x01DC
#define REG_LLT_INIT_8822B 0x01E0
#define REG_LLT_INIT_ADDR_8822B 0x01E4
#define REG_BB_ACCESS_CTRL_8822B 0x01E8
#define REG_BB_ACCESS_DATA_8822B 0x01EC
#define REG_HMEBOX_E0_8822B 0x01F0
#define REG_HMEBOX_E1_8822B 0x01F4
#define REG_HMEBOX_E2_8822B 0x01F8
#define REG_HMEBOX_E3_8822B 0x01FC
#define REG_CR_EXT_8822B 0x1100
#define REG_FWFF_8822B 0x1114
#define REG_RXFF_PTR_V1_8822B 0x1118
#define REG_RXFF_WTR_V1_8822B 0x111C
#define REG_FE2IMR_8822B 0x1120
#define REG_FE2ISR_8822B 0x1124
#define REG_FE3IMR_8822B 0x1128
#define REG_FE3ISR_8822B 0x112C
#define REG_FE4IMR_8822B 0x1130
#define REG_FE4ISR_8822B 0x1134
#define REG_FT1IMR_8822B 0x1138
#define REG_FT1ISR_8822B 0x113C
#define REG_SPWR0_8822B 0x1140
#define REG_SPWR1_8822B 0x1144
#define REG_SPWR2_8822B 0x1148
#define REG_SPWR3_8822B 0x114C
#define REG_POWSEQ_8822B 0x1150
#define REG_TC7_CTRL_V1_8822B 0x1158
#define REG_TC8_CTRL_V1_8822B 0x115C
#define REG_FT2IMR_8822B 0x11E0
#define REG_FT2ISR_8822B 0x11E4
#define REG_MSG2_8822B 0x11F0
#define REG_MSG3_8822B 0x11F4
#define REG_MSG4_8822B 0x11F8
#define REG_MSG5_8822B 0x11FC
#define REG_FIFOPAGE_CTRL_1_8822B 0x0200
#define REG_FIFOPAGE_CTRL_2_8822B 0x0204
#define REG_AUTO_LLT_V1_8822B 0x0208
#define REG_TXDMA_OFFSET_CHK_8822B 0x020C
#define REG_TXDMA_STATUS_8822B 0x0210
#define REG_TX_DMA_DBG_8822B 0x0214
#define REG_TQPNT1_8822B 0x0218
#define REG_TQPNT2_8822B 0x021C
#define REG_TQPNT3_8822B 0x0220
#define REG_TQPNT4_8822B 0x0224
#define REG_RQPN_CTRL_1_8822B 0x0228
#define REG_RQPN_CTRL_2_8822B 0x022C
#define REG_FIFOPAGE_INFO_1_8822B 0x0230
#define REG_FIFOPAGE_INFO_2_8822B 0x0234
#define REG_FIFOPAGE_INFO_3_8822B 0x0238
#define REG_FIFOPAGE_INFO_4_8822B 0x023C
#define REG_FIFOPAGE_INFO_5_8822B 0x0240
#define REG_H2C_HEAD_8822B 0x0244
#define REG_H2C_TAIL_8822B 0x0248
#define REG_H2C_READ_ADDR_8822B 0x024C
#define REG_H2C_WR_ADDR_8822B 0x0250
#define REG_H2C_INFO_8822B 0x0254
#define REG_RXDMA_AGG_PG_TH_8822B 0x0280
#define REG_RXPKT_NUM_8822B 0x0284
#define REG_RXDMA_STATUS_8822B 0x0288
#define REG_RXDMA_DPR_8822B 0x028C
#define REG_RXDMA_MODE_8822B 0x0290
#define REG_C2H_PKT_8822B 0x0294
#define REG_FWFF_C2H_8822B 0x0298
#define REG_FWFF_CTRL_8822B 0x029C
#define REG_FWFF_PKT_INFO_8822B 0x02A0
#define REG_DDMA_CH0SA_8822B 0x1200
#define REG_DDMA_CH0DA_8822B 0x1204
#define REG_DDMA_CH0CTRL_8822B 0x1208
#define REG_DDMA_CH1SA_8822B 0x1210
#define REG_DDMA_CH1DA_8822B 0x1214
#define REG_DDMA_CH1CTRL_8822B 0x1218
#define REG_DDMA_CH2SA_8822B 0x1220
#define REG_DDMA_CH2DA_8822B 0x1224
#define REG_DDMA_CH2CTRL_8822B 0x1228
#define REG_DDMA_CH3SA_8822B 0x1230
#define REG_DDMA_CH3DA_8822B 0x1234
#define REG_DDMA_CH3CTRL_8822B 0x1238
#define REG_DDMA_CH4SA_8822B 0x1240
#define REG_DDMA_CH4DA_8822B 0x1244
#define REG_DDMA_CH4CTRL_8822B 0x1248
#define REG_DDMA_CH5SA_8822B 0x1250
#define REG_DDMA_CH5DA_8822B 0x1254
#define REG_REG_DDMA_CH5CTRL_8822B 0x1258
#define REG_DDMA_INT_MSK_8822B 0x12E0
#define REG_DDMA_CHSTATUS_8822B 0x12E8
#define REG_DDMA_CHKSUM_8822B 0x12F0
#define REG_DDMA_MONITOR_8822B 0x12FC
#define REG_PCIE_CTRL_8822B 0x0300
#define REG_INT_MIG_8822B 0x0304
#define REG_BCNQ_TXBD_DESA_8822B 0x0308
#define REG_MGQ_TXBD_DESA_8822B 0x0310
#define REG_VOQ_TXBD_DESA_8822B 0x0318
#define REG_VIQ_TXBD_DESA_8822B 0x0320
#define REG_BEQ_TXBD_DESA_8822B 0x0328
#define REG_BKQ_TXBD_DESA_8822B 0x0330
#define REG_RXQ_RXBD_DESA_8822B 0x0338
#define REG_HI0Q_TXBD_DESA_8822B 0x0340
#define REG_HI1Q_TXBD_DESA_8822B 0x0348
#define REG_HI2Q_TXBD_DESA_8822B 0x0350
#define REG_HI3Q_TXBD_DESA_8822B 0x0358
#define REG_HI4Q_TXBD_DESA_8822B 0x0360
#define REG_HI5Q_TXBD_DESA_8822B 0x0368
#define REG_HI6Q_TXBD_DESA_8822B 0x0370
#define REG_HI7Q_TXBD_DESA_8822B 0x0378
#define REG_MGQ_TXBD_NUM_8822B 0x0380
#define REG_RX_RXBD_NUM_8822B 0x0382
#define REG_VOQ_TXBD_NUM_8822B 0x0384
#define REG_VIQ_TXBD_NUM_8822B 0x0386
#define REG_BEQ_TXBD_NUM_8822B 0x0388
#define REG_BKQ_TXBD_NUM_8822B 0x038A
#define REG_HI0Q_TXBD_NUM_8822B 0x038C
#define REG_HI1Q_TXBD_NUM_8822B 0x038E
#define REG_HI2Q_TXBD_NUM_8822B 0x0390
#define REG_HI3Q_TXBD_NUM_8822B 0x0392
#define REG_HI4Q_TXBD_NUM_8822B 0x0394
#define REG_HI5Q_TXBD_NUM_8822B 0x0396
#define REG_HI6Q_TXBD_NUM_8822B 0x0398
#define REG_HI7Q_TXBD_NUM_8822B 0x039A
#define REG_TSFTIMER_HCI_8822B 0x039C
#define REG_BD_RWPTR_CLR_8822B 0x039C
#define REG_VOQ_TXBD_IDX_8822B 0x03A0
#define REG_VIQ_TXBD_IDX_8822B 0x03A4
#define REG_BEQ_TXBD_IDX_8822B 0x03A8
#define REG_BKQ_TXBD_IDX_8822B 0x03AC
#define REG_MGQ_TXBD_IDX_8822B 0x03B0
#define REG_RXQ_RXBD_IDX_8822B 0x03B4
#define REG_HI0Q_TXBD_IDX_8822B 0x03B8
#define REG_HI1Q_TXBD_IDX_8822B 0x03BC
#define REG_HI2Q_TXBD_IDX_8822B 0x03C0
#define REG_HI3Q_TXBD_IDX_8822B 0x03C4
#define REG_HI4Q_TXBD_IDX_8822B 0x03C8
#define REG_HI5Q_TXBD_IDX_8822B 0x03CC
#define REG_HI6Q_TXBD_IDX_8822B 0x03D0
#define REG_HI7Q_TXBD_IDX_8822B 0x03D4
#define REG_DBG_SEL_V1_8822B 0x03D8
#define REG_PCIE_HRPWM1_V1_8822B 0x03D9
#define REG_PCIE_HCPWM1_V1_8822B 0x03DA
#define REG_PCIE_CTRL2_8822B 0x03DB
#define REG_PCIE_HRPWM2_V1_8822B 0x03DC
#define REG_PCIE_HCPWM2_V1_8822B 0x03DE
#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0
#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4
#define REG_DBI_WDATA_V1_8822B 0x03E8
#define REG_DBI_RDATA_V1_8822B 0x03EC
#define REG_DBI_FLAG_V1_8822B 0x03F0
#define REG_MDIO_V1_8822B 0x03F4
#define REG_PCIE_MIX_CFG_8822B 0x03F8
#define REG_HCI_MIX_CFG_8822B 0x03FC
#define REG_STC_INT_CS_8822B 0x1300
#define REG_ST_INT_CFG_8822B 0x1304
#define REG_CMU_DLY_CTRL_8822B 0x1310
#define REG_CMU_DLY_CFG_8822B 0x1314
#define REG_H2CQ_TXBD_DESA_8822B 0x1320
#define REG_H2CQ_TXBD_NUM_8822B 0x1328
#define REG_H2CQ_TXBD_IDX_8822B 0x132C
#define REG_H2CQ_CSR_8822B 0x1330
#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
#define REG_OLD_DEHANG_8822B 0x13F4
#define REG_Q0_INFO_8822B 0x0400
#define REG_Q1_INFO_8822B 0x0404
#define REG_Q2_INFO_8822B 0x0408
#define REG_Q3_INFO_8822B 0x040C
#define REG_MGQ_INFO_8822B 0x0410
#define REG_HIQ_INFO_8822B 0x0414
#define REG_BCNQ_INFO_8822B 0x0418
#define REG_TXPKT_EMPTY_8822B 0x041A
#define REG_CPU_MGQ_INFO_8822B 0x041C
#define REG_FWHW_TXQ_CTRL_8822B 0x0420
#define REG_DATAFB_SEL_8822B 0x0423
#define REG_BCNQ_BDNY_V1_8822B 0x0424
#define REG_LIFETIME_EN_8822B 0x0426
#define REG_SPEC_SIFS_8822B 0x0428
#define REG_RETRY_LIMIT_8822B 0x042A
#define REG_TXBF_CTRL_8822B 0x042C
#define REG_DARFRC_8822B 0x0430
#define REG_RARFRC_8822B 0x0438
#define REG_RRSR_8822B 0x0440
#define REG_ARFR0_8822B 0x0444
#define REG_ARFR1_V1_8822B 0x044C
#define REG_CCK_CHECK_8822B 0x0454
#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455
#define REG_BCNQ1_BDNY_V1_8822B 0x0456
#define REG_AMPDU_MAX_LENGTH_8822B 0x0458
#define REG_ACQ_STOP_8822B 0x045C
#define REG_NDPA_RATE_8822B 0x045D
#define REG_TX_HANG_CTRL_8822B 0x045E
#define REG_NDPA_OPT_CTRL_8822B 0x045F
#define REG_RD_RESP_PKT_TH_8822B 0x0463
#define REG_CMDQ_INFO_8822B 0x0464
#define REG_Q4_INFO_8822B 0x0468
#define REG_Q5_INFO_8822B 0x046C
#define REG_Q6_INFO_8822B 0x0470
#define REG_Q7_INFO_8822B 0x0474
#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478
#define REG_MGQ_BDNY_V1_8822B 0x047A
#define REG_TXRPT_CTRL_8822B 0x047C
#define REG_INIRTS_RATE_SEL_8822B 0x0480
#define REG_BASIC_CFEND_RATE_8822B 0x0481
#define REG_STBC_CFEND_RATE_8822B 0x0482
#define REG_DATA_SC_8822B 0x0483
#define REG_MACID_SLEEP3_8822B 0x0484
#define REG_MACID_SLEEP1_8822B 0x0488
#define REG_ARFR2_V1_8822B 0x048C
#define REG_ARFR3_V1_8822B 0x0494
#define REG_ARFR4_8822B 0x049C
#define REG_ARFR5_8822B 0x04A4
#define REG_TXRPT_START_OFFSET_8822B 0x04AC
#define REG_POWER_STAGE1_8822B 0x04B4
#define REG_POWER_STAGE2_8822B 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC
#define REG_PKT_LIFE_TIME_8822B 0x04C0
#define REG_STBC_SETTING_8822B 0x04C4
#define REG_STBC_SETTING2_8822B 0x04C5
#define REG_QUEUE_CTRL_8822B 0x04C6
#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7
#define REG_PROT_MODE_CTRL_8822B 0x04C8
#define REG_BAR_MODE_CTRL_8822B 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF
#define REG_MACID_SLEEP2_8822B 0x04D0
#define REG_MACID_SLEEP_8822B 0x04D4
#define REG_HW_SEQ0_8822B 0x04D8
#define REG_HW_SEQ1_8822B 0x04DA
#define REG_HW_SEQ2_8822B 0x04DC
#define REG_HW_SEQ3_8822B 0x04DE
#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0
#define REG_PTCL_ERR_STATUS_8822B 0x04E2
#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3
#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4
#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8
#define REG_PTCL_DBG_8822B 0x04EC
#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4
#define REG_DUMMY_PAGE4_V1_8822B 0x04FC
#define REG_MOREDATA_8822B 0x04FE
#define REG_Q0_Q1_INFO_8822B 0x1400
#define REG_Q2_Q3_INFO_8822B 0x1404
#define REG_Q4_Q5_INFO_8822B 0x1408
#define REG_Q6_Q7_INFO_8822B 0x140C
#define REG_MGQ_HIQ_INFO_8822B 0x1410
#define REG_CMDQ_BCNQ_INFO_8822B 0x1414
#define REG_USEREG_SETTING_8822B 0x1420
#define REG_AESIV_SETTING_8822B 0x1424
#define REG_BF0_TIME_SETTING_8822B 0x1428
#define REG_BF1_TIME_SETTING_8822B 0x142C
#define REG_BF_TIMEOUT_EN_8822B 0x1430
#define REG_MACID_RELEASE0_8822B 0x1434
#define REG_MACID_RELEASE1_8822B 0x1438
#define REG_MACID_RELEASE2_8822B 0x143C
#define REG_MACID_RELEASE3_8822B 0x1440
#define REG_MACID_RELEASE_SETTING_8822B 0x1444
#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448
#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C
#define REG_MACID_DROP0_8822B 0x1450
#define REG_MACID_DROP1_8822B 0x1454
#define REG_MACID_DROP2_8822B 0x1458
#define REG_MACID_DROP3_8822B 0x145C
#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460
#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C
#define REG_MGG_FIFO_CRTL_8822B 0x1470
#define REG_MGG_FIFO_INT_8822B 0x1474
#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
#define REG_MACID_SHCUT_OFFSET_8822B 0x1480
#define REG_MU_TX_CTL_8822B 0x14C0
#define REG_MU_STA_GID_VLD_8822B 0x14C4
#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
#define REG_EDCA_VO_PARAM_8822B 0x0500
#define REG_EDCA_VI_PARAM_8822B 0x0504
#define REG_EDCA_BE_PARAM_8822B 0x0508
#define REG_EDCA_BK_PARAM_8822B 0x050C
#define REG_BCNTCFG_8822B 0x0510
#define REG_PIFS_8822B 0x0512
#define REG_RDG_PIFS_8822B 0x0513
#define REG_SIFS_8822B 0x0514
#define REG_TSFTR_SYN_OFFSET_8822B 0x0518
#define REG_AGGR_BREAK_TIME_8822B 0x051A
#define REG_SLOT_8822B 0x051B
#define REG_TX_PTCL_CTRL_8822B 0x0520
#define REG_TXPAUSE_8822B 0x0522
#define REG_DIS_TXREQ_CLR_8822B 0x0523
#define REG_RD_CTRL_8822B 0x0524
#define REG_MBSSID_CTRL_8822B 0x0526
#define REG_P2PPS_CTRL_8822B 0x0527
#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
#define REG_P2PPS_SPEC_STATE_8822B 0x052B
#define REG_BAR_TX_CTRL_8822B 0x0530
#define REG_QUEUE_INCOL_THR_8822B 0x0538
#define REG_QUEUE_INCOL_EN_8822B 0x053C
#define REG_TBTT_PROHIBIT_8822B 0x0540
#define REG_P2PPS_STATE_8822B 0x0543
#define REG_RD_NAV_NXT_8822B 0x0544
#define REG_NAV_PROT_LEN_8822B 0x0546
#define REG_BCN_CTRL_8822B 0x0550
#define REG_BCN_CTRL_CLINT0_8822B 0x0551
#define REG_MBID_NUM_8822B 0x0552
#define REG_DUAL_TSF_RST_8822B 0x0553
#define REG_MBSSID_BCN_SPACE_8822B 0x0554
#define REG_DRVERLYINT_8822B 0x0558
#define REG_BCNDMATIM_8822B 0x0559
#define REG_ATIMWND_8822B 0x055A
#define REG_USTIME_TSF_8822B 0x055C
#define REG_BCN_MAX_ERR_8822B 0x055D
#define REG_RXTSF_OFFSET_CCK_8822B 0x055E
#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F
#define REG_TSFTR_8822B 0x0560
#define REG_FREERUN_CNT_8822B 0x0568
#define REG_ATIMWND1_V1_8822B 0x0570
#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571
#define REG_CTWND_8822B 0x0572
#define REG_BCNIVLCUNT_8822B 0x0573
#define REG_BCNDROPCTRL_8822B 0x0574
#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576
#define REG_MISC_CTRL_8822B 0x0577
#define REG_BCN_CTRL_CLINT1_8822B 0x0578
#define REG_BCN_CTRL_CLINT2_8822B 0x0579
#define REG_BCN_CTRL_CLINT3_8822B 0x057A
#define REG_EXTEND_CTRL_8822B 0x057B
#define REG_P2PPS1_SPEC_STATE_8822B 0x057C
#define REG_P2PPS1_STATE_8822B 0x057D
#define REG_P2PPS2_SPEC_STATE_8822B 0x057E
#define REG_P2PPS2_STATE_8822B 0x057F
#define REG_PS_TIMER0_8822B 0x0580
#define REG_PS_TIMER1_8822B 0x0584
#define REG_PS_TIMER2_8822B 0x0588
#define REG_TBTT_CTN_AREA_8822B 0x058C
#define REG_FORCE_BCN_IFS_8822B 0x058E
#define REG_TXOP_MIN_8822B 0x0590
#define REG_PRE_BKF_TIME_8822B 0x0592
#define REG_CROSS_TXOP_CTRL_8822B 0x0593
#define REG_ATIMWND2_8822B 0x05A0
#define REG_ATIMWND3_8822B 0x05A1
#define REG_ATIMWND4_8822B 0x05A2
#define REG_ATIMWND5_8822B 0x05A3
#define REG_ATIMWND6_8822B 0x05A4
#define REG_ATIMWND7_8822B 0x05A5
#define REG_ATIMUGT_8822B 0x05A6
#define REG_HIQ_NO_LMT_EN_8822B 0x05A7
#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8
#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9
#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA
#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB
#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC
#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD
#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE
#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF
#define REG_DIS_ATIM_8822B 0x05B0
#define REG_EARLY_128US_8822B 0x05B1
#define REG_P2PPS1_CTRL_8822B 0x05B2
#define REG_P2PPS2_CTRL_8822B 0x05B3
#define REG_TIMER0_SRC_SEL_8822B 0x05B4
#define REG_NOA_UNIT_SEL_8822B 0x05B5
#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7
#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8
#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC
#define REG_ACMHWCTRL_8822B 0x05C0
#define REG_ACMRSTCTRL_8822B 0x05C1
#define REG_ACMAVG_8822B 0x05C2
#define REG_VO_ADMTIME_8822B 0x05C4
#define REG_VI_ADMTIME_8822B 0x05C6
#define REG_BE_ADMTIME_8822B 0x05C8
#define REG_EDCA_RANDOM_GEN_8822B 0x05CC
#define REG_TXCMD_NOA_SEL_8822B 0x05CF
#define REG_NOA_PARAM_8822B 0x05E0
#define REG_P2P_RST_8822B 0x05F0
#define REG_SCHEDULER_RST_8822B 0x05F1
#define REG_SCH_TXCMD_8822B 0x05F8
#define REG_PAGE5_DUMMY_8822B 0x05FC
#define REG_CPUMGQ_TX_TIMER_8822B 0x1500
#define REG_PS_TIMER_A_8822B 0x1504
#define REG_PS_TIMER_B_8822B 0x1508
#define REG_PS_TIMER_C_8822B 0x150C
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510
#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514
#define REG_PS_TIMER_A_EARLY_8822B 0x1515
#define REG_PS_TIMER_B_EARLY_8822B 0x1516
#define REG_PS_TIMER_C_EARLY_8822B 0x1517
#define REG_WMAC_CR_8822B 0x0600
#define REG_WMAC_FWPKT_CR_8822B 0x0601
#define REG_BWOPMODE_8822B 0x0603
#define REG_TCR_8822B 0x0604
#define REG_RCR_8822B 0x0608
#define REG_RX_PKT_LIMIT_8822B 0x060C
#define REG_RX_DLK_TIME_8822B 0x060D
#define REG_RX_DRVINFO_SZ_8822B 0x060F
#define REG_MACID_8822B 0x0610
#define REG_BSSID_8822B 0x0618
#define REG_MAR_8822B 0x0620
#define REG_MBIDCAMCFG_1_8822B 0x0628
#define REG_MBIDCAMCFG_2_8822B 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630
#define REG_UDF_THSD_8822B 0x0632
#define REG_ZLD_NUM_8822B 0x0633
#define REG_STMP_THSD_8822B 0x0634
#define REG_WMAC_TXTIMEOUT_8822B 0x0635
#define REG_MCU_TEST_2_V1_8822B 0x0636
#define REG_USTIME_EDCA_8822B 0x0638
#define REG_MAC_SPEC_SIFS_8822B 0x063A
#define REG_RESP_SIFS_CCK_8822B 0x063C
#define REG_RESP_SIFS_OFDM_8822B 0x063E
#define REG_ACKTO_8822B 0x0640
#define REG_CTS2TO_8822B 0x0641
#define REG_EIFS_8822B 0x0642
#define REG_NAV_CTRL_8822B 0x0650
#define REG_BACAMCMD_8822B 0x0654
#define REG_BACAMCONTENT_8822B 0x0658
#define REG_LBDLY_8822B 0x0660
#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
#define REG_TX_RX_8822B 0x0662
#define REG_WMAC_BITMAP_CTL_8822B 0x0663
#define REG_RXERR_RPT_8822B 0x0664
#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
#define REG_CAMCMD_8822B 0x0670
#define REG_CAMWRITE_8822B 0x0674
#define REG_CAMREAD_8822B 0x0678
#define REG_CAMDBG_8822B 0x067C
#define REG_SECCFG_8822B 0x0680
#define REG_RXFILTER_CATEGORY_1_8822B 0x0682
#define REG_RXFILTER_ACTION_1_8822B 0x0683
#define REG_RXFILTER_CATEGORY_2_8822B 0x0684
#define REG_RXFILTER_ACTION_2_8822B 0x0685
#define REG_RXFILTER_CATEGORY_3_8822B 0x0686
#define REG_RXFILTER_ACTION_3_8822B 0x0687
#define REG_RXFLTMAP3_8822B 0x0688
#define REG_RXFLTMAP4_8822B 0x068A
#define REG_RXFLTMAP5_8822B 0x068C
#define REG_RXFLTMAP6_8822B 0x068E
#define REG_WOW_CTRL_8822B 0x0690
#define REG_NAN_RX_TSF_FILTER_8822B 0x0691
#define REG_PS_RX_INFO_8822B 0x0692
#define REG_WMMPS_UAPSD_TID_8822B 0x0693
#define REG_LPNAV_CTRL_8822B 0x0694
#define REG_WKFMCAM_CMD_8822B 0x0698
#define REG_WKFMCAM_RWD_8822B 0x069C
#define REG_RXFLTMAP0_8822B 0x06A0
#define REG_RXFLTMAP1_8822B 0x06A2
#define REG_RXFLTMAP_8822B 0x06A4
#define REG_BCN_PSR_RPT_8822B 0x06A8
#define REG_FLC_RPC_8822B 0x06AC
#define REG_FLC_RPCT_8822B 0x06AD
#define REG_FLC_PTS_8822B 0x06AE
#define REG_FLC_TRPC_8822B 0x06AF
#define REG_RXPKTMON_CTRL_8822B 0x06B0
#define REG_STATE_MON_8822B 0x06B4
#define REG_ERROR_MON_8822B 0x06B8
#define REG_SEARCH_MACID_8822B 0x06BC
#define REG_BT_COEX_TABLE_8822B 0x06C0
#define REG_RXCMD_0_8822B 0x06D0
#define REG_RXCMD_1_8822B 0x06D4
#define REG_WMAC_RESP_TXINFO_8822B 0x06D8
#define REG_BBPSF_CTRL_8822B 0x06DC
#define REG_P2P_RX_BCN_NOA_8822B 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4
#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC
#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8
#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC
#define REG_BCN_PSR_RPT2_8822B 0x1600
#define REG_BCN_PSR_RPT3_8822B 0x1604
#define REG_BCN_PSR_RPT4_8822B 0x1608
#define REG_A1_ADDR_MASK_8822B 0x160C
#define REG_MACID2_8822B 0x1620
#define REG_BSSID2_8822B 0x1628
#define REG_MACID3_8822B 0x1630
#define REG_BSSID3_8822B 0x1638
#define REG_MACID4_8822B 0x1640
#define REG_BSSID4_8822B 0x1648
#define REG_NOA_REPORT_8822B 0x1650
#define REG_PWRBIT_SETTING_8822B 0x1660
#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
#define REG_WMAC_MU_ARB_8822B 0x167E
#define REG_WMAC_MU_OPTION_8822B 0x167F
#define REG_WMAC_MU_BF_CTL_8822B 0x1680
#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8
#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0
#define REG_MACID1_8822B 0x0700
#define REG_BSSID1_8822B 0x0708
#define REG_BCN_PSR_RPT1_8822B 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714
#define REG_SND_PTCL_CTRL_8822B 0x0718
#define REG_RX_CSI_RPT_INFO_8822B 0x071C
#define REG_NS_ARP_CTRL_8822B 0x0720
#define REG_NS_ARP_INFO_8822B 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728
#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750
#define REG_WMAC_SWAES_CFG_8822B 0x0760
#define REG_BT_COEX_V2_8822B 0x0762
#define REG_BT_COEX_8822B 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E
#define REG_BT_ACT_STATISTICS_8822B 0x0770
#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785
#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790
#define REG_BT_ACT_REGISTER_8822B 0x0794
#define REG_OBFF_CTRL_BASIC_8822B 0x0798
#define REG_OBFF_CTRL2_TIMER_8822B 0x079C
#define REG_LTR_CTRL_BASIC_8822B 0x07A0
#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0
#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8
#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC
#define REG_IQ_DUMP_8822B 0x07C0
#define REG_WMAC_FTM_CTL_8822B 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE
#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0
#define REG_RX_FILTER_FUNCTION_8822B 0x07DA
#define REG_NDP_SIG_8822B 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4
#define REG_RTS_ADDRESS_0_8822B 0x07F0
#define REG_RTS_ADDRESS_1_8822B 0x07F8
#define REG__RPFM_MAP1_8822B 0x07FE
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708
#define REG_SDIO_TX_CTRL_8822B 0x10250000
#define REG_SDIO_HIMR_8822B 0x10250014
#define REG_SDIO_HISR_8822B 0x10250018
#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C
#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F
#define REG_SDIO_FREE_TXPG_8822B 0x10250020
#define REG_SDIO_FREE_TXPG2_8822B 0x10250024
#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028
#define REG_SDIO_HTSFR_INFO_8822B 0x10250030
#define REG_SDIO_HCPWM1_V2_8822B 0x10250038
#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A
#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040
#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044
#define REG_SDIO_H2C_8822B 0x10250060
#define REG_SDIO_C2H_8822B 0x10250064
#define REG_SDIO_HRPWM1_8822B 0x10250080
#define REG_SDIO_HRPWM2_8822B 0x10250082
#define REG_SDIO_HPS_CLKR_8822B 0x10250084
#define REG_SDIO_BUS_CTRL_8822B 0x10250085
#define REG_SDIO_HSUS_CTRL_8822B 0x10250086
#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
#define REG_SDIO_CMD_CRC_8822B 0x1025008A
#define REG_SDIO_HSISR_8822B 0x10250090
#define REG_SDIO_HSIMR_8822B 0x10250091
#define REG_SDIO_ERR_RPT_8822B 0x102500C0
#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1
#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2
#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
#define REG_SDIO_DATA_CRC_8822B 0x102500CA
#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB
#endif

37
drivers/staging/rtlwifi/halmac/halmac_rx_bd_chip.h
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@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_BD_CHIP_H_
#define _HALMAC_RX_BD_CHIP_H_
/*TXBD_DW0*/
#define GET_RX_BD_RXFAIL_8822B(__rx_bd) GET_RX_BD_RXFAIL(__rx_bd)
#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__rx_bd) \
GET_RX_BD_TOTALRXPKTSIZE(__rx_bd)
#define GET_RX_BD_RXTAG_8822B(__rx_bd) GET_RX_BD_RXTAG(__rx_bd)
#define GET_RX_BD_FS_8822B(__rx_bd) GET_RX_BD_FS(__rx_bd)
#define GET_RX_BD_LS_8822B(__rx_bd) GET_RX_BD_LS(__rx_bd)
#define GET_RX_BD_RXBUFFSIZE_8822B(__rx_bd) GET_RX_BD_RXBUFFSIZE(__rx_bd)
/*TXBD_DW1*/
#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__rx_bd) \
GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd)
/*TXBD_DW2*/
#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__rx_bd) \
GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd)
#endif

37
drivers/staging/rtlwifi/halmac/halmac_rx_bd_nic.h
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@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_BD_NIC_H_
#define _HALMAC_RX_BD_NIC_H_
/*TXBD_DW0*/
#define GET_RX_BD_RXFAIL(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 31, 1)
#define GET_RX_BD_TOTALRXPKTSIZE(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
#define GET_RX_BD_RXTAG(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
#define GET_RX_BD_FS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 15, 1)
#define GET_RX_BD_LS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 14, 1)
#define GET_RX_BD_RXBUFFSIZE(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 0, 14)
/*TXBD_DW1*/
#define GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x04, 0, 32)
/*TXBD_DW2*/
#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x08, 0, 32)
#endif

107
drivers/staging/rtlwifi/halmac/halmac_rx_desc_chip.h
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@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_DESC_CHIP_H_
#define _HALMAC_RX_DESC_CHIP_H_
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR_8822B(__rx_desc) GET_RX_DESC_EOR(__rx_desc)
#define GET_RX_DESC_PHYPKTIDC_8822B(__rx_desc) GET_RX_DESC_PHYPKTIDC(__rx_desc)
#define GET_RX_DESC_SWDEC_8822B(__rx_desc) GET_RX_DESC_SWDEC(__rx_desc)
#define GET_RX_DESC_PHYST_8822B(__rx_desc) GET_RX_DESC_PHYST(__rx_desc)
#define GET_RX_DESC_SHIFT_8822B(__rx_desc) GET_RX_DESC_SHIFT(__rx_desc)
#define GET_RX_DESC_QOS_8822B(__rx_desc) GET_RX_DESC_QOS(__rx_desc)
#define GET_RX_DESC_SECURITY_8822B(__rx_desc) GET_RX_DESC_SECURITY(__rx_desc)
#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__rx_desc) \
GET_RX_DESC_DRV_INFO_SIZE(__rx_desc)
#define GET_RX_DESC_ICV_ERR_8822B(__rx_desc) GET_RX_DESC_ICV_ERR(__rx_desc)
#define GET_RX_DESC_CRC32_8822B(__rx_desc) GET_RX_DESC_CRC32(__rx_desc)
#define GET_RX_DESC_PKT_LEN_8822B(__rx_desc) GET_RX_DESC_PKT_LEN(__rx_desc)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC_8822B(__rx_desc) GET_RX_DESC_BC(__rx_desc)
#define GET_RX_DESC_MC_8822B(__rx_desc) GET_RX_DESC_MC(__rx_desc)
#define GET_RX_DESC_TY_PE_8822B(__rx_desc) GET_RX_DESC_TY_PE(__rx_desc)
#define GET_RX_DESC_MF_8822B(__rx_desc) GET_RX_DESC_MF(__rx_desc)
#define GET_RX_DESC_MD_8822B(__rx_desc) GET_RX_DESC_MD(__rx_desc)
#define GET_RX_DESC_PWR_8822B(__rx_desc) GET_RX_DESC_PWR(__rx_desc)
#define GET_RX_DESC_PAM_8822B(__rx_desc) GET_RX_DESC_PAM(__rx_desc)
#define GET_RX_DESC_CHK_VLD_8822B(__rx_desc) GET_RX_DESC_CHK_VLD(__rx_desc)
#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__rx_desc) \
GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc)
#define GET_RX_DESC_RX_IPV_8822B(__rx_desc) GET_RX_DESC_RX_IPV(__rx_desc)
#define GET_RX_DESC_CHKERR_8822B(__rx_desc) GET_RX_DESC_CHKERR(__rx_desc)
#define GET_RX_DESC_PAGGR_8822B(__rx_desc) GET_RX_DESC_PAGGR(__rx_desc)
#define GET_RX_DESC_RXID_MATCH_8822B(__rx_desc) \
GET_RX_DESC_RXID_MATCH(__rx_desc)
#define GET_RX_DESC_AMSDU_8822B(__rx_desc) GET_RX_DESC_AMSDU(__rx_desc)
#define GET_RX_DESC_MACID_VLD_8822B(__rx_desc) GET_RX_DESC_MACID_VLD(__rx_desc)
#define GET_RX_DESC_TID_8822B(__rx_desc) GET_RX_DESC_TID(__rx_desc)
#define GET_RX_DESC_EXT_SECTYPE_8822B(__rx_desc) \
GET_RX_DESC_EXT_SECTYPE(__rx_desc)
#define GET_RX_DESC_MACID_8822B(__rx_desc) GET_RX_DESC_MACID(__rx_desc)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK_8822B(__rx_desc) GET_RX_DESC_FCS_OK(__rx_desc)
#define GET_RX_DESC_PPDU_CNT_8822B(__rx_desc) GET_RX_DESC_PPDU_CNT(__rx_desc)
#define GET_RX_DESC_C2H_8822B(__rx_desc) GET_RX_DESC_C2H(__rx_desc)
#define GET_RX_DESC_HWRSVD_8822B(__rx_desc) GET_RX_DESC_HWRSVD(__rx_desc)
#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__rx_desc) \
GET_RX_DESC_WLANHD_IV_LEN(__rx_desc)
#define GET_RX_DESC_RX_IS_QOS_8822B(__rx_desc) GET_RX_DESC_RX_IS_QOS(__rx_desc)
#define GET_RX_DESC_FRAG_8822B(__rx_desc) GET_RX_DESC_FRAG(__rx_desc)
#define GET_RX_DESC_SEQ_8822B(__rx_desc) GET_RX_DESC_SEQ(__rx_desc)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE_8822B(__rx_desc) \
GET_RX_DESC_MAGIC_WAKE(__rx_desc)
#define GET_RX_DESC_UNICAST_WAKE_8822B(__rx_desc) \
GET_RX_DESC_UNICAST_WAKE(__rx_desc)
#define GET_RX_DESC_PATTERN_MATCH_8822B(__rx_desc) \
GET_RX_DESC_PATTERN_MATCH(__rx_desc)
#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__rx_desc) \
GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc)
#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__rx_desc) \
GET_RX_DESC_RXPAYLOAD_ID(__rx_desc)
#define GET_RX_DESC_DMA_AGG_NUM_8822B(__rx_desc) \
GET_RX_DESC_DMA_AGG_NUM(__rx_desc)
#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__rx_desc) \
GET_RX_DESC_BSSID_FIT_1_0(__rx_desc)
#define GET_RX_DESC_EOSP_8822B(__rx_desc) GET_RX_DESC_EOSP(__rx_desc)
#define GET_RX_DESC_HTC_8822B(__rx_desc) GET_RX_DESC_HTC(__rx_desc)
#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__rx_desc) \
GET_RX_DESC_BSSID_FIT_4_2(__rx_desc)
#define GET_RX_DESC_RX_RATE_8822B(__rx_desc) GET_RX_DESC_RX_RATE(__rx_desc)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT_8822B(__rx_desc) GET_RX_DESC_A1_FIT(__rx_desc)
#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__rx_desc) \
GET_RX_DESC_MACID_RPT_BUFF(__rx_desc)
#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__rx_desc) \
GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc)
#define GET_RX_DESC_RX_SCRAMBLER_8822B(__rx_desc) \
GET_RX_DESC_RX_SCRAMBLER(__rx_desc)
#define GET_RX_DESC_RX_EOF_8822B(__rx_desc) GET_RX_DESC_RX_EOF(__rx_desc)
#define GET_RX_DESC_PATTERN_IDX_8822B(__rx_desc) \
GET_RX_DESC_PATTERN_IDX(__rx_desc)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL_8822B(__rx_desc) GET_RX_DESC_TSFL(__rx_desc)
#endif

122
drivers/staging/rtlwifi/halmac/halmac_rx_desc_nic.h
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@ -1,122 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_DESC_NIC_H_
#define _HALMAC_RX_DESC_NIC_H_
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 30, 1)
#define GET_RX_DESC_PHYPKTIDC(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 28, 1)
#define GET_RX_DESC_SWDEC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 27, 1)
#define GET_RX_DESC_PHYST(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 26, 1)
#define GET_RX_DESC_SHIFT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 24, 2)
#define GET_RX_DESC_QOS(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 23, 1)
#define GET_RX_DESC_SECURITY(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 20, 3)
#define GET_RX_DESC_DRV_INFO_SIZE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 16, 4)
#define GET_RX_DESC_ICV_ERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 15, 1)
#define GET_RX_DESC_CRC32(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 14, 1)
#define GET_RX_DESC_PKT_LEN(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 0, 14)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 31, 1)
#define GET_RX_DESC_MC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 30, 1)
#define GET_RX_DESC_TY_PE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 28, 2)
#define GET_RX_DESC_MF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 27, 1)
#define GET_RX_DESC_MD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 26, 1)
#define GET_RX_DESC_PWR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 25, 1)
#define GET_RX_DESC_PAM(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 24, 1)
#define GET_RX_DESC_CHK_VLD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 23, 1)
#define GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 22, 1)
#define GET_RX_DESC_RX_IPV(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 21, 1)
#define GET_RX_DESC_CHKERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 20, 1)
#define GET_RX_DESC_PAGGR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 15, 1)
#define GET_RX_DESC_RXID_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 14, 1)
#define GET_RX_DESC_AMSDU(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 13, 1)
#define GET_RX_DESC_MACID_VLD(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 12, 1)
#define GET_RX_DESC_TID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 8, 4)
#define GET_RX_DESC_EXT_SECTYPE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 7, 1)
#define GET_RX_DESC_MACID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 0, 7)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 31, 1)
#define GET_RX_DESC_PPDU_CNT(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 29, 2)
#define GET_RX_DESC_C2H(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 28, 1)
#define GET_RX_DESC_HWRSVD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 24, 4)
#define GET_RX_DESC_WLANHD_IV_LEN(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 18, 6)
#define GET_RX_DESC_RX_IS_QOS(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 16, 1)
#define GET_RX_DESC_FRAG(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 12, 4)
#define GET_RX_DESC_SEQ(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 0, 12)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 31, 1)
#define GET_RX_DESC_UNICAST_WAKE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 30, 1)
#define GET_RX_DESC_PATTERN_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 29, 1)
#define GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 28, 1)
#define GET_RX_DESC_RXPAYLOAD_ID(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 24, 4)
#define GET_RX_DESC_DMA_AGG_NUM(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 16, 8)
#define GET_RX_DESC_BSSID_FIT_1_0(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 12, 2)
#define GET_RX_DESC_EOSP(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 11, 1)
#define GET_RX_DESC_HTC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 10, 1)
#define GET_RX_DESC_BSSID_FIT_4_2(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 7, 3)
#define GET_RX_DESC_RX_RATE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 0, 7)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 24, 5)
#define GET_RX_DESC_MACID_RPT_BUFF(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 17, 7)
#define GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 16, 1)
#define GET_RX_DESC_RX_SCRAMBLER(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 9, 7)
#define GET_RX_DESC_RX_EOF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 8, 1)
#define GET_RX_DESC_PATTERN_IDX(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 0, 8)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x14, 0, 32)
#endif

51
drivers/staging/rtlwifi/halmac/halmac_sdio_reg.h
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@ -1,51 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_SDIO_REG_H__
#define __HALMAC_SDIO_REG_H__
/* SDIO CMD address mapping */
#define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF
#define HALMAC_SDIO_LOCAL_MSK 0x0FFF
#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF
#define HALMAC_WLAN_IOREG_MSK 0xFFFF
/* Sdio address for SDIO Local Reg, TRX FIFO, MAC Reg */
enum halmac_sdio_cmd_addr {
HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
HALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,
HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
HALMAC_SDIO_CMD_ADDR_RXFF = 7,
};
/* IO Bus domain address mapping */
#define SDIO_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define TX_MIQ_OFFSET 0x10320000
#define TX_LOQ_OFFSET 0x10330000
#define TX_EXQ_OFFSET 0x10350000
#define RX_RXOFF_OFFSET 0x10340000
/* Get TX WLAN FIFO information in CMD53 addr */
#define GET_WLAN_TXFF_DEVICE_ID(__cmd53_addr) \
LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 13, 4)
#define GET_WLAN_TXFF_PKT_SIZE(__cmd53_addr) \
(LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 0, 13) << 2)
#endif /* __HALMAC_SDIO_REG_H__ */

107
drivers/staging/rtlwifi/halmac/halmac_tx_bd_chip.h
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@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_BD_CHIP_H_
#define _HALMAC_TX_BD_CHIP_H_
/*TXBD_DW0*/
#define SET_TX_BD_OWN_8822B(__tx_bd, __value) SET_TX_BD_OWN(__tx_bd, __value)
#define GET_TX_BD_OWN_8822B(__tx_bd) GET_TX_BD_OWN(__tx_bd)
#define SET_TX_BD_PSB_8822B(__tx_bd, __value) SET_TX_BD_PSB(__tx_bd, __value)
#define GET_TX_BD_PSB_8822B(__tx_bd) GET_TX_BD_PSB(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE0(__tx_bd)
/*TXBD_DW1*/
#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd)
/*TXBD_DW2*/
#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd)
/*TXBD_DW4*/
#define SET_TX_BD_A1_8822B(__tx_bd, __value) SET_TX_BD_A1(__tx_bd, __value)
#define GET_TX_BD_A1_8822B(__tx_bd) GET_TX_BD_A1(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE1(__tx_bd)
/*TXBD_DW5*/
#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd)
/*TXBD_DW6*/
#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd)
/*TXBD_DW8*/
#define SET_TX_BD_A2_8822B(__tx_bd, __value) SET_TX_BD_A2(__tx_bd, __value)
#define GET_TX_BD_A2_8822B(__tx_bd) GET_TX_BD_A2(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE2(__tx_bd)
/*TXBD_DW9*/
#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd)
/*TXBD_DW10*/
#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd)
/*TXBD_DW12*/
#define SET_TX_BD_A3_8822B(__tx_bd, __value) SET_TX_BD_A3(__tx_bd, __value)
#define GET_TX_BD_A3_8822B(__tx_bd) GET_TX_BD_A3(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE3(__tx_bd)
/*TXBD_DW13*/
#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd)
/*TXBD_DW14*/
#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd)
#endif

112
drivers/staging/rtlwifi/halmac/halmac_tx_bd_nic.h
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@ -1,112 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_BD_NIC_H_
#define _HALMAC_TX_BD_NIC_H_
/*TXBD_DW0*/
#define SET_TX_BD_OWN(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 31, 1, __value)
#define GET_TX_BD_OWN(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 31, 1)
#define SET_TX_BD_PSB(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 16, 8, __value)
#define GET_TX_BD_PSB(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 16, 8)
#define SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE0(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 0, 16)
/*TXBD_DW1*/
#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x04, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x04, 0, 32)
/*TXBD_DW2*/
#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x08, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x08, 0, 32)
/*TXBD_DW4*/
#define SET_TX_BD_A1(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 31, 1, __value)
#define GET_TX_BD_A1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 0, 16)
/*TXBD_DW5*/
#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x14, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x14, 0, 32)
/*TXBD_DW6*/
#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x18, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x18, 0, 32)
/*TXBD_DW8*/
#define SET_TX_BD_A2(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 31, 1, __value)
#define GET_TX_BD_A2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 0, 16)
/*TXBD_DW9*/
#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x24, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x24, 0, 32)
/*TXBD_DW10*/
#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x28, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x28, 0, 32)
/*TXBD_DW12*/
#define SET_TX_BD_A3(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 31, 1, __value)
#define GET_TX_BD_A3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 0, 16)
/*TXBD_DW13*/
#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x34, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x34, 0, 32)
/*TXBD_DW14*/
#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x38, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x38, 0, 32)
#endif

433
drivers/staging/rtlwifi/halmac/halmac_tx_desc_chip.h
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@ -1,433 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_DESC_CHIP_H_
#define _HALMAC_TX_DESC_CHIP_H_
/*TXDESC_WORD0*/
#define SET_TX_DESC_DISQSELSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_DISQSELSEQ(__tx_desc, __value)
#define GET_TX_DESC_DISQSELSEQ_8822B(__tx_desc) \
GET_TX_DESC_DISQSELSEQ(__tx_desc)
#define SET_TX_DESC_GF_8822B(__tx_desc, __value) \
SET_TX_DESC_GF(__tx_desc, __value)
#define GET_TX_DESC_GF_8822B(__tx_desc) GET_TX_DESC_GF(__tx_desc)
#define SET_TX_DESC_NO_ACM_8822B(__tx_desc, __value) \
SET_TX_DESC_NO_ACM(__tx_desc, __value)
#define GET_TX_DESC_NO_ACM_8822B(__tx_desc) GET_TX_DESC_NO_ACM(__tx_desc)
#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc, __value) \
SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value)
#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc) \
GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc)
#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value)
#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc) \
GET_TX_DESC_AMSDU_PAD_EN(__tx_desc)
#define SET_TX_DESC_LS_8822B(__tx_desc, __value) \
SET_TX_DESC_LS(__tx_desc, __value)
#define GET_TX_DESC_LS_8822B(__tx_desc) GET_TX_DESC_LS(__tx_desc)
#define SET_TX_DESC_HTC_8822B(__tx_desc, __value) \
SET_TX_DESC_HTC(__tx_desc, __value)
#define GET_TX_DESC_HTC_8822B(__tx_desc) GET_TX_DESC_HTC(__tx_desc)
#define SET_TX_DESC_BMC_8822B(__tx_desc, __value) \
SET_TX_DESC_BMC(__tx_desc, __value)
#define GET_TX_DESC_BMC_8822B(__tx_desc) GET_TX_DESC_BMC(__tx_desc)
#define SET_TX_DESC_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_OFFSET_8822B(__tx_desc) GET_TX_DESC_OFFSET(__tx_desc)
#define SET_TX_DESC_TXPKTSIZE_8822B(__tx_desc, __value) \
SET_TX_DESC_TXPKTSIZE(__tx_desc, __value)
#define GET_TX_DESC_TXPKTSIZE_8822B(__tx_desc) GET_TX_DESC_TXPKTSIZE(__tx_desc)
/*TXDESC_WORD1*/
#define SET_TX_DESC_MOREDATA_8822B(__tx_desc, __value) \
SET_TX_DESC_MOREDATA(__tx_desc, __value)
#define GET_TX_DESC_MOREDATA_8822B(__tx_desc) GET_TX_DESC_MOREDATA(__tx_desc)
#define SET_TX_DESC_PKT_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_PKT_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_PKT_OFFSET_8822B(__tx_desc) \
GET_TX_DESC_PKT_OFFSET(__tx_desc)
#define SET_TX_DESC_SEC_TYPE_8822B(__tx_desc, __value) \
SET_TX_DESC_SEC_TYPE(__tx_desc, __value)
#define GET_TX_DESC_SEC_TYPE_8822B(__tx_desc) GET_TX_DESC_SEC_TYPE(__tx_desc)
#define SET_TX_DESC_EN_DESC_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_DESC_ID(__tx_desc, __value)
#define GET_TX_DESC_EN_DESC_ID_8822B(__tx_desc) \
GET_TX_DESC_EN_DESC_ID(__tx_desc)
#define SET_TX_DESC_RATE_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_RATE_ID(__tx_desc, __value)
#define GET_TX_DESC_RATE_ID_8822B(__tx_desc) GET_TX_DESC_RATE_ID(__tx_desc)
#define SET_TX_DESC_PIFS_8822B(__tx_desc, __value) \
SET_TX_DESC_PIFS(__tx_desc, __value)
#define GET_TX_DESC_PIFS_8822B(__tx_desc) GET_TX_DESC_PIFS(__tx_desc)
#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value)
#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc) \
GET_TX_DESC_LSIG_TXOP_EN(__tx_desc)
#define SET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc, __value) \
SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value)
#define GET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc) \
GET_TX_DESC_RD_NAV_EXT(__tx_desc)
#define SET_TX_DESC_QSEL_8822B(__tx_desc, __value) \
SET_TX_DESC_QSEL(__tx_desc, __value)
#define GET_TX_DESC_QSEL_8822B(__tx_desc) GET_TX_DESC_QSEL(__tx_desc)
#define SET_TX_DESC_MACID_8822B(__tx_desc, __value) \
SET_TX_DESC_MACID(__tx_desc, __value)
#define GET_TX_DESC_MACID_8822B(__tx_desc) GET_TX_DESC_MACID(__tx_desc)
/*TXDESC_WORD2*/
#define SET_TX_DESC_HW_AES_IV_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_AES_IV(__tx_desc, __value)
#define GET_TX_DESC_HW_AES_IV_8822B(__tx_desc) GET_TX_DESC_HW_AES_IV(__tx_desc)
#define SET_TX_DESC_FTM_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_FTM_EN(__tx_desc, __value)
#define GET_TX_DESC_FTM_EN_8822B(__tx_desc) GET_TX_DESC_FTM_EN(__tx_desc)
#define SET_TX_DESC_G_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_G_ID(__tx_desc, __value)
#define GET_TX_DESC_G_ID_8822B(__tx_desc) GET_TX_DESC_G_ID(__tx_desc)
#define SET_TX_DESC_BT_NULL_8822B(__tx_desc, __value) \
SET_TX_DESC_BT_NULL(__tx_desc, __value)
#define GET_TX_DESC_BT_NULL_8822B(__tx_desc) GET_TX_DESC_BT_NULL(__tx_desc)
#define SET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc, __value) \
SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value)
#define GET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc) \
GET_TX_DESC_AMPDU_DENSITY(__tx_desc)
#define SET_TX_DESC_SPE_RPT_8822B(__tx_desc, __value) \
SET_TX_DESC_SPE_RPT(__tx_desc, __value)
#define GET_TX_DESC_SPE_RPT_8822B(__tx_desc) GET_TX_DESC_SPE_RPT(__tx_desc)
#define SET_TX_DESC_RAW_8822B(__tx_desc, __value) \
SET_TX_DESC_RAW(__tx_desc, __value)
#define GET_TX_DESC_RAW_8822B(__tx_desc) GET_TX_DESC_RAW(__tx_desc)
#define SET_TX_DESC_MOREFRAG_8822B(__tx_desc, __value) \
SET_TX_DESC_MOREFRAG(__tx_desc, __value)
#define GET_TX_DESC_MOREFRAG_8822B(__tx_desc) GET_TX_DESC_MOREFRAG(__tx_desc)
#define SET_TX_DESC_BK_8822B(__tx_desc, __value) \
SET_TX_DESC_BK(__tx_desc, __value)
#define GET_TX_DESC_BK_8822B(__tx_desc) GET_TX_DESC_BK(__tx_desc)
#define SET_TX_DESC_NULL_1_8822B(__tx_desc, __value) \
SET_TX_DESC_NULL_1(__tx_desc, __value)
#define GET_TX_DESC_NULL_1_8822B(__tx_desc) GET_TX_DESC_NULL_1(__tx_desc)
#define SET_TX_DESC_NULL_0_8822B(__tx_desc, __value) \
SET_TX_DESC_NULL_0(__tx_desc, __value)
#define GET_TX_DESC_NULL_0_8822B(__tx_desc) GET_TX_DESC_NULL_0(__tx_desc)
#define SET_TX_DESC_RDG_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_RDG_EN(__tx_desc, __value)
#define GET_TX_DESC_RDG_EN_8822B(__tx_desc) GET_TX_DESC_RDG_EN(__tx_desc)
#define SET_TX_DESC_AGG_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_AGG_EN(__tx_desc, __value)
#define GET_TX_DESC_AGG_EN_8822B(__tx_desc) GET_TX_DESC_AGG_EN(__tx_desc)
#define SET_TX_DESC_CCA_RTS_8822B(__tx_desc, __value) \
SET_TX_DESC_CCA_RTS(__tx_desc, __value)
#define GET_TX_DESC_CCA_RTS_8822B(__tx_desc) GET_TX_DESC_CCA_RTS(__tx_desc)
#define SET_TX_DESC_TRI_FRAME_8822B(__tx_desc, __value) \
SET_TX_DESC_TRI_FRAME(__tx_desc, __value)
#define GET_TX_DESC_TRI_FRAME_8822B(__tx_desc) GET_TX_DESC_TRI_FRAME(__tx_desc)
#define SET_TX_DESC_P_AID_8822B(__tx_desc, __value) \
SET_TX_DESC_P_AID(__tx_desc, __value)
#define GET_TX_DESC_P_AID_8822B(__tx_desc) GET_TX_DESC_P_AID(__tx_desc)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc, __value) \
SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value)
#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc) \
GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc)
#define SET_TX_DESC_NDPA_8822B(__tx_desc, __value) \
SET_TX_DESC_NDPA(__tx_desc, __value)
#define GET_TX_DESC_NDPA_8822B(__tx_desc) GET_TX_DESC_NDPA(__tx_desc)
#define SET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc, __value) \
SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value)
#define GET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc) \
GET_TX_DESC_MAX_AGG_NUM(__tx_desc)
#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value)
#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc) \
GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc)
#define SET_TX_DESC_NAVUSEHDR_8822B(__tx_desc, __value) \
SET_TX_DESC_NAVUSEHDR(__tx_desc, __value)
#define GET_TX_DESC_NAVUSEHDR_8822B(__tx_desc) GET_TX_DESC_NAVUSEHDR(__tx_desc)
#define SET_TX_DESC_CHK_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_CHK_EN(__tx_desc, __value)
#define GET_TX_DESC_CHK_EN_8822B(__tx_desc) GET_TX_DESC_CHK_EN(__tx_desc)
#define SET_TX_DESC_HW_RTS_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_RTS_EN(__tx_desc, __value)
#define GET_TX_DESC_HW_RTS_EN_8822B(__tx_desc) GET_TX_DESC_HW_RTS_EN(__tx_desc)
#define SET_TX_DESC_RTSEN_8822B(__tx_desc, __value) \
SET_TX_DESC_RTSEN(__tx_desc, __value)
#define GET_TX_DESC_RTSEN_8822B(__tx_desc) GET_TX_DESC_RTSEN(__tx_desc)
#define SET_TX_DESC_CTS2SELF_8822B(__tx_desc, __value) \
SET_TX_DESC_CTS2SELF(__tx_desc, __value)
#define GET_TX_DESC_CTS2SELF_8822B(__tx_desc) GET_TX_DESC_CTS2SELF(__tx_desc)
#define SET_TX_DESC_DISDATAFB_8822B(__tx_desc, __value) \
SET_TX_DESC_DISDATAFB(__tx_desc, __value)
#define GET_TX_DESC_DISDATAFB_8822B(__tx_desc) GET_TX_DESC_DISDATAFB(__tx_desc)
#define SET_TX_DESC_DISRTSFB_8822B(__tx_desc, __value) \
SET_TX_DESC_DISRTSFB(__tx_desc, __value)
#define GET_TX_DESC_DISRTSFB_8822B(__tx_desc) GET_TX_DESC_DISRTSFB(__tx_desc)
#define SET_TX_DESC_USE_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_USE_RATE(__tx_desc, __value)
#define GET_TX_DESC_USE_RATE_8822B(__tx_desc) GET_TX_DESC_USE_RATE(__tx_desc)
#define SET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value)
#define GET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc) \
GET_TX_DESC_HW_SSN_SEL(__tx_desc)
#define SET_TX_DESC_WHEADER_LEN_8822B(__tx_desc, __value) \
SET_TX_DESC_WHEADER_LEN(__tx_desc, __value)
#define GET_TX_DESC_WHEADER_LEN_8822B(__tx_desc) \
GET_TX_DESC_WHEADER_LEN(__tx_desc)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc, __value) \
SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value)
#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc) \
GET_TX_DESC_PCTS_MASK_IDX(__tx_desc)
#define SET_TX_DESC_PCTS_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_PCTS_EN(__tx_desc, __value)
#define GET_TX_DESC_PCTS_EN_8822B(__tx_desc) GET_TX_DESC_PCTS_EN(__tx_desc)
#define SET_TX_DESC_RTSRATE_8822B(__tx_desc, __value) \
SET_TX_DESC_RTSRATE(__tx_desc, __value)
#define GET_TX_DESC_RTSRATE_8822B(__tx_desc) GET_TX_DESC_RTSRATE(__tx_desc)
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc) \
GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc)
#define SET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value)
#define GET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc) \
GET_TX_DESC_RTY_LMT_EN(__tx_desc)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc) \
GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc) \
GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc)
#define SET_TX_DESC_TRY_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_TRY_RATE(__tx_desc, __value)
#define GET_TX_DESC_TRY_RATE_8822B(__tx_desc) GET_TX_DESC_TRY_RATE(__tx_desc)
#define SET_TX_DESC_DATARATE_8822B(__tx_desc, __value) \
SET_TX_DESC_DATARATE(__tx_desc, __value)
#define GET_TX_DESC_DATARATE_8822B(__tx_desc) GET_TX_DESC_DATARATE(__tx_desc)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED_8822B(__tx_desc, __value) \
SET_TX_DESC_POLLUTED(__tx_desc, __value)
#define GET_TX_DESC_POLLUTED_8822B(__tx_desc) GET_TX_DESC_POLLUTED(__tx_desc)
#define SET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value)
#define GET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc) \
GET_TX_DESC_TXPWR_OFSET(__tx_desc)
#define SET_TX_DESC_TX_ANT_8822B(__tx_desc, __value) \
SET_TX_DESC_TX_ANT(__tx_desc, __value)
#define GET_TX_DESC_TX_ANT_8822B(__tx_desc) GET_TX_DESC_TX_ANT(__tx_desc)
#define SET_TX_DESC_PORT_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_PORT_ID(__tx_desc, __value)
#define GET_TX_DESC_PORT_ID_8822B(__tx_desc) GET_TX_DESC_PORT_ID(__tx_desc)
#define SET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc, __value) \
SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value)
#define GET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc) \
GET_TX_DESC_MULTIPLE_PORT(__tx_desc)
#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value)
#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc) \
GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc)
#define SET_TX_DESC_RTS_SC_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_SC(__tx_desc, __value)
#define GET_TX_DESC_RTS_SC_8822B(__tx_desc) GET_TX_DESC_RTS_SC(__tx_desc)
#define SET_TX_DESC_RTS_SHORT_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_SHORT(__tx_desc, __value)
#define GET_TX_DESC_RTS_SHORT_8822B(__tx_desc) GET_TX_DESC_RTS_SHORT(__tx_desc)
#define SET_TX_DESC_VCS_STBC_8822B(__tx_desc, __value) \
SET_TX_DESC_VCS_STBC(__tx_desc, __value)
#define GET_TX_DESC_VCS_STBC_8822B(__tx_desc) GET_TX_DESC_VCS_STBC(__tx_desc)
#define SET_TX_DESC_DATA_STBC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_STBC(__tx_desc, __value)
#define GET_TX_DESC_DATA_STBC_8822B(__tx_desc) GET_TX_DESC_DATA_STBC(__tx_desc)
#define SET_TX_DESC_DATA_LDPC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_LDPC(__tx_desc, __value)
#define GET_TX_DESC_DATA_LDPC_8822B(__tx_desc) GET_TX_DESC_DATA_LDPC(__tx_desc)
#define SET_TX_DESC_DATA_BW_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_BW(__tx_desc, __value)
#define GET_TX_DESC_DATA_BW_8822B(__tx_desc) GET_TX_DESC_DATA_BW(__tx_desc)
#define SET_TX_DESC_DATA_SHORT_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_SHORT(__tx_desc, __value)
#define GET_TX_DESC_DATA_SHORT_8822B(__tx_desc) \
GET_TX_DESC_DATA_SHORT(__tx_desc)
#define SET_TX_DESC_DATA_SC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_SC(__tx_desc, __value)
#define GET_TX_DESC_DATA_SC_8822B(__tx_desc) GET_TX_DESC_DATA_SC(__tx_desc)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANTSEL_D_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_D(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_D_8822B(__tx_desc) GET_TX_DESC_ANTSEL_D(__tx_desc)
#define SET_TX_DESC_ANT_MAPD_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPD(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPD_8822B(__tx_desc) GET_TX_DESC_ANT_MAPD(__tx_desc)
#define SET_TX_DESC_ANT_MAPC_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPC(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPC_8822B(__tx_desc) GET_TX_DESC_ANT_MAPC(__tx_desc)
#define SET_TX_DESC_ANT_MAPB_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPB(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPB_8822B(__tx_desc) GET_TX_DESC_ANT_MAPB(__tx_desc)
#define SET_TX_DESC_ANT_MAPA_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPA(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPA_8822B(__tx_desc) GET_TX_DESC_ANT_MAPA(__tx_desc)
#define SET_TX_DESC_ANTSEL_C_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_C(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_C_8822B(__tx_desc) GET_TX_DESC_ANTSEL_C(__tx_desc)
#define SET_TX_DESC_ANTSEL_B_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_B(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_B_8822B(__tx_desc) GET_TX_DESC_ANTSEL_B(__tx_desc)
#define SET_TX_DESC_ANTSEL_A_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_A(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_A_8822B(__tx_desc) GET_TX_DESC_ANTSEL_A(__tx_desc)
#define SET_TX_DESC_MBSSID_8822B(__tx_desc, __value) \
SET_TX_DESC_MBSSID(__tx_desc, __value)
#define GET_TX_DESC_MBSSID_8822B(__tx_desc) GET_TX_DESC_MBSSID(__tx_desc)
#define SET_TX_DESC_SW_DEFINE_8822B(__tx_desc, __value) \
SET_TX_DESC_SW_DEFINE(__tx_desc, __value)
#define GET_TX_DESC_SW_DEFINE_8822B(__tx_desc) GET_TX_DESC_SW_DEFINE(__tx_desc)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc, __value) \
SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value)
#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc) \
GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc)
#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value)
#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc) \
GET_TX_DESC_FINAL_DATA_RATE(__tx_desc)
#define SET_TX_DESC_NTX_MAP_8822B(__tx_desc, __value) \
SET_TX_DESC_NTX_MAP(__tx_desc, __value)
#define GET_TX_DESC_NTX_MAP_8822B(__tx_desc) GET_TX_DESC_NTX_MAP(__tx_desc)
#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc, __value) \
SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value)
#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc) \
GET_TX_DESC_TX_BUFF_SIZE(__tx_desc)
#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc, __value) \
SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value)
#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc) \
GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc)
#define SET_TX_DESC_TIMESTAMP_8822B(__tx_desc, __value) \
SET_TX_DESC_TIMESTAMP(__tx_desc, __value)
#define GET_TX_DESC_TIMESTAMP_8822B(__tx_desc) GET_TX_DESC_TIMESTAMP(__tx_desc)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP_8822B(__tx_desc, __value) \
SET_TX_DESC_TXWIFI_CP(__tx_desc, __value)
#define GET_TX_DESC_TXWIFI_CP_8822B(__tx_desc) GET_TX_DESC_TXWIFI_CP(__tx_desc)
#define SET_TX_DESC_MAC_CP_8822B(__tx_desc, __value) \
SET_TX_DESC_MAC_CP(__tx_desc, __value)
#define GET_TX_DESC_MAC_CP_8822B(__tx_desc) GET_TX_DESC_MAC_CP(__tx_desc)
#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_PKTRE_DIS(__tx_desc)
#define SET_TX_DESC_STW_RB_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_RB_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_RB_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_RB_DIS(__tx_desc)
#define SET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_RATE_DIS(__tx_desc)
#define SET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_ANT_DIS(__tx_desc)
#define SET_TX_DESC_STW_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_EN(__tx_desc, __value)
#define GET_TX_DESC_STW_EN_8822B(__tx_desc) GET_TX_DESC_STW_EN(__tx_desc)
#define SET_TX_DESC_SMH_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_SMH_EN(__tx_desc, __value)
#define GET_TX_DESC_SMH_EN_8822B(__tx_desc) GET_TX_DESC_SMH_EN(__tx_desc)
#define SET_TX_DESC_TAILPAGE_L_8822B(__tx_desc, __value) \
SET_TX_DESC_TAILPAGE_L(__tx_desc, __value)
#define GET_TX_DESC_TAILPAGE_L_8822B(__tx_desc) \
GET_TX_DESC_TAILPAGE_L(__tx_desc)
#define SET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value)
#define GET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc) \
GET_TX_DESC_SDIO_DMASEQ(__tx_desc)
#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc, __value) \
SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value)
#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc) \
GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc)
#define SET_TX_DESC_EN_HWSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_HWSEQ(__tx_desc, __value)
#define GET_TX_DESC_EN_HWSEQ_8822B(__tx_desc) GET_TX_DESC_EN_HWSEQ(__tx_desc)
#define SET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value)
#define GET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc) \
GET_TX_DESC_EN_HWEXSEQ(__tx_desc)
#define SET_TX_DESC_DATA_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_RC(__tx_desc, __value)
#define GET_TX_DESC_DATA_RC_8822B(__tx_desc) GET_TX_DESC_DATA_RC(__tx_desc)
#define SET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc, __value) \
SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value)
#define GET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc) \
GET_TX_DESC_BAR_RTY_TH(__tx_desc)
#define SET_TX_DESC_RTS_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_RC(__tx_desc, __value)
#define GET_TX_DESC_RTS_RC_8822B(__tx_desc) GET_TX_DESC_RTS_RC(__tx_desc)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H_8822B(__tx_desc, __value) \
SET_TX_DESC_TAILPAGE_H(__tx_desc, __value)
#define GET_TX_DESC_TAILPAGE_H_8822B(__tx_desc) \
GET_TX_DESC_TAILPAGE_H(__tx_desc)
#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc, __value) \
SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value)
#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc) \
GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc)
#define SET_TX_DESC_SW_SEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_SW_SEQ(__tx_desc, __value)
#define GET_TX_DESC_SW_SEQ_8822B(__tx_desc) GET_TX_DESC_SW_SEQ(__tx_desc)
#define SET_TX_DESC_TXBF_PATH_8822B(__tx_desc, __value) \
SET_TX_DESC_TXBF_PATH(__tx_desc, __value)
#define GET_TX_DESC_TXBF_PATH_8822B(__tx_desc) GET_TX_DESC_TXBF_PATH(__tx_desc)
#define SET_TX_DESC_PADDING_LEN_8822B(__tx_desc, __value) \
SET_TX_DESC_PADDING_LEN(__tx_desc, __value)
#define GET_TX_DESC_PADDING_LEN_8822B(__tx_desc) \
GET_TX_DESC_PADDING_LEN(__tx_desc)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc) \
GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc)
/*WORD10*/
#define SET_TX_DESC_MU_DATARATE_8822B(__tx_desc, __value) \
SET_TX_DESC_MU_DATARATE(__tx_desc, __value)
#define GET_TX_DESC_MU_DATARATE_8822B(__tx_desc) \
GET_TX_DESC_MU_DATARATE(__tx_desc)
#define SET_TX_DESC_MU_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_MU_RC(__tx_desc, __value)
#define GET_TX_DESC_MU_RC_8822B(__tx_desc) GET_TX_DESC_MU_RC(__tx_desc)
#define SET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc, __value) \
SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value)
#define GET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc) \
GET_TX_DESC_SND_PKT_SEL(__tx_desc)
#endif

495
drivers/staging/rtlwifi/halmac/halmac_tx_desc_nic.h
View File

@ -1,495 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_DESC_NIC_H_
#define _HALMAC_TX_DESC_NIC_H_
/*TXDESC_WORD0*/
#define SET_TX_DESC_DISQSELSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 31, 1, __value)
#define GET_TX_DESC_DISQSELSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 31, 1)
#define SET_TX_DESC_GF(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 30, 1, __value)
#define GET_TX_DESC_GF(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 30, 1)
#define SET_TX_DESC_NO_ACM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 29, 1, __value)
#define GET_TX_DESC_NO_ACM(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 29, 1)
#define SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 28, 1, __value)
#define GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 28, 1)
#define SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 27, 1, __value)
#define GET_TX_DESC_AMSDU_PAD_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 27, 1)
#define SET_TX_DESC_LS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 26, 1, __value)
#define GET_TX_DESC_LS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 26, 1)
#define SET_TX_DESC_HTC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 25, 1, __value)
#define GET_TX_DESC_HTC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 25, 1)
#define SET_TX_DESC_BMC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 24, 1, __value)
#define GET_TX_DESC_BMC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 24, 1)
#define SET_TX_DESC_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 16, 8, __value)
#define GET_TX_DESC_OFFSET(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 16, 8)
#define SET_TX_DESC_TXPKTSIZE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 0, 16, __value)
#define GET_TX_DESC_TXPKTSIZE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 0, 16)
/*TXDESC_WORD1*/
#define SET_TX_DESC_MOREDATA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 29, 1, __value)
#define GET_TX_DESC_MOREDATA(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 29, 1)
#define SET_TX_DESC_PKT_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 24, 5, __value)
#define GET_TX_DESC_PKT_OFFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 24, 5)
#define SET_TX_DESC_SEC_TYPE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 22, 2, __value)
#define GET_TX_DESC_SEC_TYPE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 22, 2)
#define SET_TX_DESC_EN_DESC_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 21, 1, __value)
#define GET_TX_DESC_EN_DESC_ID(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 21, 1)
#define SET_TX_DESC_RATE_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 16, 5, __value)
#define GET_TX_DESC_RATE_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 16, 5)
#define SET_TX_DESC_PIFS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 15, 1, __value)
#define GET_TX_DESC_PIFS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 15, 1)
#define SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 14, 1, __value)
#define GET_TX_DESC_LSIG_TXOP_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 14, 1)
#define SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 13, 1, __value)
#define GET_TX_DESC_RD_NAV_EXT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 13, 1)
#define SET_TX_DESC_QSEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 8, 5, __value)
#define GET_TX_DESC_QSEL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 8, 5)
#define SET_TX_DESC_MACID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 0, 7, __value)
#define GET_TX_DESC_MACID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 0, 7)
/*TXDESC_WORD2*/
#define SET_TX_DESC_HW_AES_IV(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 31, 1, __value)
#define GET_TX_DESC_HW_AES_IV(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 31, 1)
#define SET_TX_DESC_FTM_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 30, 1, __value)
#define GET_TX_DESC_FTM_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 30, 1)
#define SET_TX_DESC_G_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 24, 6, __value)
#define GET_TX_DESC_G_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 24, 6)
#define SET_TX_DESC_BT_NULL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 23, 1, __value)
#define GET_TX_DESC_BT_NULL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 23, 1)
#define SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 20, 3, __value)
#define GET_TX_DESC_AMPDU_DENSITY(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 20, 3)
#ifdef SET_TX_DESC_SPE_RPT
#undef SET_TX_DESC_SPE_RPT
#endif
#define SET_TX_DESC_SPE_RPT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 19, 1, __value)
#define GET_TX_DESC_SPE_RPT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 19, 1)
#define SET_TX_DESC_RAW(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 18, 1, __value)
#define GET_TX_DESC_RAW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 18, 1)
#define SET_TX_DESC_MOREFRAG(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 17, 1, __value)
#define GET_TX_DESC_MOREFRAG(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 17, 1)
#define SET_TX_DESC_BK(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 16, 1, __value)
#define GET_TX_DESC_BK(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 16, 1)
#define SET_TX_DESC_NULL_1(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 15, 1, __value)
#define GET_TX_DESC_NULL_1(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 15, 1)
#define SET_TX_DESC_NULL_0(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 14, 1, __value)
#define GET_TX_DESC_NULL_0(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 14, 1)
#define SET_TX_DESC_RDG_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 13, 1, __value)
#define GET_TX_DESC_RDG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 13, 1)
#define SET_TX_DESC_AGG_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 12, 1, __value)
#define GET_TX_DESC_AGG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 12, 1)
#define SET_TX_DESC_CCA_RTS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 10, 2, __value)
#define GET_TX_DESC_CCA_RTS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 10, 2)
#define SET_TX_DESC_TRI_FRAME(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 9, 1, __value)
#define GET_TX_DESC_TRI_FRAME(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 9, 1)
#define SET_TX_DESC_P_AID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 0, 9, __value)
#define GET_TX_DESC_P_AID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 0, 9)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 24, 8, __value)
#define GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 24, 8)
#define SET_TX_DESC_NDPA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 22, 2, __value)
#define GET_TX_DESC_NDPA(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 22, 2)
#define SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 17, 5, __value)
#define GET_TX_DESC_MAX_AGG_NUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 17, 5)
#define SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 16, 1, __value)
#define GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 16, 1)
#define SET_TX_DESC_NAVUSEHDR(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 15, 1, __value)
#define GET_TX_DESC_NAVUSEHDR(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 15, 1)
#define SET_TX_DESC_CHK_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 14, 1, __value)
#define GET_TX_DESC_CHK_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 14, 1)
#define SET_TX_DESC_HW_RTS_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 13, 1, __value)
#define GET_TX_DESC_HW_RTS_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 13, 1)
#define SET_TX_DESC_RTSEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 12, 1, __value)
#define GET_TX_DESC_RTSEN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 12, 1)
#define SET_TX_DESC_CTS2SELF(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 11, 1, __value)
#define GET_TX_DESC_CTS2SELF(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 11, 1)
#define SET_TX_DESC_DISDATAFB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 10, 1, __value)
#define GET_TX_DESC_DISDATAFB(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 10, 1)
#define SET_TX_DESC_DISRTSFB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 9, 1, __value)
#define GET_TX_DESC_DISRTSFB(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 9, 1)
#define SET_TX_DESC_USE_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 8, 1, __value)
#define GET_TX_DESC_USE_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 8, 1)
#define SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 6, 2, __value)
#define GET_TX_DESC_HW_SSN_SEL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 6, 2)
#define SET_TX_DESC_WHEADER_LEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 0, 5, __value)
#define GET_TX_DESC_WHEADER_LEN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 0, 5)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 30, 2, __value)
#define GET_TX_DESC_PCTS_MASK_IDX(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 30, 2)
#define SET_TX_DESC_PCTS_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 29, 1, __value)
#define GET_TX_DESC_PCTS_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 29, 1)
#define SET_TX_DESC_RTSRATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 24, 5, __value)
#define GET_TX_DESC_RTSRATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 24, 5)
#define SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 18, 6, __value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 18, 6)
#define SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 17, 1, __value)
#define GET_TX_DESC_RTY_LMT_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 17, 1)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 13, 4, __value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 13, 4)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 8, 5, __value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 8, 5)
#define SET_TX_DESC_TRY_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 7, 1, __value)
#define GET_TX_DESC_TRY_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 7, 1)
#define SET_TX_DESC_DATARATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 0, 7, __value)
#define GET_TX_DESC_DATARATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 0, 7)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 31, 1, __value)
#define GET_TX_DESC_POLLUTED(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 31, 1)
#define SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 28, 3, __value)
#define GET_TX_DESC_TXPWR_OFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 28, 3)
#define SET_TX_DESC_TX_ANT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 24, 4, __value)
#define GET_TX_DESC_TX_ANT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 24, 4)
#define SET_TX_DESC_PORT_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 21, 3, __value)
#define GET_TX_DESC_PORT_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 21, 3)
#define SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 18, 3, __value)
#define GET_TX_DESC_MULTIPLE_PORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 18, 3)
#define SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 17, 1, __value)
#define GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 17, 1)
#define SET_TX_DESC_RTS_SC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 13, 4, __value)
#define GET_TX_DESC_RTS_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 13, 4)
#define SET_TX_DESC_RTS_SHORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 12, 1, __value)
#define GET_TX_DESC_RTS_SHORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 12, 1)
#define SET_TX_DESC_VCS_STBC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 10, 2, __value)
#define GET_TX_DESC_VCS_STBC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 10, 2)
#define SET_TX_DESC_DATA_STBC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 8, 2, __value)
#define GET_TX_DESC_DATA_STBC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 8, 2)
#define SET_TX_DESC_DATA_LDPC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 7, 1, __value)
#define GET_TX_DESC_DATA_LDPC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 7, 1)
#define SET_TX_DESC_DATA_BW(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 5, 2, __value)
#define GET_TX_DESC_DATA_BW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 5, 2)
#define SET_TX_DESC_DATA_SHORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 4, 1, __value)
#define GET_TX_DESC_DATA_SHORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 4, 1)
#define SET_TX_DESC_DATA_SC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 0, 4, __value)
#define GET_TX_DESC_DATA_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 0, 4)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANTSEL_D(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 30, 2, __value)
#define GET_TX_DESC_ANTSEL_D(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 30, 2)
#define SET_TX_DESC_ANT_MAPD(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 28, 2, __value)
#define GET_TX_DESC_ANT_MAPD(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 28, 2)
#define SET_TX_DESC_ANT_MAPC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 26, 2, __value)
#define GET_TX_DESC_ANT_MAPC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 26, 2)
#define SET_TX_DESC_ANT_MAPB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 24, 2, __value)
#define GET_TX_DESC_ANT_MAPB(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 24, 2)
#define SET_TX_DESC_ANT_MAPA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 22, 2, __value)
#define GET_TX_DESC_ANT_MAPA(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 22, 2)
#define SET_TX_DESC_ANTSEL_C(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 20, 2, __value)
#define GET_TX_DESC_ANTSEL_C(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 20, 2)
#define SET_TX_DESC_ANTSEL_B(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 18, 2, __value)
#define GET_TX_DESC_ANTSEL_B(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 18, 2)
#define SET_TX_DESC_ANTSEL_A(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 16, 2, __value)
#define GET_TX_DESC_ANTSEL_A(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 16, 2)
#define SET_TX_DESC_MBSSID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 12, 4, __value)
#define GET_TX_DESC_MBSSID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x18, 12, 4)
#ifdef SET_TX_DESC_SW_DEFINE
#undef SET_TX_DESC_SW_DEFINE
#endif
#define SET_TX_DESC_SW_DEFINE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 0, 12, __value)
#define GET_TX_DESC_SW_DEFINE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 0, 12)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
#define GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
#define SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
#define GET_TX_DESC_FINAL_DATA_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
#define SET_TX_DESC_NTX_MAP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 20, 4, __value)
#define GET_TX_DESC_NTX_MAP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 20, 4)
#define SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TX_BUFF_SIZE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
#define SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
#define SET_TX_DESC_TIMESTAMP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TIMESTAMP(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 31, 1, __value)
#define GET_TX_DESC_TXWIFI_CP(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 31, 1)
#define SET_TX_DESC_MAC_CP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 30, 1, __value)
#define GET_TX_DESC_MAC_CP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 30, 1)
#define SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 29, 1, __value)
#define GET_TX_DESC_STW_PKTRE_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 29, 1)
#define SET_TX_DESC_STW_RB_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 28, 1, __value)
#define GET_TX_DESC_STW_RB_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 28, 1)
#define SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 27, 1, __value)
#define GET_TX_DESC_STW_RATE_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 27, 1)
#define SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 26, 1, __value)
#define GET_TX_DESC_STW_ANT_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 26, 1)
#define SET_TX_DESC_STW_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 25, 1, __value)
#define GET_TX_DESC_STW_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 25, 1)
#define SET_TX_DESC_SMH_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 1, __value)
#define GET_TX_DESC_SMH_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 1)
#define SET_TX_DESC_TAILPAGE_L(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 8, __value)
#define GET_TX_DESC_TAILPAGE_L(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 8)
#define SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
#define GET_TX_DESC_SDIO_DMASEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
#define SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
#define GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
#define SET_TX_DESC_EN_HWSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 15, 1, __value)
#define GET_TX_DESC_EN_HWSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 15, 1)
#define SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 14, 1, __value)
#define GET_TX_DESC_EN_HWEXSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 14, 1)
#define SET_TX_DESC_DATA_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 8, 6, __value)
#define GET_TX_DESC_DATA_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 8, 6)
#define SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 6, 2, __value)
#define GET_TX_DESC_BAR_RTY_TH(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 6, 2)
#define SET_TX_DESC_RTS_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 0, 6, __value)
#define GET_TX_DESC_RTS_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 0, 6)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 28, 4, __value)
#define GET_TX_DESC_TAILPAGE_H(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 28, 4)
#define SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 24, 4, __value)
#define GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 24, 4)
#define SET_TX_DESC_SW_SEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 12, 12, __value)
#define GET_TX_DESC_SW_SEQ(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x24, 12, 12)
#define SET_TX_DESC_TXBF_PATH(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 11, 1, __value)
#define GET_TX_DESC_TXBF_PATH(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 11, 1)
#define SET_TX_DESC_PADDING_LEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 11, __value)
#define GET_TX_DESC_PADDING_LEN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 11)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 8, __value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 8)
/*WORD10*/
#define SET_TX_DESC_MU_DATARATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 8, 8, __value)
#define GET_TX_DESC_MU_DATARATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x28, 8, 8)
#define SET_TX_DESC_MU_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 4, 4, __value)
#define GET_TX_DESC_MU_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x28, 4, 4)
#define SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 0, 2, __value)
#define GET_TX_DESC_SND_PKT_SEL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x28, 0, 2)
#endif

1923
drivers/staging/rtlwifi/halmac/halmac_type.h
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17
drivers/staging/rtlwifi/halmac/halmac_usb_reg.h
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@ -1,17 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_USB_REG_H__
#define __HALMAC_USB_REG_H__
#endif /* __HALMAC_USB_REG_H__ */

1373
drivers/staging/rtlwifi/halmac/rtl_halmac.c
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drivers/staging/rtlwifi/halmac/rtl_halmac.h
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/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _RTL_HALMAC_H_
#define _RTL_HALMAC_H_
#include "halmac_api.h"
#define rtlpriv_to_halmac(priv) \
((struct halmac_adapter *)((priv)->halmac.internal))
/* for H2C cmd */
#define MAX_H2C_BOX_NUMS 4
#define MESSAGE_BOX_SIZE 4
#define EX_MESSAGE_BOX_SIZE 4
/* HALMAC API for Driver(HAL) */
int rtl_halmac_init_adapter(struct rtl_priv *rtlpriv);
int rtl_halmac_deinit_adapter(struct rtl_priv *rtlpriv);
int rtl_halmac_poweron(struct rtl_priv *rtlpriv);
int rtl_halmac_poweroff(struct rtl_priv *rtlpriv);
int rtl_halmac_init_hal(struct rtl_priv *rtlpriv);
int rtl_halmac_init_hal_fw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
int rtl_halmac_init_hal_fw_file(struct rtl_priv *rtlpriv, u8 *fwpath);
int rtl_halmac_deinit_hal(struct rtl_priv *rtlpriv);
int rtl_halmac_self_verify(struct rtl_priv *rtlpriv);
int rtl_halmac_dlfw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
int rtl_halmac_dlfw_from_file(struct rtl_priv *rtlpriv, u8 *fwpath);
int rtl_halmac_phy_power_switch(struct rtl_priv *rtlpriv, u8 enable);
int rtl_halmac_send_h2c(struct rtl_priv *rtlpriv, u8 *h2c);
int rtl_halmac_c2h_handle(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
int rtl_halmac_get_physical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
int rtl_halmac_read_physical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size);
int rtl_halmac_read_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_write_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_get_logical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
int rtl_halmac_read_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size);
int rtl_halmac_write_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size, u8 *maskmap, u32 masksize);
int rtl_halmac_read_logical_efuse(struct rtl_priv *rtlpriv, u32 offset, u32 cnt,
u8 *data);
int rtl_halmac_write_logical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_config_rx_info(struct rtl_priv *rtlpriv, enum halmac_drv_info);
int rtl_halmac_set_mac_address(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
int rtl_halmac_set_bssid(struct rtl_priv *d, u8 hwport, u8 *addr);
int rtl_halmac_set_bandwidth(struct rtl_priv *rtlpriv, u8 channel,
u8 pri_ch_idx, u8 bw);
int rtl_halmac_rx_agg_switch(struct rtl_priv *rtlpriv, bool enable);
int rtl_halmac_get_hw_value(struct rtl_priv *d, enum halmac_hw_id hw_id,
void *pvalue);
int rtl_halmac_dump_fifo(struct rtl_priv *rtlpriv,
enum hal_fifo_sel halmac_fifo_sel);
int rtl_halmac_get_wow_reason(struct rtl_priv *rtlpriv, u8 *reason);
int rtl_halmac_get_drv_info_sz(struct rtl_priv *d, u8 *sz);
int rtl_halmac_get_rsvd_drv_pg_bndy(struct rtl_priv *dvobj, u16 *drv_pg);
int rtl_halmac_download_rsvd_page(struct rtl_priv *dvobj, u8 pg_offset,
u8 *pbuf, u32 size);
int rtl_halmac_chk_txdesc(struct rtl_priv *rtlpriv, u8 *txdesc, u32 size);
struct rtl_halmac_ops *rtl_halmac_get_ops_pointer(void);
#endif /* _RTL_HALMAC_H_ */

2496
drivers/staging/rtlwifi/pci.c
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319
drivers/staging/rtlwifi/pci.h
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@ -1,319 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2009-2012 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_PCI_H__
#define __RTL_PCI_H__
#include <linux/pci.h>
/* 1: MSDU packet queue,
* 2: Rx Command Queue
*/
#define RTL_PCI_RX_MPDU_QUEUE 0
#define RTL_PCI_RX_CMD_QUEUE 1
#define RTL_PCI_MAX_RX_QUEUE 2
#define RTL_PCI_MAX_RX_COUNT 512/*64*/
#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
#define RT_TXDESC_NUM 128
#define TX_DESC_NUM_92E 512
#define TX_DESC_NUM_8822B 512
#define RT_TXDESC_NUM_BE_QUEUE 256
#define BK_QUEUE 0
#define BE_QUEUE 1
#define VI_QUEUE 2
#define VO_QUEUE 3
#define BEACON_QUEUE 4
#define TXCMD_QUEUE 5
#define MGNT_QUEUE 6
#define HIGH_QUEUE 7
#define HCCA_QUEUE 8
#define H2C_QUEUE TXCMD_QUEUE /* In 8822B */
#define RTL_PCI_DEVICE(vend, dev, cfg) \
.vendor = (vend), \
.device = (dev), \
.subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID,\
.driver_data = (kernel_ulong_t)&(cfg)
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define PCI_CAP_ID_EXP 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
#define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
#define RTL_PCI_700F_DID 0x700F
#define RTL_PCI_701F_DID 0x701F
#define RTL_PCI_DLINK_DID 0x3304
#define RTL_PCI_8723AE_DID 0x8723 /*8723e */
#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
#define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
#define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
#define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
#define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
#define RTL_PCI_8822BE_DID 0xB822 /*8822be*/
/*8192 support 16 pages of IO registers*/
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
#define RTL_PCI_REVISION_ID_8190PCI 0x00
#define RTL_PCI_REVISION_ID_8192PCIE 0x01
#define RTL_PCI_REVISION_ID_8192SE 0x10
#define RTL_PCI_REVISION_ID_8192CE 0x1
#define RTL_PCI_REVISION_ID_8192DE 0x0
#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
PCI_BRIDGE_VENDOR_MAX,
};
struct rtl_pci_capabilities_header {
u8 capability_id;
u8 next;
};
/* In new TRX flow, Buffer_desc is new concept
* But TX wifi info == TX descriptor in old flow
* RX wifi info == RX descriptor in old flow
*/
struct rtl_tx_buffer_desc {
u32 dword[4 * (1 << (BUFDESC_SEG_NUM + 1))];
} __packed;
struct rtl_tx_desc {
u32 dword[16];
} __packed;
struct rtl_rx_buffer_desc { /*rx buffer desc*/
u32 dword[4];
} __packed;
struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
u32 dword[8];
} __packed;
struct rtl_tx_cmd_desc {
u32 dword[16];
} __packed;
struct rtl8192_tx_ring {
struct rtl_tx_desc *desc;
dma_addr_t dma;
unsigned int idx;
unsigned int entries;
struct sk_buff_head queue;
/*add for new trx flow*/
struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
u16 cur_tx_wp; /* current_tx_write_point */
u16 cur_tx_rp; /* current_tx_read_point */
};
struct rtl8192_rx_ring {
struct rtl_rx_desc *desc;
dma_addr_t dma;
unsigned int idx;
struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
/*add for new trx flow*/
struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
u16 next_rx_rp; /* next_rx_read_point */
};
struct rtl_pci {
struct pci_dev *pdev;
bool irq_enabled;
bool driver_is_goingto_unload;
bool up_first_time;
bool first_init;
bool being_init_adapter;
bool init_ready;
/*Tx */
struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
u32 transmit_config;
/*Rx */
struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
int rxringcount;
u16 rxbuffersize;
u32 receive_config;
/*irq */
u8 irq_alloc;
u32 irq_mask[4]; /* 0-1: normal, 2: unused, 3: h2c */
u32 sys_irq_mask;
/*Bcn control register setting */
u32 reg_bcn_ctrl_val;
/*ASPM*/
u8 const_pci_aspm;
u8 const_amdpci_aspm;
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
/*pci-e bridge */
u8 const_hostpci_aspm_setting;
/*pci-e device */
u8 const_devicepci_aspm_setting;
/* If it supports ASPM, Offset[560h] = 0x40,
* otherwise Offset[560h] = 0x00.
*/
bool support_aspm;
bool support_backdoor;
/*QOS & EDCA */
enum acm_method acm_method;
u16 shortretry_limit;
u16 longretry_limit;
/* MSI support */
bool msi_support;
bool using_msi;
/* interrupt clear before set */
bool int_clear;
};
struct mp_adapter {
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u8 num4bytes;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
bool amd_l1_patch;
};
struct rtl_pci_priv {
struct bt_coexist_info bt_coexist;
struct rtl_led_ctl ledctl;
struct rtl_pci dev;
struct mp_adapter ndis_adapter;
};
#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
extern const struct rtl_intf_ops rtl_pci_ops;
int rtl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id);
void rtl_pci_disconnect(struct pci_dev *pdev);
#ifdef CONFIG_PM_SLEEP
int rtl_pci_suspend(struct device *dev);
int rtl_pci_resume(struct device *dev);
#endif /* CONFIG_PM_SLEEP */
static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readb((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readw((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readl((u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
{
writeb(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write16_async(struct rtl_priv *rtlpriv,
u32 addr, u16 val)
{
writew(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write32_async(struct rtl_priv *rtlpriv,
u32 addr, u32 val)
{
writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
}
static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size)
{
if (rp <= wp)
return size - 1 + rp - wp;
return rp - wp - 1;
}
#endif

954
drivers/staging/rtlwifi/phydm/halphyrf_ce.c
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// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, \
_delta_thermal) \
do { \
for (_offset = 0; _offset < _size; _offset++) { \
if (_delta_thermal < \
thermal_threshold[_direction][_offset]) { \
if (_offset != 0) \
_offset--; \
break; \
} \
} \
if (_offset >= _size) \
_offset = _size - 1; \
} while (0)
static inline void phydm_set_calibrate_info_up(
struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
struct dm_rf_calibration_struct *cali_info,
u8 *delta_swing_table_idx_tup_a, u8 *delta_swing_table_idx_tup_b,
u8 *delta_swing_table_idx_tup_c, u8 *delta_swing_table_idx_tup_d)
{
u8 p = 0;
for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
cali_info->delta_power_index_last[p] =
cali_info->delta_power_index
[p]; /*recording poer index offset*/
switch (p) {
case ODM_RF_PATH_B:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_b[%d] = %d\n",
delta, delta_swing_table_idx_tup_b[delta]);
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_b[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_b[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
case ODM_RF_PATH_C:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_c[%d] = %d\n",
delta, delta_swing_table_idx_tup_c[delta]);
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_c[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_c[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
case ODM_RF_PATH_D:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_d[%d] = %d\n",
delta, delta_swing_table_idx_tup_d[delta]);
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_d[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_d[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tup_a[%d] = %d\n",
delta, delta_swing_table_idx_tup_a[delta]);
cali_info->delta_power_index[p] =
delta_swing_table_idx_tup_a[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
delta_swing_table_idx_tup_a[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is higher and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
}
static inline void phydm_set_calibrate_info_down(
struct phy_dm_struct *dm, struct txpwrtrack_cfg *c, u8 delta,
struct dm_rf_calibration_struct *cali_info,
u8 *delta_swing_table_idx_tdown_a, u8 *delta_swing_table_idx_tdown_b,
u8 *delta_swing_table_idx_tdown_c, u8 *delta_swing_table_idx_tdown_d)
{
u8 p = 0;
for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
cali_info->delta_power_index_last[p] =
cali_info->delta_power_index
[p]; /*recording poer index offset*/
switch (p) {
case ODM_RF_PATH_B:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_b[%d] = %d\n",
delta,
delta_swing_table_idx_tdown_b[delta]);
cali_info->delta_power_index[p] =
-1 * delta_swing_table_idx_tdown_b[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
-1 * delta_swing_table_idx_tdown_b[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
case ODM_RF_PATH_C:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_c[%d] = %d\n",
delta,
delta_swing_table_idx_tdown_c[delta]);
cali_info->delta_power_index[p] =
-1 * delta_swing_table_idx_tdown_c[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
-1 * delta_swing_table_idx_tdown_c[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
case ODM_RF_PATH_D:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_d[%d] = %d\n",
delta,
delta_swing_table_idx_tdown_d[delta]);
cali_info->delta_power_index[p] =
-1 * delta_swing_table_idx_tdown_d[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
-1 * delta_swing_table_idx_tdown_d[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
default:
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_swing_table_idx_tdown_a[%d] = %d\n",
delta,
delta_swing_table_idx_tdown_a[delta]);
cali_info->delta_power_index[p] =
-1 * delta_swing_table_idx_tdown_a[delta];
/*Record delta swing for mix mode pwr tracking*/
cali_info->absolute_ofdm_swing_idx[p] =
-1 * delta_swing_table_idx_tdown_a[delta];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"******Temp is lower and cali_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n",
cali_info->absolute_ofdm_swing_idx[p]);
break;
}
}
}
static inline void phydm_odm_tx_power_set(struct phy_dm_struct *dm,
struct txpwrtrack_cfg *c,
u8 indexforchannel, u8 flag)
{
u8 p = 0;
if (dm->support_ic_type == ODM_RTL8188E ||
dm->support_ic_type == ODM_RTL8192E ||
dm->support_ic_type == ODM_RTL8821 ||
dm->support_ic_type == ODM_RTL8812 ||
dm->support_ic_type == ODM_RTL8723B ||
dm->support_ic_type == ODM_RTL8814A ||
dm->support_ic_type == ODM_RTL8703B ||
dm->support_ic_type == ODM_RTL8188F ||
dm->support_ic_type == ODM_RTL8822B ||
dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8821C ||
dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking MIX_MODE**********\n");
for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++) {
if (flag == 0)
(*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
0);
else
(*c->odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
indexforchannel);
}
} else {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking BBSWING_MODE**********\n");
for (p = ODM_RF_PATH_A; p < c->rf_path_count; p++)
(*c->odm_tx_pwr_track_set_pwr)(dm, BBSWING, p,
indexforchannel);
}
}
void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8822B)
configure_txpower_track_8822b(config);
}
/* **********************************************************************
* <20121113, Kordan> This function should be called when tx_agc changed.
* Otherwise the previous compensation is gone, because we record the
* delta of temperature between two TxPowerTracking watch dogs.
*
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
* need to call this function.
* ***********************************************************************/
void odm_clear_txpowertracking_state(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
u8 p = 0;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
dm->rf_calibrate_info.CCK_index = 0;
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
cali_info->bb_swing_idx_ofdm_base[p] =
cali_info->default_ofdm_index;
cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
cali_info->power_index_offset[p] = 0;
cali_info->delta_power_index[p] = 0;
cali_info->delta_power_index_last[p] = 0;
cali_info->absolute_ofdm_swing_idx[p] =
0; /* Initial Mix mode power tracking*/
cali_info->remnant_ofdm_swing_idx[p] = 0;
cali_info->kfree_offset[p] = 0;
}
cali_info->modify_tx_agc_flag_path_a =
false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_b =
false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_c =
false; /*Initial at Modify Tx Scaling mode*/
cali_info->modify_tx_agc_flag_path_d =
false; /*Initial at Modify Tx Scaling mode*/
cali_info->remnant_cck_swing_idx = 0;
cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
}
void odm_txpowertracking_callback_thermal_meter(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
void *adapter = dm->adapter;
struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
s8 diff_DPK[4]; /* use 'for..loop' to initialize */
u8 thermal_value_avg_count = 0;
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
/* OFDM BB Swing should be less than +3.0dB (required by Arthur) */
u8 OFDM_min_index = 0;
/* get_right_chnl_place_for_iqk(hal_data->current_channel) */
u8 indexforchannel = 0;
u8 power_tracking_type = 0; /* no specify type */
u8 xtal_offset_eanble = 0;
struct txpwrtrack_cfg c;
/* 4 1. The following TWO tables decide the final index of
* OFDM/CCK swing table.
*/
u8 *delta_swing_table_idx_tup_a = NULL;
u8 *delta_swing_table_idx_tdown_a = NULL;
u8 *delta_swing_table_idx_tup_b = NULL;
u8 *delta_swing_table_idx_tdown_b = NULL;
/*for 8814 add by Yu Chen*/
u8 *delta_swing_table_idx_tup_c = NULL;
u8 *delta_swing_table_idx_tdown_c = NULL;
u8 *delta_swing_table_idx_tup_d = NULL;
u8 *delta_swing_table_idx_tdown_d = NULL;
/*for Xtal Offset by James.Tung*/
s8 *delta_swing_table_xtal_up = NULL;
s8 *delta_swing_table_xtal_down = NULL;
/* 4 2. Initialization ( 7 steps in total ) */
configure_txpower_track(dm, &c);
(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a,
(u8 **)&delta_swing_table_idx_tdown_a,
(u8 **)&delta_swing_table_idx_tup_b,
(u8 **)&delta_swing_table_idx_tdown_b);
if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
(*c.get_delta_swing_table8814only)(
dm, (u8 **)&delta_swing_table_idx_tup_c,
(u8 **)&delta_swing_table_idx_tdown_c,
(u8 **)&delta_swing_table_idx_tup_d,
(u8 **)&delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
(*c.get_delta_swing_xtal_table)(
dm, (s8 **)&delta_swing_table_xtal_up,
(s8 **)&delta_swing_table_xtal_down);
cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
cali_info->is_txpowertracking_init = true;
/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
*<Kordan> We should keep updating ctrl variable according to HalData.
*<Kordan> rf_calibrate_info.rega24 will be initialized when
*ODM HW configuring, but MP configures with para files.
*/
if (dm->mp_mode)
cali_info->rega24 = 0x090e1317;
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"===>%s\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
__func__, cali_info->bb_swing_idx_cck_base,
cali_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A],
cali_info->default_ofdm_index);
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n",
cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter);
thermal_value =
(u8)odm_get_rf_reg(dm, ODM_RF_PATH_A, c.thermal_reg_addr,
0xfc00); /* 0x42: RF Reg[15:10] 88E */
/*add log by zhao he, check c80/c94/c14/ca0 value*/
if (dm->support_ic_type == ODM_RTL8723D) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
ODM_RT_TRACE(
dm, ODM_COMP_CALIBRATION,
"0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
regc80, regcd0, regcd4, regab4);
}
/* JJ ADD 20161014 */
if (dm->support_ic_type == ODM_RTL8710B) {
regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
ODM_RT_TRACE(
dm, ODM_COMP_CALIBRATION,
"0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
regc80, regcd0, regcd4, regab4);
}
if (!cali_info->txpowertrack_control)
return;
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
if (cali_info->is_reloadtxpowerindex)
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"reload ofdm index for band switch\n");
/*4 4. Calculate average thermal meter*/
cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] =
thermal_value;
cali_info->thermal_value_avg_index++;
if (cali_info->thermal_value_avg_index ==
c.average_thermal_num) /*Average times = c.average_thermal_num*/
cali_info->thermal_value_avg_index = 0;
for (i = 0; i < c.average_thermal_num; i++) {
if (cali_info->thermal_value_avg[i]) {
thermal_value_avg += cali_info->thermal_value_avg[i];
thermal_value_avg_count++;
}
}
if (thermal_value_avg_count) {
/* Calculate Average thermal_value after average enough times */
thermal_value =
(u8)(thermal_value_avg / thermal_value_avg_count);
cali_info->thermal_value_delta =
thermal_value - rtlefu->eeprom_thermalmeter;
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
thermal_value, rtlefu->eeprom_thermalmeter);
}
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
/* "delta" is used to determine whether thermal value changes or not*/
delta = (thermal_value > cali_info->thermal_value) ?
(thermal_value - cali_info->thermal_value) :
(cali_info->thermal_value - thermal_value);
delta_LCK = (thermal_value > cali_info->thermal_value_lck) ?
(thermal_value - cali_info->thermal_value_lck) :
(cali_info->thermal_value_lck - thermal_value);
delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ?
(thermal_value - cali_info->thermal_value_iqk) :
(cali_info->thermal_value_iqk - thermal_value);
if (cali_info->thermal_value_iqk ==
0xff) { /*no PG, use thermal value for IQK*/
cali_info->thermal_value_iqk = thermal_value;
delta_IQK =
(thermal_value > cali_info->thermal_value_iqk) ?
(thermal_value - cali_info->thermal_value_iqk) :
(cali_info->thermal_value_iqk - thermal_value);
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"no PG, use thermal_value for IQK\n");
}
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
/*4 6. If necessary, do LCK.*/
if (!(dm->support_ic_type &
ODM_RTL8821)) { /*no PG, do LCK at initial status*/
if (cali_info->thermal_value_lck == 0xff) {
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"no PG, do LCK\n");
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if (!(dm->support_ic_type & ODM_RTL8814A) &&
c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
delta_LCK =
(thermal_value > cali_info->thermal_value_lck) ?
(thermal_value -
cali_info->thermal_value_lck) :
(cali_info->thermal_value_lck -
thermal_value);
}
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
delta, delta_LCK, delta_IQK);
/*Delta temperature is equal to or larger than 20 centigrade.*/
if (delta_LCK >= c.threshold_iqk) {
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_LCK(%d) >= threshold_iqk(%d)\n",
delta_LCK, c.threshold_iqk);
cali_info->thermal_value_lck = thermal_value;
/*Use RTLCK, so close power tracking driver LCK*/
if (!(dm->support_ic_type & ODM_RTL8814A) &&
c.phy_lc_calibrate)
(*c.phy_lc_calibrate)(dm);
}
}
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
if (delta > 0 && cali_info->txpowertrack_control) {
/* "delta" here is used to record the abs value of difference.*/
delta = thermal_value > rtlefu->eeprom_thermalmeter ?
(thermal_value - rtlefu->eeprom_thermalmeter) :
(rtlefu->eeprom_thermalmeter - thermal_value);
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
if (thermal_value > rtlefu->eeprom_thermalmeter) {
phydm_set_calibrate_info_up(
dm, &c, delta, cali_info,
delta_swing_table_idx_tup_a,
delta_swing_table_idx_tup_b,
delta_swing_table_idx_tup_c,
delta_swing_table_idx_tup_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
/*recording last Xtal offset*/
cali_info->xtal_offset_last =
cali_info->xtal_offset;
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_up[%d] = %d\n",
delta,
delta_swing_table_xtal_up[delta]);
cali_info->xtal_offset =
delta_swing_table_xtal_up[delta];
xtal_offset_eanble =
(cali_info->xtal_offset_last ==
cali_info->xtal_offset) ?
0 :
1;
}
} else {
phydm_set_calibrate_info_down(
dm, &c, delta, cali_info,
delta_swing_table_idx_tdown_a,
delta_swing_table_idx_tdown_b,
delta_swing_table_idx_tdown_c,
delta_swing_table_idx_tdown_d);
/* JJ ADD 20161014 */
if (dm->support_ic_type &
(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
/*Save xtal_offset from Xtal table*/
/*recording last Xtal offset*/
cali_info->xtal_offset_last =
cali_info->xtal_offset;
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"[Xtal] delta_swing_table_xtal_down[%d] = %d\n",
delta,
delta_swing_table_xtal_down[delta]);
cali_info->xtal_offset =
delta_swing_table_xtal_down[delta];
xtal_offset_eanble =
(cali_info->xtal_offset_last ==
cali_info->xtal_offset) ?
0 :
1;
}
}
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n",
p);
if (cali_info->delta_power_index[p] ==
cali_info->delta_power_index_last[p]) {
/* If Thermal value changes but lookup table
* value still the same
*/
cali_info->power_index_offset[p] = 0;
} else {
/*Power idx diff between 2 times Pwr Tracking*/
cali_info->power_index_offset[p] =
cali_info->delta_power_index[p] -
cali_info->delta_power_index_last[p];
}
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n",
p, cali_info->power_index_offset[p],
cali_info->delta_power_index[p],
cali_info->delta_power_index_last[p]);
cali_info->OFDM_index[p] =
cali_info->bb_swing_idx_ofdm_base[p] +
cali_info->power_index_offset[p];
cali_info->CCK_index =
cali_info->bb_swing_idx_cck_base +
cali_info->power_index_offset[p];
cali_info->bb_swing_idx_cck = cali_info->CCK_index;
cali_info->bb_swing_idx_ofdm[p] =
cali_info->OFDM_index[p];
/*******Print BB Swing base and index Offset**********/
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
cali_info->bb_swing_idx_cck,
cali_info->bb_swing_idx_cck_base,
cali_info->power_index_offset[p]);
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
cali_info->bb_swing_idx_ofdm[p], p,
cali_info->bb_swing_idx_ofdm_base[p],
cali_info->power_index_offset[p]);
/*4 7.1 Handle boundary conditions of index.*/
if (cali_info->OFDM_index[p] >
c.swing_table_size_ofdm - 1)
cali_info->OFDM_index[p] =
c.swing_table_size_ofdm - 1;
else if (cali_info->OFDM_index[p] <= OFDM_min_index)
cali_info->OFDM_index[p] = OFDM_min_index;
}
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"\n\n========================================================================================================\n");
if (cali_info->CCK_index > c.swing_table_size_cck - 1)
cali_info->CCK_index = c.swing_table_size_cck - 1;
else if (cali_info->CCK_index <= 0)
cali_info->CCK_index = 0;
} else {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
cali_info->txpowertrack_control, thermal_value,
cali_info->thermal_value);
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
cali_info->power_index_offset[p] = 0;
}
/*Print Swing base & current*/
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
cali_info->OFDM_index[p], p,
cali_info->bb_swing_idx_ofdm_base[p]);
if ((dm->support_ic_type & ODM_RTL8814A)) {
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"power_tracking_type=%d\n", power_tracking_type);
if (power_tracking_type == 0) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking MIX_MODE**********\n");
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
0);
} else if (power_tracking_type == 1) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(
dm, MIX_2G_TSSI_5G_MODE, p, 0);
} else if (power_tracking_type == 2) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(
dm, MIX_5G_TSSI_2G_MODE, p, 0);
} else if (power_tracking_type == 3) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter POWER Tracking TSSI MODE**********\n");
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p,
0);
}
/*Record last Power Tracking Thermal value*/
cali_info->thermal_value = thermal_value;
} else if ((cali_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
cali_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
cali_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
cali_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
cali_info->txpowertrack_control &&
(rtlefu->eeprom_thermalmeter != 0xff)) {
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
/*Always true after Tx Power is adjusted by power tracking.*/
cali_info->is_tx_power_changed = true;
/* 2012/04/23 MH According to Luke's suggestion, we can not
* write BB digital to increase TX power. Otherwise, EVM will
* be bad.
*/
/* 2012/04/25 MH Add for tx power tracking to set tx power in
* tx agc for 88E.
*/
if (thermal_value > cali_info->thermal_value) {
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
/* print temperature increasing */
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p],
delta, thermal_value,
rtlefu->eeprom_thermalmeter,
cali_info->thermal_value);
}
} else if (thermal_value <
cali_info->thermal_value) { /*Low temperature*/
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
/* print temperature decreasing */
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
p, cali_info->power_index_offset[p],
delta, thermal_value,
rtlefu->eeprom_thermalmeter,
cali_info->thermal_value);
}
}
if (thermal_value > rtlefu->eeprom_thermalmeter) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n",
thermal_value, rtlefu->eeprom_thermalmeter);
phydm_odm_tx_power_set(dm, &c, indexforchannel, 0);
} else {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n",
thermal_value, rtlefu->eeprom_thermalmeter);
phydm_odm_tx_power_set(dm, &c, indexforchannel, 1);
}
/*Record last time Power Tracking result as base.*/
cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
cali_info->bb_swing_idx_ofdm_base[p] =
cali_info->bb_swing_idx_ofdm[p];
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"cali_info->thermal_value = %d thermal_value= %d\n",
cali_info->thermal_value, thermal_value);
/*Record last Power Tracking Thermal value*/
cali_info->thermal_value = thermal_value;
}
if (dm->support_ic_type == ODM_RTL8703B ||
dm->support_ic_type == ODM_RTL8723D ||
dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
if (xtal_offset_eanble != 0 &&
cali_info->txpowertrack_control &&
rtlefu->eeprom_thermalmeter != 0xff) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"**********Enter Xtal Tracking**********\n");
if (thermal_value > rtlefu->eeprom_thermalmeter) {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) higher than PG value(%d)\n",
thermal_value,
rtlefu->eeprom_thermalmeter);
(*c.odm_txxtaltrack_set_xtal)(dm);
} else {
ODM_RT_TRACE(
dm, ODM_COMP_TX_PWR_TRACK,
"Temperature(%d) lower than PG value(%d)\n",
thermal_value,
rtlefu->eeprom_thermalmeter);
(*c.odm_txxtaltrack_set_xtal)(dm);
}
}
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"**********End Xtal Tracking**********\n");
}
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
/* Delta temperature is equal to or larger than 20 centigrade
* (When threshold is 8).
*/
if (delta_IQK >= c.threshold_iqk) {
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK,
"delta_IQK(%d) >= threshold_iqk(%d)\n",
delta_IQK, c.threshold_iqk);
if (!cali_info->is_iqk_in_progress)
(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
}
}
if (cali_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(
dm, 0xcc4,
BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
(diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 +
(diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
BIT(11) | BIT(10),
value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) |
BIT(11) | BIT(10),
0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
if (cali_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(
dm, 0xec4,
BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10),
(diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
s32 value = 0x20 +
(diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
BIT(11) | BIT(10),
value);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) |
BIT(11) | BIT(10),
0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
}
}
ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "<===%s\n", __func__);
cali_info->tx_powercount = 0;
}
/* 3============================================================
* 3 IQ Calibration
* 3============================================================
*/
void odm_reset_iqk_result(void *dm_void) { return; }
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
{
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136,
138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165};
u8 place = chnl;
if (chnl > 14) {
for (place = 14; place < sizeof(channel_all); place++) {
if (channel_all[place] == chnl)
return place - 13;
}
}
return 0;
}
static void odm_iq_calibrate(struct phy_dm_struct *dm)
{
void *adapter = dm->adapter;
if (IS_HARDWARE_TYPE_8812AU(adapter))
return;
if (dm->is_linked) {
if ((*dm->channel != dm->pre_channel) &&
(!*dm->is_scan_in_process)) {
dm->pre_channel = *dm->channel;
dm->linked_interval = 0;
}
if (dm->linked_interval < 3)
dm->linked_interval++;
if (dm->linked_interval == 2) {
if (IS_HARDWARE_TYPE_8814A(adapter))
;
else if (IS_HARDWARE_TYPE_8822B(adapter))
phy_iq_calibrate_8822b(dm, false);
}
} else {
dm->linked_interval = 0;
}
}
void phydm_rf_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
odm_txpowertracking_init(dm);
odm_clear_txpowertracking_state(dm);
}
void phydm_rf_watchdog(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
odm_txpowertracking_check(dm);
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_iq_calibrate(dm);
}

74
drivers/staging/rtlwifi/phydm/halphyrf_ce.h
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@ -1,74 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#include "phydm_kfree.h"
#include "rtl8822b/phydm_iqk_8822b.h"
#include "phydm_powertracking_ce.h"
enum spur_cal_method { PLL_RESET, AFE_PHASE_SEL };
enum pwrtrack_method {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE,
MIX_2G_TSSI_5G_MODE,
MIX_5G_TSSI_2G_MODE
};
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
typedef void (*func_iqk)(void *, u8, u8, u8);
typedef void (*func_lck)(void *);
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
typedef void (*func_set_xtal)(void *);
struct txpwrtrack_cfg {
u8 swing_table_size_cck;
u8 swing_table_size_ofdm;
u8 threshold_iqk;
u8 threshold_dpk;
u8 average_thermal_num;
u8 rf_path_count;
u32 thermal_reg_addr;
func_set_pwr odm_tx_pwr_track_set_pwr;
func_iqk do_iqk;
func_lck phy_lc_calibrate;
func_swing get_delta_swing_table;
func_swing8814only get_delta_swing_table8814only;
func_swing_xtal get_delta_swing_xtal_table;
func_set_xtal odm_txxtaltrack_set_xtal;
};
void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
void odm_clear_txpowertracking_state(void *dm_void);
void odm_txpowertracking_callback_thermal_meter(void *dm);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void odm_reset_iqk_result(void *dm_void);
u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
void phydm_rf_init(void *dm_void);
void phydm_rf_watchdog(void *dm_void);
#endif /* #ifndef __HAL_PHY_RF_H__ */

13
drivers/staging/rtlwifi/phydm/mp_precomp.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/

1967
drivers/staging/rtlwifi/phydm/phydm.c
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File diff suppressed because it is too large Load Diff

935
drivers/staging/rtlwifi/phydm/phydm.h
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@ -1,935 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALDMOUTSRC_H__
#define __HALDMOUTSRC_H__
/*============================================================*/
/*include files*/
/*============================================================*/
#include "phydm_pre_define.h"
#include "phydm_dig.h"
#include "phydm_edcaturbocheck.h"
#include "phydm_antdiv.h"
#include "phydm_dynamicbbpowersaving.h"
#include "phydm_rainfo.h"
#include "phydm_dynamictxpower.h"
#include "phydm_cfotracking.h"
#include "phydm_acs.h"
#include "phydm_adaptivity.h"
#include "phydm_iqk.h"
#include "phydm_dfs.h"
#include "phydm_ccx.h"
#include "txbf/phydm_hal_txbf_api.h"
#include "phydm_adc_sampling.h"
#include "phydm_dynamic_rx_path.h"
#include "phydm_psd.h"
#include "phydm_beamforming.h"
#include "phydm_noisemonitor.h"
#include "halphyrf_ce.h"
/*============================================================*/
/*Definition */
/*============================================================*/
/* Traffic load decision */
#define TRAFFIC_ULTRA_LOW 1
#define TRAFFIC_LOW 2
#define TRAFFIC_MID 3
#define TRAFFIC_HIGH 4
#define NONE 0
/*NBI API------------------------------------*/
#define NBI_ENABLE 1
#define NBI_DISABLE 2
#define NBI_TABLE_SIZE_128 27
#define NBI_TABLE_SIZE_256 59
#define NUM_START_CH_80M 7
#define NUM_START_CH_40M 14
#define CH_OFFSET_40M 2
#define CH_OFFSET_80M 6
/*CSI MASK API------------------------------------*/
#define CSI_MASK_ENABLE 1
#define CSI_MASK_DISABLE 2
/*------------------------------------------------*/
#define FFT_128_TYPE 1
#define FFT_256_TYPE 2
#define SET_SUCCESS 1
#define SET_ERROR 2
#define SET_NO_NEED 3
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
#define PHYDM_WATCH_DOG_PERIOD 2
/*============================================================*/
/*structure and define*/
/*============================================================*/
/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
/*We need to remove to other position???*/
struct rtl8192cd_priv {
u8 temp;
};
struct dyn_primary_cca {
u8 pri_cca_flag;
u8 intf_flag;
u8 intf_type;
u8 dup_rts_flag;
u8 monitor_flag;
u8 ch_offset;
u8 mf_state;
};
#define dm_type_by_fw 0
#define dm_type_by_driver 1
/*Declare for common info*/
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
struct dm_phy_status_info {
/* */
/* Be care, if you want to add any element please insert between */
/* rx_pwdb_all & signal_strength. */
/* */
u8 rx_pwdb_all;
u8 signal_quality; /* in 0-100 index. */
s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
s16 cfo_short[4]; /* per-path's cfo_short */
s16 cfo_tail[4]; /* per-path's cfo_tail */
s8 rx_power; /* in dBm Translate from PWdB */
s8 recv_signal_power; /* Real power in dBm for this packet,
* no beautification and aggregation.
* Keep this raw info to be used for the other
* procedures.
*/
u8 bt_rx_rssi_percentage;
u8 signal_strength; /* in 0-100 index. */
s8 rx_pwr[4]; /* per-path's pwdb */
s8 rx_snr[4]; /* per-path's SNR */
/* s8 BB_Backup[13]; backup reg. */
u8 rx_count : 2; /* RX path counter---*/
u8 band_width : 2;
u8 rxsc : 4; /* sub-channel---*/
u8 bt_coex_pwr_adjust;
u8 channel; /* channel number---*/
bool is_mu_packet; /* is MU packet or not---*/
bool is_beamformed; /* BF packet---*/
};
struct dm_per_pkt_info {
u8 data_rate;
u8 station_id;
bool is_packet_match_bssid;
bool is_packet_to_self;
bool is_packet_beacon;
bool is_to_self;
u8 ppdu_cnt;
};
struct odm_phy_dbg_info {
/*ODM Write,debug info*/
s8 rx_snr_db[4];
u32 num_qry_phy_status;
u32 num_qry_phy_status_cck;
u32 num_qry_phy_status_ofdm;
u32 num_qry_mu_pkt;
u32 num_qry_bf_pkt;
u32 num_qry_mu_vht_pkt[40];
u32 num_qry_vht_pkt[40];
bool is_ldpc_pkt;
bool is_stbc_pkt;
u8 num_of_ppdu[4];
u8 gid_num[4];
u8 num_qry_beacon_pkt;
/* Others */
s32 rx_evm[4];
};
/*2011/20/20 MH For MP driver RT_WLAN_STA = struct rtl_sta_info*/
/*Please declare below ODM relative info in your STA info structure.*/
struct odm_sta_info {
/*Driver Write*/
bool is_used; /*record the sta status link or not?*/
u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/
/*ODM Write*/
/*PHY_STATUS_INFO*/
u8 rssi_path[4];
u8 rssi_ave;
u8 RXEVM[4];
u8 RXSNR[4];
};
enum odm_cmninfo {
/*Fixed value*/
/*-----------HOOK BEFORE REG INIT-----------*/
ODM_CMNINFO_PLATFORM = 0,
ODM_CMNINFO_ABILITY,
ODM_CMNINFO_INTERFACE,
ODM_CMNINFO_MP_TEST_CHIP,
ODM_CMNINFO_IC_TYPE,
ODM_CMNINFO_CUT_VER,
ODM_CMNINFO_FAB_VER,
ODM_CMNINFO_RF_TYPE,
ODM_CMNINFO_RFE_TYPE,
ODM_CMNINFO_BOARD_TYPE,
ODM_CMNINFO_PACKAGE_TYPE,
ODM_CMNINFO_EXT_LNA,
ODM_CMNINFO_5G_EXT_LNA,
ODM_CMNINFO_EXT_PA,
ODM_CMNINFO_5G_EXT_PA,
ODM_CMNINFO_GPA,
ODM_CMNINFO_APA,
ODM_CMNINFO_GLNA,
ODM_CMNINFO_ALNA,
ODM_CMNINFO_EXT_TRSW,
ODM_CMNINFO_DPK_EN,
ODM_CMNINFO_EXT_LNA_GAIN,
ODM_CMNINFO_PATCH_ID,
ODM_CMNINFO_BINHCT_TEST,
ODM_CMNINFO_BWIFI_TEST,
ODM_CMNINFO_SMART_CONCURRENT,
ODM_CMNINFO_CONFIG_BB_RF,
ODM_CMNINFO_DOMAIN_CODE_2G,
ODM_CMNINFO_DOMAIN_CODE_5G,
ODM_CMNINFO_IQKFWOFFLOAD,
ODM_CMNINFO_IQKPAOFF,
ODM_CMNINFO_HUBUSBMODE,
ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
ODM_CMNINFO_TX_TP,
ODM_CMNINFO_RX_TP,
ODM_CMNINFO_SOUNDING_SEQ,
ODM_CMNINFO_REGRFKFREEENABLE,
ODM_CMNINFO_RFKFREEENABLE,
ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
ODM_CMNINFO_EFUSE0X3D8,
ODM_CMNINFO_EFUSE0X3D7,
/*-----------HOOK BEFORE REG INIT-----------*/
/*Dynamic value:*/
/*--------- POINTER REFERENCE-----------*/
ODM_CMNINFO_MAC_PHY_MODE,
ODM_CMNINFO_TX_UNI,
ODM_CMNINFO_RX_UNI,
ODM_CMNINFO_WM_MODE,
ODM_CMNINFO_BAND,
ODM_CMNINFO_SEC_CHNL_OFFSET,
ODM_CMNINFO_SEC_MODE,
ODM_CMNINFO_BW,
ODM_CMNINFO_CHNL,
ODM_CMNINFO_FORCED_RATE,
ODM_CMNINFO_ANT_DIV,
ODM_CMNINFO_ADAPTIVITY,
ODM_CMNINFO_DMSP_GET_VALUE,
ODM_CMNINFO_BUDDY_ADAPTOR,
ODM_CMNINFO_DMSP_IS_MASTER,
ODM_CMNINFO_SCAN,
ODM_CMNINFO_POWER_SAVING,
ODM_CMNINFO_ONE_PATH_CCA,
ODM_CMNINFO_DRV_STOP,
ODM_CMNINFO_PNP_IN,
ODM_CMNINFO_INIT_ON,
ODM_CMNINFO_ANT_TEST,
ODM_CMNINFO_NET_CLOSED,
ODM_CMNINFO_FORCED_IGI_LB,
ODM_CMNINFO_P2P_LINK,
ODM_CMNINFO_FCS_MODE,
ODM_CMNINFO_IS1ANTENNA,
ODM_CMNINFO_RFDEFAULTPATH,
ODM_CMNINFO_DFS_MASTER_ENABLE,
ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
/*--------- POINTER REFERENCE-----------*/
/*------------CALL BY VALUE-------------*/
ODM_CMNINFO_WIFI_DIRECT,
ODM_CMNINFO_WIFI_DISPLAY,
ODM_CMNINFO_LINK_IN_PROGRESS,
ODM_CMNINFO_LINK,
ODM_CMNINFO_CMW500LINK,
ODM_CMNINFO_LPSPG,
ODM_CMNINFO_STATION_STATE,
ODM_CMNINFO_RSSI_MIN,
ODM_CMNINFO_DBG_COMP,
ODM_CMNINFO_DBG_LEVEL,
ODM_CMNINFO_RA_THRESHOLD_HIGH,
ODM_CMNINFO_RA_THRESHOLD_LOW,
ODM_CMNINFO_RF_ANTENNA_TYPE,
ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
ODM_CMNINFO_BE_FIX_TX_ANT,
ODM_CMNINFO_BT_ENABLED,
ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
ODM_CMNINFO_BT_HS_RSSI,
ODM_CMNINFO_BT_OPERATION,
ODM_CMNINFO_BT_LIMITED_DIG,
ODM_CMNINFO_BT_DIG,
ODM_CMNINFO_BT_BUSY,
ODM_CMNINFO_BT_DISABLE_EDCA,
ODM_CMNINFO_AP_TOTAL_NUM,
ODM_CMNINFO_POWER_TRAINING,
ODM_CMNINFO_DFS_REGION_DOMAIN,
/*------------CALL BY VALUE-------------*/
/*Dynamic ptr array hook itms.*/
ODM_CMNINFO_STA_STATUS,
ODM_CMNINFO_MAX,
};
enum phydm_info_query {
PHYDM_INFO_FA_OFDM,
PHYDM_INFO_FA_CCK,
PHYDM_INFO_FA_TOTAL,
PHYDM_INFO_CCA_OFDM,
PHYDM_INFO_CCA_CCK,
PHYDM_INFO_CCA_ALL,
PHYDM_INFO_CRC32_OK_VHT,
PHYDM_INFO_CRC32_OK_HT,
PHYDM_INFO_CRC32_OK_LEGACY,
PHYDM_INFO_CRC32_OK_CCK,
PHYDM_INFO_CRC32_ERROR_VHT,
PHYDM_INFO_CRC32_ERROR_HT,
PHYDM_INFO_CRC32_ERROR_LEGACY,
PHYDM_INFO_CRC32_ERROR_CCK,
PHYDM_INFO_EDCCA_FLAG,
PHYDM_INFO_OFDM_ENABLE,
PHYDM_INFO_CCK_ENABLE,
PHYDM_INFO_DBG_PORT_0
};
enum phydm_api {
PHYDM_API_NBI = 1,
PHYDM_API_CSI_MASK,
};
/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
enum odm_ability {
/*BB ODM section BIT 0-19*/
ODM_BB_DIG = BIT(0),
ODM_BB_RA_MASK = BIT(1),
ODM_BB_DYNAMIC_TXPWR = BIT(2),
ODM_BB_FA_CNT = BIT(3),
ODM_BB_RSSI_MONITOR = BIT(4),
ODM_BB_CCK_PD = BIT(5),
ODM_BB_ANT_DIV = BIT(6),
ODM_BB_PWR_TRAIN = BIT(8),
ODM_BB_RATE_ADAPTIVE = BIT(9),
ODM_BB_PATH_DIV = BIT(10),
ODM_BB_ADAPTIVITY = BIT(13),
ODM_BB_CFO_TRACKING = BIT(14),
ODM_BB_NHM_CNT = BIT(15),
ODM_BB_PRIMARY_CCA = BIT(16),
ODM_BB_TXBF = BIT(17),
ODM_BB_DYNAMIC_ARFR = BIT(18),
ODM_MAC_EDCA_TURBO = BIT(20),
ODM_BB_DYNAMIC_RX_PATH = BIT(21),
/*RF ODM section BIT 24-31*/
ODM_RF_TX_PWR_TRACK = BIT(24),
ODM_RF_RX_GAIN_TRACK = BIT(25),
ODM_RF_CALIBRATION = BIT(26),
};
/*ODM_CMNINFO_ONE_PATH_CCA*/
enum odm_cca_path {
ODM_CCA_2R = 0,
ODM_CCA_1R_A = 1,
ODM_CCA_1R_B = 2,
};
enum cca_pathdiv_en {
CCA_PATHDIV_DISABLE = 0,
CCA_PATHDIV_ENABLE = 1,
};
enum phy_reg_pg_type {
PHY_REG_PG_RELATIVE_VALUE = 0,
PHY_REG_PG_EXACT_VALUE = 1
};
/*2011/09/22 MH Copy from SD4 defined structure.
*We use to support PHY DM integration.
*/
struct phy_dm_struct {
/*Add for different team use temporarily*/
void *adapter; /*For CE/NIC team*/
struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
/*When you use adapter or priv pointer,
*you must make sure the pointer is ready.
*/
bool odm_ready;
struct rtl8192cd_priv fake_priv;
enum phy_reg_pg_type phy_reg_pg_value_type;
u8 phy_reg_pg_version;
u32 debug_components;
u32 fw_debug_components;
u32 debug_level;
u32 num_qry_phy_status_all; /*CCK + OFDM*/
u32 last_num_qry_phy_status_all;
u32 rx_pwdb_ave;
bool MPDIG_2G; /*off MPDIG*/
u8 times_2g;
bool is_init_hw_info_by_rfe;
/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
bool is_cck_high_power;
u8 rf_path_rx_enable;
u8 control_channel;
/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
/* 1 COMMON INFORMATION */
/*Init value*/
/*-----------HOOK BEFORE REG INIT-----------*/
/*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
u8 support_platform;
/* ODM Platform info WIN/AP/CE = 1/2/3 */
u8 normal_rx_path;
/*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ... = 1/2/3/...*/
u32 support_ability;
/*ODM PCIE/USB/SDIO = 1/2/3*/
u8 support_interface;
/*ODM composite or independent. Bit oriented/ 92C+92D+ .... or
*any other type = 1/2/3/...
*/
u32 support_ic_type;
/*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
u8 cut_version;
/*Fab version TSMC/UMC = 0/1*/
u8 fab_version;
/*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
u8 rf_type;
u8 rfe_type;
/*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
/*Enable Function DPK OFF/ON = 0/1*/
u8 dpk_en;
u8 board_type;
u8 package_type;
u16 type_glna;
u16 type_gpa;
u16 type_alna;
u16 type_apa;
/*with external LNA NO/Yes = 0/1*/
u8 ext_lna; /*2G*/
u8 ext_lna_5g; /*5G*/
/*with external PA NO/Yes = 0/1*/
u8 ext_pa; /*2G*/
u8 ext_pa_5g; /*5G*/
/*with Efuse number*/
u8 efuse0x3d7;
u8 efuse0x3d8;
/*with external TRSW NO/Yes = 0/1*/
u8 ext_trsw;
u8 ext_lna_gain; /*2G*/
u8 patch_id; /*Customer ID*/
bool is_in_hct_test;
u8 wifi_test;
bool is_dual_mac_smart_concurrent;
u32 bk_support_ability;
u8 ant_div_type;
u8 with_extenal_ant_switch;
bool config_bbrf;
u8 odm_regulation_2_4g;
u8 odm_regulation_5g;
u8 iqk_fw_offload;
bool cck_new_agc;
u8 phydm_period;
u32 phydm_sys_up_time;
u8 num_rf_path;
/*-----------HOOK BEFORE REG INIT-----------*/
/*Dynamic value*/
/*--------- POINTER REFERENCE-----------*/
u8 u1_byte_temp;
bool BOOLEAN_temp;
void *PADAPTER_temp;
/*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
u8 *mac_phy_mode;
/*TX Unicast byte count*/
u64 *num_tx_bytes_unicast;
/*RX Unicast byte count*/
u64 *num_rx_bytes_unicast;
/*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
u8 *wireless_mode;
/*Frequence band 2.4G/5G = 0/1*/
u8 *band_type;
/*Secondary channel offset don't_care/below/above = 0/1/2*/
u8 *sec_ch_offset;
/*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
u8 *security;
/*BW info 20M/40M/80M = 0/1/2*/
u8 *band_width;
/*Central channel location Ch1/Ch2/....*/
u8 *channel; /*central channel number*/
bool dpk_done;
/*Common info for 92D DMSP*/
bool *is_get_value_from_other_mac;
void **buddy_adapter;
bool *is_master_of_dmsp; /* MAC0: master, MAC1: slave */
/*Common info for status*/
bool *is_scan_in_process;
bool *is_power_saving;
/*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
u8 *one_path_cca;
u8 *antenna_test;
bool *is_net_closed;
u8 *pu1_forced_igi_lb;
bool *is_fcs_mode_enable;
/*--------- For 8723B IQK-----------*/
bool *is_1_antenna;
u8 *rf_default_path;
/* 0:S1, 1:S0 */
/*--------- POINTER REFERENCE-----------*/
u16 *forced_data_rate;
u8 *enable_antdiv;
u8 *enable_adaptivity;
u8 *hub_usb_mode;
bool *is_fw_dw_rsvd_page_in_progress;
u32 *current_tx_tp;
u32 *current_rx_tp;
u8 *sounding_seq;
/*------------CALL BY VALUE-------------*/
bool is_link_in_process;
bool is_wifi_direct;
bool is_wifi_display;
bool is_linked;
bool is_linkedcmw500;
bool is_in_lps_pg;
bool bsta_state;
u8 rssi_min;
u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
bool is_mp_chip;
bool is_one_entry_only;
bool mp_mode;
u32 one_entry_macid;
u8 pre_number_linked_client;
u8 number_linked_client;
u8 pre_number_active_client;
u8 number_active_client;
/*Common info for BTDM*/
bool is_bt_enabled; /*BT is enabled*/
bool is_bt_connect_process; /*BT HS is under connection progress.*/
u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
bool is_bt_hs_operation; /*BT HS mode is under progress*/
u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
bool is_bt_disable_edca_turbo; /*Under some condition, don't enable*/
bool is_bt_busy; /*BT is busy.*/
bool is_bt_limited_dig; /*BT is busy.*/
bool is_disable_phy_api;
/*------------CALL BY VALUE-------------*/
u8 rssi_a;
u8 rssi_b;
u8 rssi_c;
u8 rssi_d;
u64 rssi_trsw;
u64 rssi_trsw_h;
u64 rssi_trsw_l;
u64 rssi_trsw_iso;
u8 tx_ant_status;
u8 rx_ant_status;
u8 cck_lna_idx;
u8 cck_vga_idx;
u8 curr_station_id;
u8 ofdm_agc_idx[4];
u8 rx_rate;
bool is_noisy_state;
u8 tx_rate;
u8 linked_interval;
u8 pre_channel;
u32 txagc_offset_value_a;
bool is_txagc_offset_positive_a;
u32 txagc_offset_value_b;
bool is_txagc_offset_positive_b;
u32 tx_tp;
u32 rx_tp;
u32 total_tp;
u64 cur_tx_ok_cnt;
u64 cur_rx_ok_cnt;
u64 last_tx_ok_cnt;
u64 last_rx_ok_cnt;
u32 bb_swing_offset_a;
bool is_bb_swing_offset_positive_a;
u32 bb_swing_offset_b;
bool is_bb_swing_offset_positive_b;
u8 igi_lower_bound;
u8 igi_upper_bound;
u8 antdiv_rssi;
u8 fat_comb_a;
u8 fat_comb_b;
u8 antdiv_intvl;
u8 ant_type;
u8 pre_ant_type;
u8 antdiv_period;
u8 evm_antdiv_period;
u8 antdiv_select;
u8 path_select;
u8 antdiv_evm_en;
u8 bdc_holdstate;
u8 ndpa_period;
bool h2c_rarpt_connect;
bool cck_agc_report_type;
u8 dm_dig_max_TH;
u8 dm_dig_min_TH;
u8 print_agc;
u8 traffic_load;
u8 pre_traffic_load;
/*8821C Antenna BTG/WLG/WLA Select*/
u8 current_rf_set_8821c;
u8 default_rf_set_8821c;
/*For Adaptivtiy*/
u16 nhm_cnt_0;
u16 nhm_cnt_1;
s8 TH_L2H_default;
s8 th_edcca_hl_diff_default;
s8 th_l2h_ini;
s8 th_edcca_hl_diff;
s8 th_l2h_ini_mode2;
s8 th_edcca_hl_diff_mode2;
bool carrier_sense_enable;
u8 adaptivity_igi_upper;
bool adaptivity_flag;
u8 dc_backoff;
bool adaptivity_enable;
u8 ap_total_num;
bool edcca_enable;
u8 pre_dbg_priority;
struct adaptivity_statistics adaptivity;
/*For Adaptivtiy*/
u8 last_usb_hub;
u8 tx_bf_data_rate;
u8 nbi_set_result;
u8 c2h_cmd_start;
u8 fw_debug_trace[60];
u8 pre_c2h_seq;
bool fw_buff_is_enpty;
u32 data_frame_num;
/*for noise detection*/
bool noisy_decision; /*b_noisy*/
bool pre_b_noisy;
u32 noisy_decision_smooth;
bool is_disable_dym_ecs;
struct odm_noise_monitor noise_level;
/*Define STA info.*/
/*odm_sta_info*/
/*2012/01/12 MH For MP,
*we need to reduce one array pointer for default port.??
*/
struct rtl_sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
/* platform_macid_table[platform_macid] = phydm_macid */
s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
/*2012/02/14 MH Add to share 88E ra with other SW team.*/
/*We need to colelct all support abilit to a proper area.*/
bool ra_support88e;
struct odm_phy_dbg_info phy_dbg_info;
/*ODM Structure*/
struct fast_antenna_training dm_fat_table;
struct dig_thres dm_dig_table;
struct dyn_pwr_saving dm_ps_table;
struct dyn_primary_cca dm_pri_cca;
struct ra_table dm_ra_table;
struct false_alarm_stat false_alm_cnt;
struct false_alarm_stat flase_alm_cnt_buddy_adapter;
struct sw_antenna_switch dm_swat_table;
struct cfo_tracking dm_cfo_track;
struct acs_info dm_acs;
struct ccx_info dm_ccx_info;
struct psd_info dm_psd_table;
struct rt_adcsmp adcsmp;
struct dm_iqk_info IQK_info;
struct edca_turbo dm_edca_table;
u32 WMMEDCA_BE;
bool *is_driver_stopped;
bool *is_driver_is_going_to_pnp_set_power_sleep;
bool *pinit_adpt_in_progress;
/*PSD*/
bool is_user_assign_level;
u8 RSSI_BT; /*come from BT*/
bool is_psd_in_process;
bool is_psd_active;
bool is_dm_initial_gain_enable;
/*MPT DIG*/
struct timer_list mpt_dig_timer;
/*for rate adaptive, in fact, 88c/92c fw will handle this*/
u8 is_use_ra_mask;
/* for dynamic SoML control */
bool bsomlenabled;
struct odm_rate_adaptive rate_adaptive;
struct dm_rf_calibration_struct rf_calibrate_info;
u32 n_iqk_cnt;
u32 n_iqk_ok_cnt;
u32 n_iqk_fail_cnt;
/*Power Training*/
u8 force_power_training_state;
bool is_change_state;
u32 PT_score;
u64 ofdm_rx_cnt;
u64 cck_rx_cnt;
bool is_disable_power_training;
u8 dynamic_tx_high_power_lvl;
u8 last_dtp_lvl;
u32 tx_agc_ofdm_18_6;
u8 rx_pkt_type;
/*ODM relative time.*/
struct timer_list path_div_switch_timer;
/*2011.09.27 add for path Diversity*/
struct timer_list cck_path_diversity_timer;
struct timer_list fast_ant_training_timer;
struct timer_list sbdcnt_timer;
/*ODM relative workitem.*/
};
enum phydm_structure_type {
PHYDM_FALSEALMCNT,
PHYDM_CFOTRACK,
PHYDM_ADAPTIVITY,
PHYDM_ROMINFO,
};
enum odm_rf_content {
odm_radioa_txt = 0x1000,
odm_radiob_txt = 0x1001,
odm_radioc_txt = 0x1002,
odm_radiod_txt = 0x1003
};
enum odm_bb_config_type {
CONFIG_BB_PHY_REG,
CONFIG_BB_AGC_TAB,
CONFIG_BB_AGC_TAB_2G,
CONFIG_BB_AGC_TAB_5G,
CONFIG_BB_PHY_REG_PG,
CONFIG_BB_PHY_REG_MP,
CONFIG_BB_AGC_TAB_DIFF,
};
enum odm_rf_config_type {
CONFIG_RF_RADIO,
CONFIG_RF_TXPWR_LMT,
};
enum odm_fw_config_type {
CONFIG_FW_NIC,
CONFIG_FW_NIC_2,
CONFIG_FW_AP,
CONFIG_FW_AP_2,
CONFIG_FW_MP,
CONFIG_FW_WOWLAN,
CONFIG_FW_WOWLAN_2,
CONFIG_FW_AP_WOWLAN,
CONFIG_FW_BT,
};
/*status code*/
enum rt_status {
RT_STATUS_SUCCESS,
RT_STATUS_FAILURE,
RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,
};
/*===========================================================*/
/*AGC RX High Power mode*/
/*===========================================================*/
#define lna_low_gain_1 0x64
#define lna_low_gain_2 0x5A
#define lna_low_gain_3 0x58
#define FA_RXHP_TH1 5000
#define FA_RXHP_TH2 1500
#define FA_RXHP_TH3 800
#define FA_RXHP_TH4 600
#define FA_RXHP_TH5 500
enum dm_1r_cca {
CCA_1R = 0,
CCA_2R = 1,
CCA_MAX = 2,
};
enum dm_rf {
rf_save = 0,
rf_normal = 1,
RF_MAX = 2,
};
/*check Sta pointer valid or not*/
#define IS_STA_VALID(sta) (sta)
u32 odm_convert_to_db(u32 value);
u32 odm_convert_to_linear(u32 value);
s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
s32 odm_sign_conversion(s32 value, u32 total_bit);
void odm_init_mp_driver_status(struct phy_dm_struct *dm);
void phydm_txcurrentcalibration(struct phy_dm_struct *dm);
void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
u8 seq_length);
void odm_dm_init(struct phy_dm_struct *dm);
void odm_dm_reset(struct phy_dm_struct *dm);
void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
char *output, u32 *_out_len);
void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path);
void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
char *output, u32 *_out_len);
void odm_dm_watchdog(struct phy_dm_struct *dm);
void phydm_watchdog_mp(struct phy_dm_struct *dm);
void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
u32 value);
void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
void *value);
void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
enum odm_cmninfo cmn_info, u16 index,
void *value);
void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value);
u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
enum phydm_info_query info_type);
void odm_init_all_timers(struct phy_dm_struct *dm);
void odm_cancel_all_timers(struct phy_dm_struct *dm);
void odm_release_all_timers(struct phy_dm_struct *dm);
void odm_asoc_entry_init(struct phy_dm_struct *dm);
void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type);
/*===========================================================*/
/* The following is for compile only*/
/*===========================================================*/
#define IS_HARDWARE_TYPE_8188E(_adapter) false
#define IS_HARDWARE_TYPE_8188F(_adapter) false
#define IS_HARDWARE_TYPE_8703B(_adapter) false
#define IS_HARDWARE_TYPE_8723D(_adapter) false
#define IS_HARDWARE_TYPE_8821C(_adapter) false
#define IS_HARDWARE_TYPE_8812AU(_adapter) false
#define IS_HARDWARE_TYPE_8814A(_adapter) false
#define IS_HARDWARE_TYPE_8814AU(_adapter) false
#define IS_HARDWARE_TYPE_8814AE(_adapter) false
#define IS_HARDWARE_TYPE_8814AS(_adapter) false
#define IS_HARDWARE_TYPE_8723BU(_adapter) false
#define IS_HARDWARE_TYPE_8822BU(_adapter) false
#define IS_HARDWARE_TYPE_8822BS(_adapter) false
#define IS_HARDWARE_TYPE_JAGUAR(_adapter) \
(IS_HARDWARE_TYPE_8812(_adapter) || IS_HARDWARE_TYPE_8821(_adapter))
#define IS_HARDWARE_TYPE_8723AE(_adapter) false
#define IS_HARDWARE_TYPE_8192C(_adapter) false
#define IS_HARDWARE_TYPE_8192D(_adapter) false
#define RF_T_METER_92D 0x42
#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) \
LE_BITS_TO_1BYTE(__prx_status_desc + 12, 0, 6)
#define REG_CONFIG_RAM64X16 0xb2c
#define TARGET_CHNL_NUM_2G_5G 59
/* *********************************************************** */
void odm_dtc(struct phy_dm_struct *dm);
void phydm_noisy_detection(struct phy_dm_struct *dm);
void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
char *output, u32 *_out_len);
void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
u32 *_used, char *output, u32 *_out_len);
u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
u32 f_interference, u32 second_ch);
#endif /* __HALDMOUTSRC_H__ */

189
drivers/staging/rtlwifi/phydm/phydm_acs.c
View File

@ -1,189 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* *************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
u8 odm_get_auto_channel_select_result(void *dm_void, u8 band)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct acs_info *acs = &dm->dm_acs;
u8 result;
if (band == ODM_BAND_2_4G) {
ODM_RT_TRACE(
dm, ODM_COMP_ACS,
"[struct acs_info] %s(): clean_channel_2g(%d)\n",
__func__, acs->clean_channel_2g);
result = (u8)acs->clean_channel_2g;
} else {
ODM_RT_TRACE(
dm, ODM_COMP_ACS,
"[struct acs_info] %s(): clean_channel_5g(%d)\n",
__func__, acs->clean_channel_5g);
result = (u8)acs->clean_channel_5g;
}
return result;
}
static void odm_auto_channel_select_setting(void *dm_void, bool is_enable)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u16 period = 0x2710; /* 40ms in default */
u16 nhm_type = 0x7;
ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
if (is_enable) {
/* 20 ms */
period = 0x1388;
nhm_type = 0x1;
}
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/* PHY parameters initialize for ac series */
/* 0x990[31:16]=0x2710
* Time duration for NHM unit: 4us, 0x2710=40ms
*/
odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
/* PHY parameters initialize for n series */
/* 0x894[31:16]=0x2710
* Time duration for NHM unit: 4us, 0x2710=40ms
*/
odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, period);
}
}
void odm_auto_channel_select_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct acs_info *acs = &dm->dm_acs;
u8 i;
if (!(dm->support_ability & ODM_BB_NHM_CNT))
return;
if (acs->is_force_acs_result)
return;
ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
acs->clean_channel_2g = 1;
acs->clean_channel_5g = 36;
for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
acs->channel_info_2g[0][i] = 0;
acs->channel_info_2g[1][i] = 0;
}
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
acs->channel_info_5g[0][i] = 0;
acs->channel_info_5g[1][i] = 0;
}
}
}
void odm_auto_channel_select_reset(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct acs_info *acs = &dm->dm_acs;
if (!(dm->support_ability & ODM_BB_NHM_CNT))
return;
if (acs->is_force_acs_result)
return;
ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
odm_auto_channel_select_setting(dm, true); /* for 20ms measurement */
phydm_nhm_counter_statistics_reset(dm);
}
void odm_auto_channel_select(void *dm_void, u8 channel)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct acs_info *acs = &dm->dm_acs;
u8 channel_idx = 0, search_idx = 0;
u16 max_score = 0;
if (!(dm->support_ability & ODM_BB_NHM_CNT)) {
ODM_RT_TRACE(
dm, ODM_COMP_DIG,
"%s(): Return: support_ability ODM_BB_NHM_CNT is disabled\n",
__func__);
return;
}
if (acs->is_force_acs_result) {
ODM_RT_TRACE(
dm, ODM_COMP_DIG,
"%s(): Force 2G clean channel = %d, 5G clean channel = %d\n",
__func__, acs->clean_channel_2g, acs->clean_channel_5g);
return;
}
ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): channel = %d=========>\n",
__func__, channel);
phydm_get_nhm_counter_statistics(dm);
odm_auto_channel_select_setting(dm, false);
if (channel >= 1 && channel <= 14) {
channel_idx = channel - 1;
acs->channel_info_2g[1][channel_idx]++;
if (acs->channel_info_2g[1][channel_idx] >= 2)
acs->channel_info_2g[0][channel_idx] =
(acs->channel_info_2g[0][channel_idx] >> 1) +
(acs->channel_info_2g[0][channel_idx] >> 2) +
(dm->nhm_cnt_0 >> 2);
else
acs->channel_info_2g[0][channel_idx] = dm->nhm_cnt_0;
ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): nhm_cnt_0 = %d\n",
__func__, dm->nhm_cnt_0);
ODM_RT_TRACE(
dm, ODM_COMP_ACS,
"%s(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n",
__func__, channel_idx,
acs->channel_info_2g[0][channel_idx], channel_idx,
acs->channel_info_2g[1][channel_idx]);
for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G;
search_idx++) {
if (acs->channel_info_2g[1][search_idx] != 0 &&
acs->channel_info_2g[0][search_idx] >= max_score) {
max_score = acs->channel_info_2g[0][search_idx];
acs->clean_channel_2g = search_idx + 1;
}
}
ODM_RT_TRACE(
dm, ODM_COMP_ACS,
"(1)%s(): 2G: clean_channel_2g = %d, max_score = %d\n",
__func__, acs->clean_channel_2g, max_score);
} else if (channel >= 36) {
/* Need to do */
acs->clean_channel_5g = channel;
}
}

46
drivers/staging/rtlwifi/phydm/phydm_acs.h
View File

@ -1,46 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
/* For phydm_auto_channel_select_setting_ap() */
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
struct acs_info {
bool is_force_acs_result;
u8 clean_channel_2g;
u8 clean_channel_5g;
/* channel_info[1]: channel score, channel_info[2]:channel_scan_times */
u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G];
u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
};
void odm_auto_channel_select_init(void *dm_void);
void odm_auto_channel_select_reset(void *dm_void);
void odm_auto_channel_select(void *dm_void, u8 channel);
u8 odm_get_auto_channel_select_result(void *dm_void, u8 band);
#endif /* #ifndef __PHYDMACS_H__ */

930
drivers/staging/rtlwifi/phydm/phydm_adaptivity.c
View File

@ -1,930 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* *************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
void phydm_check_adaptivity(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
if (dm->support_ability & ODM_BB_ADAPTIVITY) {
if (adaptivity->dynamic_link_adaptivity ||
adaptivity->acs_for_adaptivity) {
if (dm->is_linked && !adaptivity->is_check) {
phydm_nhm_counter_statistics(dm);
phydm_check_environment(dm);
} else if (!dm->is_linked) {
adaptivity->is_check = false;
}
} else {
dm->adaptivity_enable = true;
if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA |
ODM_IC_11N_GAIN_IDX_EDCCA))
dm->adaptivity_flag = false;
else
dm->adaptivity_flag = true;
}
} else {
dm->adaptivity_enable = false;
dm->adaptivity_flag = false;
}
}
void phydm_nhm_counter_statistics_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
/*PHY parameters initialize for n series*/
/*0x894[31:16]=0x0xC350
*Time duration for NHM unit: us, 0xc350=200ms
*/
odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350);
/*0x890[31:16]=0xffff th_9, th_10*/
odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
/*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);
/*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);
/*0xe28[7:0]=0xff th_8*/
odm_set_bb_reg(dm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff);
/*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N,
BIT(10) | BIT(9) | BIT(8), 0x1);
/*0xc0c[7]=1 max power among all RX ants*/
odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*PHY parameters initialize for ac series*/
odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350);
/*0x994[31:16]=0xffff th_9, th_10*/
odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
/*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);
/*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);
/*0x9a0[7:0]=0xff th_8*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff);
/*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC,
BIT(8) | BIT(9) | BIT(10), 0x1);
/*0x9e8[7]=1 max power among all RX ants*/
odm_set_bb_reg(dm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1);
}
}
void phydm_nhm_counter_statistics(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_NHM_CNT))
return;
/*Get NHM report*/
phydm_get_nhm_counter_statistics(dm);
/*Reset NHM counter*/
phydm_nhm_counter_statistics_reset(dm);
}
void phydm_get_nhm_counter_statistics(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u32 value32 = 0;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11AC, MASKDWORD);
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11N, MASKDWORD);
dm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0);
dm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8);
}
void phydm_nhm_counter_statistics_reset(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
}
}
void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
MASKBYTE2 | MASKBYTE0,
(u32)((u8)L2H | (u8)H2L << 16));
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
(u16)((u8)L2H | (u8)H2L << 8));
}
static void phydm_set_lna(void *dm_void, enum phydm_set_lna type)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
if (type == phydm_disable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0000f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0x37f82); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (dm->rf_type > ODM_1T1R) {
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
0x18000);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
0x0000f);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
0x37f82);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x0);
}
} else if (type == phydm_enable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0000f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0x77f82); /*back to normal*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (dm->rf_type > ODM_1T1R) {
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
0x18000);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
0x0000f);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
0x77f82);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x0);
}
}
} else if (dm->support_ic_type & ODM_RTL8723B) {
if (type == phydm_disable_lna) {
/*S0*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0001f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xe6137); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
odm_set_rf_reg(
dm, ODM_RF_PATH_A, 0x43, 0xfffff,
0x3008d); /*select Rx mode and disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
} else if (type == phydm_enable_lna) {
/*S0*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0001f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xe6177); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
odm_set_rf_reg(
dm, ODM_RF_PATH_A, 0x43, 0xfffff,
0x300bd); /*select Rx mode and disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
}
} else if (dm->support_ic_type & ODM_RTL8812) {
if (type == phydm_disable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x3f7ff);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xc22bf); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (dm->rf_type > ODM_1T1R) {
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
0x3f7ff);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
0xc22bf); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x0);
}
} else if (type == phydm_enable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x3f7ff);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xc26bf); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (dm->rf_type > ODM_1T1R) {
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
0x3f7ff);
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
0xc26bf); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
0x0);
}
}
} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
if (type == phydm_disable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0002f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xfb09b); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
} else if (type == phydm_enable_lna) {
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
0x0002f);
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
0xfb0bb); /*disable LNA*/
odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
}
}
}
void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
enum phydm_trx_mux_type rx_mode)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
/*set TXmod to standby mode to remove outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
BIT(3) | BIT(2) | BIT(1), tx_mode);
/*set RXmod to standby mode to remove outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
BIT(22) | BIT(21) | BIT(20), rx_mode);
if (dm->rf_type > ODM_1T1R) {
/*set TXmod to standby mode to rm outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
BIT(3) | BIT(2) | BIT(1), tx_mode);
/*set RXmod to standby mode to rm outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
BIT(22) | BIT(21) | BIT(20), rx_mode);
}
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*set TXmod to standby mode to remove outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode);
/*set RXmod to standby mode to remove outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode);
if (dm->rf_type > ODM_1T1R) {
/*set TXmod to standby mode to rm outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
BIT(11) | BIT(10) | BIT(9) | BIT(8),
tx_mode);
/*set RXmod to standby mode to rm outside noise affect*/
odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
BIT(7) | BIT(6) | BIT(5) | BIT(4),
rx_mode);
}
}
}
void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (state == phydm_ignore_edcca) {
/*ignore EDCCA reg520[15]=1*/
odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1);
} else { /*don't set MAC ignore EDCCA signal*/
/*don't ignore EDCCA reg520[15]=0*/
odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0);
}
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "EDCCA enable state = %d\n",
state);
}
bool phydm_cal_nhm_cnt(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u16 base = 0;
base = dm->nhm_cnt_0 + dm->nhm_cnt_1;
if (base != 0) {
dm->nhm_cnt_0 = ((dm->nhm_cnt_0) << 8) / base;
dm->nhm_cnt_1 = ((dm->nhm_cnt_1) << 8) / base;
}
if ((dm->nhm_cnt_0 - dm->nhm_cnt_1) >= 100)
return true; /*clean environment*/
else
return false; /*noisy environment*/
}
void phydm_check_environment(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
bool is_clean_environment = false;
if (adaptivity->is_first_link) {
if (dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
dm->adaptivity_flag = false;
else
dm->adaptivity_flag = true;
adaptivity->is_first_link = false;
return;
}
if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/
adaptivity->nhm_wait++;
phydm_nhm_counter_statistics(dm);
return;
}
phydm_nhm_counter_statistics(dm);
is_clean_environment = phydm_cal_nhm_cnt(dm);
if (is_clean_environment) {
dm->th_l2h_ini =
adaptivity->th_l2h_ini_backup; /*adaptivity mode*/
dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
dm->adaptivity_enable = true;
if (dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
dm->adaptivity_flag = false;
else
dm->adaptivity_flag = true;
} else {
if (!adaptivity->acs_for_adaptivity) {
dm->th_l2h_ini = dm->th_l2h_ini_mode2; /*mode2*/
dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
dm->adaptivity_flag = false;
dm->adaptivity_enable = false;
}
}
adaptivity->nhm_wait = 0;
adaptivity->is_first_link = true;
adaptivity->is_check = true;
}
void phydm_search_pwdb_lower_bound(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
u32 value32 = 0, reg_value32 = 0;
u8 cnt, try_count = 0;
u8 tx_edcca1 = 0, tx_edcca0 = 0;
bool is_adjust = true;
s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
s8 diff;
u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini -
(u8)dm->th_edcca_hl_diff;
if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
phydm_set_lna(dm, phydm_disable_lna);
} else {
phydm_set_trx_mux(dm, phydm_standby_mode, phydm_standby_mode);
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
}
diff = igi_target - (s8)IGI;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
ODM_delay_ms(30);
while (is_adjust) {
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
reg_value32 =
odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD,
0x0);
reg_value32 =
odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
}
while (reg_value32 & BIT(3) && try_count < 3) {
ODM_delay_ms(3);
try_count = try_count + 1;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
reg_value32 = odm_get_bb_reg(
dm, ODM_REG_RPT_11N, MASKDWORD);
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
reg_value32 = odm_get_bb_reg(
dm, ODM_REG_RPT_11AC, MASKDWORD);
}
try_count = 0;
for (cnt = 0; cnt < 20; cnt++) {
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N,
MASKDWORD, 0x208);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11N,
MASKDWORD);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC,
MASKDWORD, 0x209);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC,
MASKDWORD);
}
if (value32 & BIT(30) &&
(dm->support_ic_type &
(ODM_RTL8723B | ODM_RTL8188E)))
tx_edcca1 = tx_edcca1 + 1;
else if (value32 & BIT(29))
tx_edcca1 = tx_edcca1 + 1;
else
tx_edcca0 = tx_edcca0 + 1;
}
if (tx_edcca1 > 1) {
IGI = IGI - 1;
th_l2h_dmc = th_l2h_dmc + 1;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
if (th_l2h_dmc == 10) {
is_adjust = false;
adaptivity->h2l_lb = th_h2l_dmc;
adaptivity->l2h_lb = th_l2h_dmc;
dm->adaptivity_igi_upper = IGI;
}
tx_edcca1 = 0;
tx_edcca0 = 0;
} else {
is_adjust = false;
adaptivity->h2l_lb = th_h2l_dmc;
adaptivity->l2h_lb = th_l2h_dmc;
dm->adaptivity_igi_upper = IGI;
tx_edcca1 = 0;
tx_edcca0 = 0;
}
}
dm->adaptivity_igi_upper = dm->adaptivity_igi_upper - dm->dc_backoff;
adaptivity->h2l_lb = adaptivity->h2l_lb + dm->dc_backoff;
adaptivity->l2h_lb = adaptivity->l2h_lb + dm->dc_backoff;
if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
phydm_set_lna(dm, phydm_enable_lna);
} else {
phydm_set_trx_mux(dm, phydm_tx_mode, phydm_rx_mode);
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
}
phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
}
static bool phydm_re_search_condition(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u8 adaptivity_igi_upper;
u8 count = 0;
adaptivity_igi_upper = dm->adaptivity_igi_upper + dm->dc_backoff;
if (adaptivity_igi_upper <= 0x26 && count < 3) {
count = count + 1;
return true;
}
return false;
}
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
switch (cmn_info) {
case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
dm->carrier_sense_enable = (bool)value;
break;
case PHYDM_ADAPINFO_DCBACKOFF:
dm->dc_backoff = (u8)value;
break;
case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
adaptivity->dynamic_link_adaptivity = (bool)value;
break;
case PHYDM_ADAPINFO_TH_L2H_INI:
dm->th_l2h_ini = (s8)value;
break;
case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
dm->th_edcca_hl_diff = (s8)value;
break;
case PHYDM_ADAPINFO_AP_NUM_TH:
adaptivity->ap_num_th = (u8)value;
break;
default:
break;
}
}
void phydm_adaptivity_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
s8 igi_target = 0x32;
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
dm->th_l2h_ini = 0xf5;
} else {
dm->th_l2h_ini = 0xa;
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
if (dm->wifi_test || dm->mp_mode) {
/*even no adaptivity, we still enable EDCCA, AP use mib ctrl*/
dm->edcca_enable = false;
} else {
dm->edcca_enable = true;
}
dm->adaptivity_igi_upper = 0;
dm->adaptivity_enable =
false; /*use this flag to decide enable or disable*/
dm->th_l2h_ini_mode2 = 20;
dm->th_edcca_hl_diff_mode2 = 8;
adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
adaptivity->igi_base = 0x32;
adaptivity->igi_target = 0x1c;
adaptivity->h2l_lb = 0;
adaptivity->l2h_lb = 0;
adaptivity->nhm_wait = 0;
adaptivity->is_check = false;
adaptivity->is_first_link = true;
adaptivity->adajust_igi_level = 0;
adaptivity->is_stop_edcca = false;
adaptivity->backup_h2l = 0;
adaptivity->backup_l2h = 0;
phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca);
/*Search pwdB lower bound*/
if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
if (dm->support_ic_type & ODM_RTL8197F) {
/*set to page B1*/
odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1);
/*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F,
BIT(27) | BIT(26), 0x1);
odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
} else {
/*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N,
BIT(21) | BIT(20), 0x1);
}
}
/*8814a no need to find pwdB lower bound, maybe*/
if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) {
/*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE,
BIT(29) | BIT(28), 0x1);
}
if (!(dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
phydm_search_pwdb_lower_bound(dm);
if (phydm_re_search_condition(dm))
phydm_search_pwdb_lower_bound(dm);
}
/*we need to consider PwdB upper bound for 8814 later IC*/
adaptivity->adajust_igi_level =
(u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound +
dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n",
dm->th_l2h_ini, dm->th_edcca_hl_diff,
adaptivity->adajust_igi_level);
/*Check this later on Windows*/
/*phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);*/
}
void phydm_adaptivity(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct dig_thres *dig_tab = &dm->dm_dig_table;
u8 IGI = dig_tab->cur_ig_value;
s8 th_l2h_dmc, th_h2l_dmc;
s8 diff = 0, igi_target;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
if (!dm->edcca_enable || adaptivity->is_stop_edcca) {
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "Disable EDCCA!!!\n");
return;
}
if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
"adaptivity disable, enable EDCCA mode!!!\n");
dm->th_l2h_ini = dm->th_l2h_ini_mode2;
dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
}
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "%s() =====>\n", __func__);
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
"igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
adaptivity->igi_base, dm->th_l2h_ini,
dm->th_edcca_hl_diff);
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*fix AC series when enable EDCCA hang issue*/
odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
}
if (*dm->band_width == ODM_BW20M) /*CHANNEL_WIDTH_20*/
igi_target = adaptivity->igi_base;
else if (*dm->band_width == ODM_BW40M)
igi_target = adaptivity->igi_base + 2;
else if (*dm->band_width == ODM_BW80M)
igi_target = adaptivity->igi_base + 2;
else
igi_target = adaptivity->igi_base;
adaptivity->igi_target = (u8)igi_target;
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n",
(*dm->band_width == ODM_BW80M) ?
"80M" :
((*dm->band_width == ODM_BW40M) ? "40M" : "20M"),
igi_target, adaptivity->dynamic_link_adaptivity,
adaptivity->acs_for_adaptivity);
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"rssi_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
dm->rssi_min, adaptivity->adajust_igi_level,
dm->adaptivity_flag, dm->adaptivity_enable);
if (adaptivity->dynamic_link_adaptivity && !dm->is_linked &&
!dm->adaptivity_enable) {
phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n");
return;
}
if (dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
if (adaptivity->adajust_igi_level > IGI &&
dm->adaptivity_enable)
diff = adaptivity->adajust_igi_level - IGI;
th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
} else {
diff = igi_target - (s8)IGI;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10 && dm->adaptivity_enable)
th_l2h_dmc = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l_dmc < adaptivity->h2l_lb)
th_h2l_dmc = adaptivity->h2l_lb;
if (th_l2h_dmc < adaptivity->l2h_lb)
th_l2h_dmc = adaptivity->l2h_lb;
}
ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
"IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI,
th_l2h_dmc, th_h2l_dmc);
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
dm->adaptivity_igi_upper, adaptivity->h2l_lb,
adaptivity->l2h_lb);
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
if (dm->adaptivity_enable)
odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
}
/*This is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
struct dig_thres *dig_tab = &dm->dm_dig_table;
u8 IGI = dig_tab->cur_ig_value;
s8 diff = 0;
if (is_pasue_edcca) {
adaptivity->is_stop_edcca = true;
if (dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
if (adaptivity->adajust_igi_level > IGI)
diff = adaptivity->adajust_igi_level - IGI;
adaptivity->backup_l2h =
dm->th_l2h_ini - diff + adaptivity->igi_target;
adaptivity->backup_h2l =
adaptivity->backup_l2h - dm->th_edcca_hl_diff;
} else {
diff = adaptivity->igi_target - (s8)IGI;
adaptivity->backup_l2h = dm->th_l2h_ini + diff;
if (adaptivity->backup_l2h > 10)
adaptivity->backup_l2h = 10;
adaptivity->backup_h2l =
adaptivity->backup_l2h - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (adaptivity->backup_h2l < adaptivity->h2l_lb)
adaptivity->backup_h2l = adaptivity->h2l_lb;
if (adaptivity->backup_l2h < adaptivity->l2h_lb)
adaptivity->backup_l2h = adaptivity->l2h_lb;
}
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
/*Disable EDCCA*/
phydm_pause_edcca_work_item_callback(dm);
} else {
adaptivity->is_stop_edcca = false;
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
/*Resume EDCCA*/
phydm_resume_edcca_work_item_callback(dm);
}
}
void phydm_pause_edcca_work_item_callback(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
(u16)(0x7f | 0x7f << 8));
}
void phydm_resume_edcca_work_item_callback(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
if (dm->support_ic_type & ODM_IC_11N_SERIES)
odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
MASKBYTE2 | MASKBYTE0,
(u32)((u8)adaptivity->backup_l2h |
(u8)adaptivity->backup_h2l << 16));
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
(u16)((u8)adaptivity->backup_l2h |
(u8)adaptivity->backup_h2l << 8));
}
void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct adaptivity_statistics *adaptivity =
(struct adaptivity_statistics *)phydm_get_structure(
dm, PHYDM_ADAPTIVITY);
s8 th_l2h_dmc, th_h2l_dmc;
s8 diff = 0, igi_target = 0x32;
if (dm->support_ability & ODM_BB_ADAPTIVITY) {
if (dm->support_ic_type &
(ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
if (adaptivity->adajust_igi_level > IGI)
diff = adaptivity->adajust_igi_level - IGI;
th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
} else {
diff = igi_target - (s8)IGI;
th_l2h_dmc = dm->th_l2h_ini + diff;
if (th_l2h_dmc > 10)
th_l2h_dmc = 10;
th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l_dmc < adaptivity->h2l_lb)
th_h2l_dmc = adaptivity->h2l_lb;
if (th_l2h_dmc < adaptivity->l2h_lb)
th_l2h_dmc = adaptivity->l2h_lb;
}
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
IGI, th_l2h_dmc, th_h2l_dmc);
ODM_RT_TRACE(
dm, PHYDM_COMP_ADAPTIVITY,
"API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
dm->adaptivity_igi_upper, adaptivity->h2l_lb,
adaptivity->l2h_lb);
phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
}
}

108
drivers/staging/rtlwifi/phydm/phydm_adaptivity.h
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@ -1,108 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
/*20160902 changed by Kevin, refine method for searching pwdb lower bound*/
#define ADAPTIVITY_VERSION "9.3.5"
#define pwdb_upper_bound 7
#define dfir_loss 5
enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
};
enum phydm_set_lna {
phydm_disable_lna = 0,
phydm_enable_lna = 1,
};
enum phydm_trx_mux_type {
phydm_shutdown = 0,
phydm_standby_mode = 1,
phydm_tx_mode = 2,
phydm_rx_mode = 3
};
enum phydm_mac_edcca_type {
phydm_ignore_edcca = 0,
phydm_dont_ignore_edcca = 1
};
struct adaptivity_statistics {
s8 th_l2h_ini_backup;
s8 th_edcca_hl_diff_backup;
s8 igi_base;
u8 igi_target;
u8 nhm_wait;
s8 h2l_lb;
s8 l2h_lb;
bool is_first_link;
bool is_check;
bool dynamic_link_adaptivity;
u8 ap_num_th;
u8 adajust_igi_level;
bool acs_for_adaptivity;
s8 backup_l2h;
s8 backup_h2l;
bool is_stop_edcca;
};
void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca);
void phydm_check_adaptivity(void *dm_void);
void phydm_check_environment(void *dm_void);
void phydm_nhm_counter_statistics_init(void *dm_void);
void phydm_nhm_counter_statistics(void *dm_void);
void phydm_nhm_counter_statistics_reset(void *dm_void);
void phydm_get_nhm_counter_statistics(void *dm_void);
void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state);
void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H);
void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
enum phydm_trx_mux_type rx_mode);
bool phydm_cal_nhm_cnt(void *dm_void);
void phydm_search_pwdb_lower_bound(void *dm_void);
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);
void phydm_adaptivity_init(void *dm_void);
void phydm_adaptivity(void *dm_void);
void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
void phydm_pause_edcca_work_item_callback(void *dm_void);
void phydm_resume_edcca_work_item_callback(void *dm_void);
#endif

616
drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c
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@ -1,616 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
static bool phydm_la_buffer_allocate(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
bool ret = false;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA mode BufferAllocate]\n");
if (adc_smp_buf->length == 0) {
odm_allocate_memory(dm, (void **)&adc_smp_buf->octet,
adc_smp_buf->buffer_size);
if (!adc_smp_buf->octet) {
ret = false;
} else {
adc_smp_buf->length = adc_smp_buf->buffer_size;
ret = true;
}
}
return ret;
}
static void phydm_la_get_tx_pkt_buf(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 i = 0, value32, data_l = 0, data_h = 0;
u32 addr, finish_addr;
u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) -
1; /*end_addr = 0x3ffff;*/
bool is_round_up;
static u32 page = 0xFF;
u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
odm_write_1byte(dm, 0x0106, 0x69);
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "GetTxPktBuf\n");
value32 = odm_read_4byte(dm, 0x7c0);
is_round_up = (bool)((value32 & BIT(31)) >> 31);
/*Reg7C0[30:16]: finish addr (unit: 8byte)*/
finish_addr = (value32 & 0x7FFF0000) >> 16;
if (is_round_up) {
addr = (finish_addr + 1) << 3;
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n",
is_round_up, finish_addr, value32);
/*Byte to 64Byte*/
smp_number = (adc_smp_buf->buffer_size) >> 3;
} else {
addr = adc_smp_buf->start_pos;
addr_8byte = addr >> 3;
if (addr_8byte > finish_addr)
smp_number = addr_8byte - finish_addr;
else
smp_number = finish_addr - addr_8byte;
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
is_round_up, finish_addr, addr_8byte, smp_number);
}
if (dm->support_ic_type & ODM_RTL8197F) {
/*64K byte*/
for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) {
if ((addr & 0xfff) == 0)
odm_set_bb_reg(dm, 0x0140, MASKLWORD,
0x780 + (addr >> 12));
data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
MASKDWORD);
data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
MASKDWORD);
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
data_l);
}
} else {
while (addr != (finish_addr << 3)) {
if (page != (addr >> 12)) {
/*Reg140=0x780+(addr>>12),
*addr=0x30~0x3F, total 16 pages
*/
page = addr >> 12;
}
odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
/*pDataL = 0x8000+(addr&0xfff);*/
data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
MASKDWORD);
data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
MASKDWORD);
adc_smp_buf->octet[i] = data_h;
adc_smp_buf->octet[i + 1] = data_l;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
data_l);
i = i + 2;
if ((addr + 8) >= end_addr)
addr = adc_smp_buf->start_pos;
else
addr = addr + 8;
smp_cnt++;
if (smp_cnt >= (smp_number - 1))
break;
}
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "smp_cnt = ((%d))\n",
smp_cnt);
}
}
static void phydm_la_mode_set_mac_iq_dump(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u32 reg_value;
odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
adc_smp->is_bb_trigger = 0;
odm_set_mac_reg(dm, 0x7c0, BIT(2),
1); /*polling bit for MAC mode*/
odm_set_mac_reg(
dm, 0x7c0, BIT(4) | BIT(3),
adc_smp->la_trigger_edge); /*trigger mode for MAC*/
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel,
adc_smp->la_dbg_port);
/*[Set MAC Debug Port]*/
odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
} else {
adc_smp->is_bb_trigger = 1;
odm_set_mac_reg(dm, 0x7c0, BIT(1),
1); /*polling bit for BB ADC mode*/
if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
odm_set_mac_reg(
dm, 0x7c0, BIT(3),
1); /*polling bit for MAC trigger event*/
odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6),
adc_smp->la_trig_sig_sel);
if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
odm_set_mac_reg(
dm, 0x7c0, BIT(5),
1); /* manual trigger 0x7C0[5] = 0->1*/
}
}
reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
}
static void phydm_la_mode_set_dma_type(void *dm_void, u8 la_dma_type)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"2. [LA mode DMA setting] Dma_type = ((%d))\n",
la_dma_type);
if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
else
odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00,
la_dma_type); /*0x95C[11:8]*/
}
static void phydm_adc_smp_start(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 tmp_u1b;
u8 while_cnt = 0;
u8 polling_ok = false, target_polling_bit;
phydm_la_mode_bb_setting(dm);
phydm_la_mode_set_dma_type(dm, adc_smp->la_dma_type);
phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
if (dm->support_ic_type & ODM_RTL8197F) {
odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
} else { /*for 8814A and 8822B?*/
odm_write_1byte(dm, 0x198c, 0x7);
odm_write_1byte(dm, 0x8b4, 0x80);
/* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
}
phydm_la_mode_set_mac_iq_dump(dm);
/* return; */
target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
do { /*Poll time always use 100ms, when it exceed 2s, break while loop*/
tmp_u1b = odm_read_1byte(dm, 0x7c0);
if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
break;
} else if (tmp_u1b & target_polling_bit) {
ODM_delay_ms(100);
while_cnt = while_cnt + 1;
continue;
} else {
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"[LA Query OK] polling_bit=((0x%x))\n",
target_polling_bit);
polling_ok = true;
if (dm->support_ic_type & ODM_RTL8197F)
odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
break;
}
} while (while_cnt < 20);
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
if (polling_ok)
phydm_la_get_tx_pkt_buf(dm);
else
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"[Polling timeout]\n");
}
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"[LA mode] LA_pattern_count = ((%d))\n",
adc_smp->la_count);
adc_smp_stop(dm);
if (adc_smp->la_count == 0) {
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"LA Dump finished ---------->\n\n\n");
/**/
} else {
adc_smp->la_count--;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"LA Dump more ---------->\n\n\n");
adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel,
adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
}
}
void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
bool is_set_success = true;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
adc_smp->la_trig_mode = trig_mode;
adc_smp->la_trig_sig_sel = trig_sig_sel;
adc_smp->la_dma_type = dma_data_sig_sel;
adc_smp->la_trigger_time = trigger_time;
if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
is_set_success = false;
else if (adc_smp->adc_smp_buf.length == 0)
is_set_success = phydm_la_buffer_allocate(dm);
if (is_set_success) {
adc_smp->adc_smp_state = ADCSMP_STATE_SET;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"[LA Set Success] LA_State=((%d))\n",
adc_smp->adc_smp_state);
phydm_adc_smp_start(dm);
} else {
ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
"[LA Set Fail] LA_State=((%d))\n",
adc_smp->adc_smp_state);
}
}
void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 used = *pused;
u32 i;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%s adc_smp_state %d", __func__,
adc_smp->adc_smp_state);
for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
adc_smp_buf->octet[i],
adc_smp_buf->octet[i + 1]);
}
PHYDM_SNPRINTF(output + used, out_len - used, "\n");
*pused = used;
}
s32 adc_smp_get_sample_counts(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
return (adc_smp_buf->length >> 2) - 2;
}
s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
u32 index)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
u32 used = 0;
if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
PHYDM_SNPRINTF(output + used, out_len - used,
"Error: la data is not ready yet ...\n");
return -1;
}
if (index < ((adc_smp_buf->length >> 2) - 2)) {
PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
adc_smp_buf->octet[index],
adc_smp_buf->octet[index + 1]);
}
return 0;
}
void adc_smp_stop(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA_Stop] LA_state = ((%d))\n",
adc_smp->adc_smp_state);
}
void adc_smp_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
if (dm->support_ic_type & ODM_RTL8814A) {
adc_smp_buf->start_pos = 0x30000;
adc_smp_buf->buffer_size = 0x10000;
} else if (dm->support_ic_type & ODM_RTL8822B) {
adc_smp_buf->start_pos = 0x20000;
adc_smp_buf->buffer_size = 0x20000;
} else if (dm->support_ic_type & ODM_RTL8197F) {
adc_smp_buf->start_pos = 0x00000;
adc_smp_buf->buffer_size = 0x10000;
} else if (dm->support_ic_type & ODM_RTL8821C) {
adc_smp_buf->start_pos = 0x8000;
adc_smp_buf->buffer_size = 0x8000;
}
}
void adc_smp_de_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
adc_smp_stop(dm);
if (adc_smp_buf->length != 0x0) {
odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
adc_smp_buf->length = 0x0;
}
}
void phydm_la_mode_bb_setting(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 trig_mode = adc_smp->la_trig_mode;
u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
u32 dbg_port = adc_smp->la_dbg_port;
u8 is_trigger_edge = adc_smp->la_trigger_edge;
u8 sampling_rate = adc_smp->la_smp_rate;
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
trig_mode, dbg_port, is_trigger_edge, sampling_rate,
trig_sig_sel);
if (trig_mode == PHYDM_MAC_TRIG)
trig_sig_sel = 0; /*ignore this setting*/
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
if (trig_mode == PHYDM_ADC_RF0_TRIG) {
/*DBGOUT_RFC_a[31:0]*/
odm_set_bb_reg(dm, 0x8f8,
BIT(25) | BIT(24) | BIT(23) | BIT(22),
9);
} else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
/*DBGOUT_RFC_b[31:0]*/
odm_set_bb_reg(dm, 0x8f8,
BIT(25) | BIT(24) | BIT(23) | BIT(22),
8);
} else {
odm_set_bb_reg(dm, 0x8f8,
BIT(25) | BIT(24) | BIT(23) | BIT(22),
0);
}
/*
* (0:) '{ofdm_dbg[31:0]}'
* (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
* (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
* (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
* (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
* (5:) '{dbg_iqk_anta}'
* (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
* (7:) '{dbg_iqk_antb}'
* (8:) '{DBGOUT_RFC_b[31:0]}'
* (9:) '{DBGOUT_RFC_a[31:0]}'
* (a:) '{dbg_ofdm}'
* (b:) '{dbg_cck}'
*/
/*disable dbg clk gating*/
odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7);
/*0x95C[4:0], BB debug port bit*/
odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel);
odm_set_bb_reg(dm, 0x8FC, MASKDWORD, dbg_port);
/*0: posedge, 1: negedge*/
odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge);
odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
/* (0:) '80MHz'
* (1:) '40MHz'
* (2:) '20MHz'
* (3:) '10MHz'
* (4:) '5MHz'
* (5:) '2.5MHz'
* (6:) '1.25MHz'
* (7:) '160MHz (for BW160 ic)'
*/
} else {
/*0x9A0[4:0], BB debug port bit*/
odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel);
odm_set_bb_reg(dm, 0x908, MASKDWORD, dbg_port);
/*0: posedge, 1: negedge*/
odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge);
odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
/* (0:) '80MHz'
* (1:) '40MHz'
* (2:) '20MHz'
* (3:) '10MHz'
* (4:) '5MHz'
* (5:) '2.5MHz'
* (6:) '1.25MHz'
* (7:) '160MHz (for BW160 ic)'
*/
}
}
void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u8 trigger_time_unit_num;
u32 time_unit = 0;
if (trigger_time_mu_sec < 128)
time_unit = 0; /*unit: 1mu sec*/
else if (trigger_time_mu_sec < 256)
time_unit = 1; /*unit: 2mu sec*/
else if (trigger_time_mu_sec < 512)
time_unit = 2; /*unit: 4mu sec*/
else if (trigger_time_mu_sec < 1024)
time_unit = 3; /*unit: 8mu sec*/
else if (trigger_time_mu_sec < 2048)
time_unit = 4; /*unit: 16mu sec*/
else if (trigger_time_mu_sec < 4096)
time_unit = 5; /*unit: 32mu sec*/
else if (trigger_time_mu_sec < 8192)
time_unit = 6; /*unit: 64mu sec*/
trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
trigger_time_unit_num, time_unit);
odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
}
void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len, u32 input_num)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rt_adcsmp *adc_smp = &dm->adcsmp;
u8 trig_mode, dma_data_sig_sel;
u32 trig_sig_sel;
bool is_enable_la_mode;
u32 trigger_time_mu_sec;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
is_enable_la_mode = (bool)var1[0];
/*dbg_print("echo cmd input_num = %d\n", input_num);*/
if ((strcmp(input[1], help) == 0)) {
PHYDM_SNPRINTF(output + used,
out_len - used,
"{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC}\n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime}\n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
} else if (is_enable_la_mode) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
trig_mode = (u8)var1[1];
if (trig_mode == PHYDM_MAC_TRIG)
PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
else
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
trig_sig_sel = var1[2];
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
dma_data_sig_sel = (u8)var1[3];
trigger_time_mu_sec = var1[4]; /* unit: us */
adc_smp->la_mac_ref_mask = var1[5];
adc_smp->la_dbg_port = var1[6];
adc_smp->la_trigger_edge = (u8)var1[7];
adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
adc_smp->la_count = var1[9];
ODM_RT_TRACE(
dm, ODM_COMP_UNCOND,
"echo lamode %d %d %d %d %d %d %x %d %d %d\n",
var1[0], var1[1], var1[2], var1[3], var1[4],
var1[5], var1[6], var1[7], var1[8], var1[9]);
PHYDM_SNPRINTF(
output + used, out_len - used,
"a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
trig_mode, trig_sig_sel, dma_data_sig_sel);
PHYDM_SNPRINTF(
output + used, out_len - used,
"e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
trigger_time_mu_sec, adc_smp->la_mac_ref_mask,
adc_smp->la_dbg_port);
PHYDM_SNPRINTF(
output + used, out_len - used,
"h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
adc_smp->la_trigger_edge,
(80 >> adc_smp->la_smp_rate),
adc_smp->la_count);
adc_smp_set(dm, trig_mode, trig_sig_sel,
dma_data_sig_sel, trigger_time_mu_sec, 0);
} else {
adc_smp_stop(dm);
PHYDM_SNPRINTF(output + used, out_len - used,
"Disable LA mode\n");
}
}
}

85
drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h
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@ -1,85 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_ADCSMP_H
#define __INC_ADCSMP_H
#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
};
enum rt_adcsmp_trig_sel {
PHYDM_ADC_BB_TRIG = 0,
PHYDM_ADC_MAC_TRIG = 1,
PHYDM_ADC_RF0_TRIG = 2,
PHYDM_ADC_RF1_TRIG = 3,
PHYDM_MAC_TRIG = 4
};
enum rt_adcsmp_trig_sig_sel {
ADCSMP_TRIG_CRCOK = 0,
ADCSMP_TRIG_CRCFAIL = 1,
ADCSMP_TRIG_CCA = 2,
ADCSMP_TRIG_REG = 3
};
enum rt_adcsmp_state {
ADCSMP_STATE_IDLE = 0,
ADCSMP_STATE_SET = 1,
ADCSMP_STATE_QUERY = 2
};
struct rt_adcsmp {
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
u32 la_mac_ref_mask;
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u8 is_bb_trigger;
u8 la_work_item_index;
};
void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time);
void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
s32 adc_smp_get_sample_counts(void *dm_void);
s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
u32 index);
void adc_smp_stop(void *dm_void);
void adc_smp_init(void *dm_void);
void adc_smp_de_init(void *dm_void);
void phydm_la_mode_bb_setting(void *dm_void);
void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len, u32 input_num);
#endif

72
drivers/staging/rtlwifi/phydm/phydm_antdiv.c
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@ -1,72 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* *************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/* ******************************************************
* when antenna test utility is on or some testing need to disable antenna
* diversity, call this function to disable all ODM related mechanisms which
* will switch antenna.
* *******************************************************/
void odm_stop_antenna_switch_dm(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
/* disable ODM antenna diversity */
dm->support_ability &= ~ODM_BB_ANT_DIV;
ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV, "STOP Antenna Diversity\n");
}
void phydm_enable_antenna_diversity(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
dm->support_ability |= ODM_BB_ANT_DIV;
ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV,
"AntDiv is enabled & Re-Init AntDiv\n");
odm_antenna_diversity_init(dm);
}
void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type == ODM_RTL8723B) {
if (ant_setting == 0) /* ant A*/
odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
else if (ant_setting == 1)
odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
} else if (dm->support_ic_type == ODM_RTL8723D) {
if (ant_setting == 0) /* ant A*/
odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
else if (ant_setting == 1)
odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
}
}
/* ****************************************************** */
void odm_sw_ant_div_rest_after_link(void *dm_void) {}
void odm_ant_div_reset(void *dm_void) {}
void odm_antenna_diversity_init(void *dm_void) {}
void odm_antenna_diversity(void *dm_void) {}

290
drivers/staging/rtlwifi/phydm/phydm_antdiv.h
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@ -1,290 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/* 2.0 2014.11.04
* 2.1 2015.01.13 Dino
* 2.2 2015.01.16 Dino
* 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
* 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
* 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
* by BT, because antenna diversity only works when BT is disable
* or radio off
* 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
* Diversity
* 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
* for 8723B, not from PHYDM
* 3.6 2015.11.16 Stanley
* 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
* 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
* 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
* add cmd for adjust truth table
*/
#define ANTDIV_VERSION "3.9"
/* 1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*ant A or ant Main or S1*/
#define AUX_ANT 2 /*AntB or ant Aux or S0*/
#define MAX_ANT 3 /* 3 for AP using*/
#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
* TX fixed at S1
*/
#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
* TX fixed at S1
*/
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
#define NUM_ANTENNA_8821A 2
#define SUPPORT_BEAM_SET_PATTERN_NUM 8
#define NO_FIX_TX_ANT 0
#define FIX_TX_AT_MAIN 1
#define FIX_AUX_AT_MAIN 2
/* Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_N_ANTDIV_SUPPORT \
(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
ODM_RTL8723D | ODM_RTL8195A)
#define ODM_AC_ANTDIV_SUPPORT \
(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
ODM_RTL8822B | ODM_RTL8814B)
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
#define ODM_ANTDIV_2G_SUPPORT_IC \
(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
ODM_RTL8188F | ODM_RTL8723D)
#define ODM_ANTDIV_5G_SUPPORT_IC \
(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_ANTDIV_2G BIT(0)
#define ODM_ANTDIV_5G BIT(1)
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define TX_BY_REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define evm_rssi_th_high 25
#define evm_rssi_th_low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define bdc_bfer_train_state 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
/*SW S0S1 antenna diversity*/
#define SWAW_STEP_INIT 0xff
#define SWAW_STEP_PEEK 0
#define SWAW_STEP_DETERMINE 1
#define RSSI_CHECK_RESET_PERIOD 10
#define RSSI_CHECK_THRESHOLD 50
/*Hong Lin Smart antenna*/
#define HL_SMTANT_2WIRE_DATA_LEN 24
/* 1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct sw_antenna_switch {
u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
*than check this antenna again
*/
u8 try_flag;
s32 pre_rssi;
u8 cur_antenna;
u8 pre_antenna;
u8 rssi_trying;
u8 reset_idx;
u8 train_time;
u8 train_time_flag; /*base on RSSI difference between two antennas*/
struct timer_list phydm_sw_antenna_switch_timer;
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
bool is_sw_ant_div_by_ctrl_frame;
/* AntDect (Before link Antenna Switch check) need to be moved*/
u16 single_ant_counter;
u16 dual_ant_counter;
u16 aux_fail_detec_counter;
u16 retry_counter;
u8 swas_no_link_state;
u32 swas_no_link_bk_reg948;
bool ANTA_ON; /*To indicate ant A is or not*/
bool ANTB_ON; /*To indicate ant B is on or not*/
bool pre_aux_fail_detec;
bool rssi_ant_dect_result;
u8 ant_5g;
u8 ant_2g;
};
struct fast_antenna_training {
u8 bssid[6];
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u8 antsel_rx_keep_3;
u32 ant_sum_rssi[7];
u32 ant_rssi_cnt[7];
u32 ant_ave_rssi[7];
u8 fat_state;
u32 train_idx;
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
u8 ant_div_on_off;
bool is_become_linked;
u32 min_max_rssi;
u8 idx_ant_div_counter_2g;
u8 idx_ant_div_counter_5g;
u8 ant_div_2g_5g;
u32 cck_ctrl_frame_cnt_main;
u32 cck_ctrl_frame_cnt_aux;
u32 ofdm_ctrl_frame_cnt_main;
u32 ofdm_ctrl_frame_cnt_aux;
u32 main_ant_ctrl_frame_sum;
u32 aux_ant_ctrl_frame_sum;
u32 main_ant_ctrl_frame_cnt;
u32 aux_ant_ctrl_frame_cnt;
u8 b_fix_tx_ant;
bool fix_ant_bfee;
bool enable_ctrl_frame_antdiv;
bool use_ctrl_frame_antdiv;
u8 hw_antsw_occur;
u8 *p_force_tx_ant_by_desc;
u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
*outer parameter later
*/
u8 *p_default_s0_s1;
u8 default_s0_s1;
};
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/*Fast antenna training*/
enum fat_state {
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
FAT_TRAINING_STATE = 2,
FAT_DECISION_STATE = 3
};
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
/*8723B intrnal switch S0 S1*/
S0S1_SW_ANTDIV = 0x06,
/*TRX S0S1 diversity for 8723D*/
S0S1_TRX_HW_ANTDIV = 0x07,
/*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
*each ant. is equipped with 4 antenna patterns
*/
HL_SW_SMART_ANT_TYPE1 = 0x10,
/*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
HL_SW_SMART_ANT_TYPE2 = 0x11,
};
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void odm_stop_antenna_switch_dm(void *dm_void);
void phydm_enable_antenna_diversity(void *dm_void);
void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
);
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
void odm_sw_ant_div_rest_after_link(void *dm_void);
void odm_ant_div_reset(void *dm_void);
void odm_antenna_diversity_init(void *dm_void);
void odm_antenna_diversity(void *dm_void);
#endif /*#ifndef __ODMANTDIV_H__*/

37
drivers/staging/rtlwifi/phydm/phydm_beamforming.h
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@ -1,37 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_PHYDM_BEAMFORMING_H
#define __INC_PHYDM_BEAMFORMING_H
/*Beamforming Related*/
#include "txbf/halcomtxbf.h"
#include "txbf/haltxbfjaguar.h"
#include "txbf/haltxbf8822b.h"
#include "txbf/haltxbfinterface.h"
#define beamforming_gid_paid(adapter, tcb)
#define phydm_acting_determine(dm, type) false
#define beamforming_enter(dm, sta_idx)
#define beamforming_leave(dm, RA)
#define beamforming_end_fw(dm)
#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
#define beamforming_control_v2(dm, idx, mode, BW, period) true
#define phydm_beamforming_end_sw(dm, _status)
#define beamforming_timer_callback(dm)
#define phydm_beamforming_init(dm)
#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
#define beamforming_watchdog(dm)
#define phydm_beamforming_watchdog(dm)
#endif

447
drivers/staging/rtlwifi/phydm/phydm_ccx.c
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@ -1,447 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/*Set NHM period, threshold, disable ignore cca or not,
*disable ignore txon or not
*/
void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct ccx_info *ccx_info = &dm->dm_ccx_info;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
if (nhm_setting == SET_NHM_SETTING) {
/*Set inexclude_cca, inexclude_txon*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
ccx_info->nhm_inexclude_cca);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
ccx_info->nhm_inexclude_txon);
/*Set NHM period*/
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
ccx_info->NHM_period);
/*Set NHM threshold*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE0, ccx_info->NHM_th[0]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE1, ccx_info->NHM_th[1]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE2, ccx_info->NHM_th[2]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE3, ccx_info->NHM_th[3]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE0, ccx_info->NHM_th[4]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE1, ccx_info->NHM_th[5]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE2, ccx_info->NHM_th[6]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE3, ccx_info->NHM_th[7]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
ccx_info->NHM_th[8]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
ccx_info->NHM_th[9]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
ccx_info->NHM_th[10]);
/*CCX EN*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
CCX_EN);
} else if (nhm_setting == STORE_NHM_SETTING) {
/*Store prev. disable_ignore_cca, disable_ignore_txon*/
ccx_info->NHM_inexclude_cca_restore =
(enum nhm_inexclude_cca)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
ccx_info->NHM_inexclude_txon_restore =
(enum nhm_inexclude_txon)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
/*Store pervious NHM period*/
ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
/*Store NHM threshold*/
ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
} else if (nhm_setting == RESTORE_NHM_SETTING) {
/*Set disable_ignore_cca, disable_ignore_txon*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
ccx_info->NHM_inexclude_cca_restore);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
ccx_info->NHM_inexclude_txon_restore);
/*Set NHM period*/
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
ccx_info->NHM_period);
/*Set NHM threshold*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE0, ccx_info->NHM_th_restore[0]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE1, ccx_info->NHM_th_restore[1]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE2, ccx_info->NHM_th_restore[2]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
MASKBYTE3, ccx_info->NHM_th_restore[3]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE0, ccx_info->NHM_th_restore[4]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE1, ccx_info->NHM_th_restore[5]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE2, ccx_info->NHM_th_restore[6]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
MASKBYTE3, ccx_info->NHM_th_restore[7]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
ccx_info->NHM_th_restore[8]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
ccx_info->NHM_th_restore[9]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
ccx_info->NHM_th_restore[10]);
} else {
return;
}
}
else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (nhm_setting == SET_NHM_SETTING) {
/*Set disable_ignore_cca, disable_ignore_txon*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
ccx_info->nhm_inexclude_cca);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
ccx_info->nhm_inexclude_txon);
/*Set NHM period*/
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
ccx_info->NHM_period);
/*Set NHM threshold*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE0, ccx_info->NHM_th[0]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE1, ccx_info->NHM_th[1]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE2, ccx_info->NHM_th[2]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE3, ccx_info->NHM_th[3]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE0, ccx_info->NHM_th[4]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE1, ccx_info->NHM_th[5]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE2, ccx_info->NHM_th[6]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE3, ccx_info->NHM_th[7]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
ccx_info->NHM_th[8]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
ccx_info->NHM_th[9]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
ccx_info->NHM_th[10]);
/*CCX EN*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
CCX_EN);
} else if (nhm_setting == STORE_NHM_SETTING) {
/*Store prev. disable_ignore_cca, disable_ignore_txon*/
ccx_info->NHM_inexclude_cca_restore =
(enum nhm_inexclude_cca)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
ccx_info->NHM_inexclude_txon_restore =
(enum nhm_inexclude_txon)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
/*Store pervious NHM period*/
ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
/*Store NHM threshold*/
ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
} else if (nhm_setting == RESTORE_NHM_SETTING) {
/*Set disable_ignore_cca, disable_ignore_txon*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
ccx_info->NHM_inexclude_cca_restore);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
ccx_info->NHM_inexclude_txon_restore);
/*Set NHM period*/
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
ccx_info->NHM_period_restore);
/*Set NHM threshold*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE0, ccx_info->NHM_th_restore[0]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE1, ccx_info->NHM_th_restore[1]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE2, ccx_info->NHM_th_restore[2]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
MASKBYTE3, ccx_info->NHM_th_restore[3]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE0, ccx_info->NHM_th_restore[4]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE1, ccx_info->NHM_th_restore[5]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE2, ccx_info->NHM_th_restore[6]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
MASKBYTE3, ccx_info->NHM_th_restore[7]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
ccx_info->NHM_th_restore[8]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
ccx_info->NHM_th_restore[9]);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
ccx_info->NHM_th_restore[10]);
} else {
return;
}
}
}
void phydm_nhm_trigger(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*Trigger NHM*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
/*Trigger NHM*/
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
}
}
void phydm_get_nhm_result(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u32 value32;
struct ccx_info *ccx_info = &dm->dm_ccx_info;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
/*Get NHM duration*/
value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
}
else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
/* Get NHM duration */
value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
}
}
bool phydm_check_nhm_ready(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u32 value32 = 0;
u8 i;
bool ret = false;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
value32 = odm_get_bb_reg(dm,
ODM_REG_CLM_RESULT_11AC,
MASKDWORD);
for (i = 0; i < 200; i++) {
ODM_delay_ms(1);
if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
BIT(17))) {
ret = true;
break;
}
}
}
else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
for (i = 0; i < 200; i++) {
ODM_delay_ms(1);
if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
BIT(17))) {
ret = true;
break;
}
}
}
return ret;
}
void phydm_clm_setting(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct ccx_info *ccx_info = &dm->dm_ccx_info;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
ccx_info->CLM_period); /*4us sample 1 time*/
odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
0x1); /*Enable CCX for CLM*/
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
ccx_info->CLM_period); /*4us sample 1 time*/
odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
0x1); /*Enable CCX for CLM*/
}
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
ccx_info->CLM_period * 4);
}
void phydm_clm_trigger(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
0x0); /*Trigger CLM*/
odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
0x0); /*Trigger CLM*/
odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
}
}
bool phydm_check_cl_mready(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u32 value32 = 0;
bool ret = false;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
value32 = odm_get_bb_reg(
dm, ODM_REG_CLM_RESULT_11AC,
MASKDWORD); /*make sure CLM calc is ready*/
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
value32 = odm_get_bb_reg(
dm, ODM_REG_CLM_READY_11N,
MASKDWORD); /*make sure CLM calc is ready*/
if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
ret = true;
else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
(value32 & BIT(16)))
ret = true;
else
ret = false;
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
ret);
return ret;
}
void phydm_get_cl_mresult(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct ccx_info *ccx_info = &dm->dm_ccx_info;
u32 value32 = 0;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
MASKDWORD); /*read CLM calc result*/
else if (dm->support_ic_type & ODM_IC_11N_SERIES)
value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
MASKDWORD); /*read CLM calc result*/
ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
ccx_info->CLM_result * 4);
}

72
drivers/staging/rtlwifi/phydm/phydm_ccx.h
View File

@ -1,72 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
#define CCX_EN 1
#define SET_NHM_SETTING 0
#define STORE_NHM_SETTING 1
#define RESTORE_NHM_SETTING 2
enum nhm_inexclude_cca { NHM_EXCLUDE_CCA, NHM_INCLUDE_CCA };
enum nhm_inexclude_txon { NHM_EXCLUDE_TXON, NHM_INCLUDE_TXON };
struct ccx_info {
/*Settings*/
u8 NHM_th[11];
u16 NHM_period; /* 4us per unit */
u16 CLM_period; /* 4us per unit */
enum nhm_inexclude_txon nhm_inexclude_txon;
enum nhm_inexclude_cca nhm_inexclude_cca;
/*Previous Settings*/
u8 NHM_th_restore[11];
u16 NHM_period_restore; /* 4us per unit */
u16 CLM_period_restore; /* 4us per unit */
enum nhm_inexclude_txon NHM_inexclude_txon_restore;
enum nhm_inexclude_cca NHM_inexclude_cca_restore;
/*Report*/
u8 NHM_result[12];
u16 NHM_duration;
u16 CLM_result;
bool echo_NHM_en;
bool echo_CLM_en;
u8 echo_IGI;
};
/*NHM*/
void phydm_nhm_setting(void *dm_void, u8 nhm_setting);
void phydm_nhm_trigger(void *dm_void);
void phydm_get_nhm_result(void *dm_void);
bool phydm_check_nhm_ready(void *dm_void);
/*CLM*/
void phydm_clm_setting(void *dm_void);
void phydm_clm_trigger(void *dm_void);
bool phydm_check_cl_mready(void *dm_void);
void phydm_get_cl_mresult(void *dm_void);
#endif

332
drivers/staging/rtlwifi/phydm/phydm_cfotracking.c
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@ -1,332 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
static void odm_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
if (cfo_track->crystal_cap == crystal_cap)
return;
cfo_track->crystal_cap = crystal_cap;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
crystal_cap = crystal_cap & 0x3F;
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x007ff800,
(crystal_cap | (crystal_cap << 6)));
} else if (dm->support_ic_type & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
crystal_cap = crystal_cap & 0x3F;
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x7FF80000,
(crystal_cap | (crystal_cap << 6)));
} else if ((dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B |
ODM_RTL8192E | ODM_RTL8821))) {
/* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
crystal_cap = crystal_cap & 0x3F;
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x00FFF000,
(crystal_cap | (crystal_cap << 6)));
} else if (dm->support_ic_type & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
crystal_cap = crystal_cap & 0x3F;
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0x07FF8000,
(crystal_cap | (crystal_cap << 6)));
} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
crystal_cap = crystal_cap & 0x3F;
odm_set_bb_reg(dm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
odm_set_bb_reg(dm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
} else {
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): Use default setting.\n", __func__);
odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000,
(crystal_cap | (crystal_cap << 6)));
}
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s(): crystal_cap = 0x%x\n",
__func__, crystal_cap);
/* JJ modified 20161115 */
}
static u8 odm_get_default_crytaltal_cap(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
u8 crystal_cap = 0x20;
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
crystal_cap = rtlefuse->crystalcap;
crystal_cap = crystal_cap & 0x3f;
return crystal_cap;
}
static void odm_set_atc_status(void *dm_void, bool atc_status)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
if (cfo_track->is_atc_status == atc_status)
return;
odm_set_bb_reg(dm, ODM_REG(BB_ATC, dm), ODM_BIT(BB_ATC, dm),
atc_status);
cfo_track->is_atc_status = atc_status;
}
static bool odm_get_atc_status(void *dm_void)
{
bool atc_status;
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
atc_status = (bool)odm_get_bb_reg(dm, ODM_REG(BB_ATC, dm),
ODM_BIT(BB_ATC, dm));
return atc_status;
}
void odm_cfo_tracking_reset(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
cfo_track->def_x_cap = odm_get_default_crytaltal_cap(dm);
cfo_track->is_adjust = true;
if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
odm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): approch default value (0x%x)\n", __func__,
cfo_track->crystal_cap);
} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
odm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): approch default value (0x%x)\n", __func__,
cfo_track->crystal_cap);
}
odm_set_atc_status(dm, true);
}
void odm_cfo_tracking_init(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
cfo_track->crystal_cap = odm_get_default_crytaltal_cap(dm);
cfo_track->def_x_cap = cfo_track->crystal_cap;
cfo_track->is_atc_status = odm_get_atc_status(dm);
cfo_track->is_adjust = true;
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): is_atc_status = %d, crystal_cap = 0x%x\n", __func__,
cfo_track->is_atc_status, cfo_track->def_x_cap);
/* Crystal cap. control by WiFi */
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, 0x10, 0x40, 0x1);
}
void odm_cfo_tracking(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
s32 cfo_ave = 0;
u32 cfo_rpt_sum, cfo_khz_avg[4] = {0};
s32 cfo_ave_diff;
s8 crystal_cap = cfo_track->crystal_cap;
u8 adjust_xtal = 1, i, valid_path_cnt = 0;
/* 4 Support ability */
if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) {
ODM_RT_TRACE(
dm, ODM_COMP_CFO_TRACKING,
"%s(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n",
__func__);
return;
}
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING, "%s()=========>\n", __func__);
if (!dm->is_linked || !dm->is_one_entry_only) {
/* 4 No link or more than one entry */
odm_cfo_tracking_reset(dm);
ODM_RT_TRACE(
dm, ODM_COMP_CFO_TRACKING,
"%s(): Reset: is_linked = %d, is_one_entry_only = %d\n",
__func__, dm->is_linked, dm->is_one_entry_only);
} else {
/* 3 1. CFO Tracking */
/* 4 1.1 No new packet */
if (cfo_track->packet_count == cfo_track->packet_count_pre) {
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): packet counter doesn't change\n",
__func__);
return;
}
cfo_track->packet_count_pre = cfo_track->packet_count;
/* 4 1.2 Calculate CFO */
for (i = 0; i < dm->num_rf_path; i++) {
if (cfo_track->CFO_cnt[i] == 0)
continue;
valid_path_cnt++;
cfo_rpt_sum =
(u32)((cfo_track->CFO_tail[i] < 0) ?
(0 - cfo_track->CFO_tail[i]) :
cfo_track->CFO_tail[i]);
cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(cfo_rpt_sum) /
cfo_track->CFO_cnt[i];
ODM_RT_TRACE(
dm, ODM_COMP_CFO_TRACKING,
"[path %d] cfo_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
cfo_khz_avg[i]);
}
for (i = 0; i < valid_path_cnt; i++) {
if (cfo_track->CFO_tail[i] < 0) {
/* */
cfo_ave += (0 - (s32)cfo_khz_avg[i]);
} else {
cfo_ave += (s32)cfo_khz_avg[i];
}
}
if (valid_path_cnt >= 2)
cfo_ave = cfo_ave / valid_path_cnt;
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"valid_path_cnt = ((%d)), cfo_ave = ((%d kHz))\n",
valid_path_cnt, cfo_ave);
/*reset counter*/
for (i = 0; i < dm->num_rf_path; i++) {
cfo_track->CFO_tail[i] = 0;
cfo_track->CFO_cnt[i] = 0;
}
/* 4 1.3 Avoid abnormal large CFO */
cfo_ave_diff = (cfo_track->CFO_ave_pre >= cfo_ave) ?
(cfo_track->CFO_ave_pre - cfo_ave) :
(cfo_ave - cfo_track->CFO_ave_pre);
if (cfo_ave_diff > 20 && cfo_track->large_cfo_hit == 0 &&
!cfo_track->is_adjust) {
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): first large CFO hit\n", __func__);
cfo_track->large_cfo_hit = 1;
return;
}
cfo_track->large_cfo_hit = 0;
cfo_track->CFO_ave_pre = cfo_ave;
/* 4 1.4 Dynamic Xtal threshold */
if (!cfo_track->is_adjust) {
if (cfo_ave > CFO_TH_XTAL_HIGH ||
cfo_ave < (-CFO_TH_XTAL_HIGH))
cfo_track->is_adjust = true;
} else {
if (cfo_ave < CFO_TH_XTAL_LOW &&
cfo_ave > (-CFO_TH_XTAL_LOW))
cfo_track->is_adjust = false;
}
/* 4 1.5 BT case: Disable CFO tracking */
if (dm->is_bt_enabled) {
cfo_track->is_adjust = false;
odm_set_crystal_cap(dm, cfo_track->def_x_cap);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): Disable CFO tracking for BT!!\n",
__func__);
}
/* 4 1.7 Adjust Crystal Cap. */
if (cfo_track->is_adjust) {
if (cfo_ave > CFO_TH_XTAL_LOW)
crystal_cap = crystal_cap + adjust_xtal;
else if (cfo_ave < (-CFO_TH_XTAL_LOW))
crystal_cap = crystal_cap - adjust_xtal;
if (crystal_cap > 0x3f)
crystal_cap = 0x3f;
else if (crystal_cap < 0)
crystal_cap = 0;
odm_set_crystal_cap(dm, (u8)crystal_cap);
}
ODM_RT_TRACE(
dm, ODM_COMP_CFO_TRACKING,
"%s(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
__func__, cfo_track->crystal_cap, cfo_track->def_x_cap);
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
/* 3 2. Dynamic ATC switch */
if (cfo_ave < CFO_TH_ATC && cfo_ave > -CFO_TH_ATC) {
odm_set_atc_status(dm, false);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): Disable ATC!!\n", __func__);
} else {
odm_set_atc_status(dm, true);
ODM_RT_TRACE(dm, ODM_COMP_CFO_TRACKING,
"%s(): Enable ATC!!\n", __func__);
}
}
}
void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, u8 num_ss)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct dm_per_pkt_info *pktinfo =
(struct dm_per_pkt_info *)pktinfo_void;
struct cfo_tracking *cfo_track =
(struct cfo_tracking *)phydm_get_structure(dm, PHYDM_CFOTRACK);
u8 i;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
if (pktinfo->is_packet_match_bssid) {
if (num_ss > dm->num_rf_path) /*For fool proof*/
num_ss = dm->num_rf_path;
/* 3 Update CFO report for path-A & path-B */
/* Only paht-A and path-B have CFO tail and short CFO */
for (i = 0; i < num_ss; i++) {
cfo_track->CFO_tail[i] += pcfotail[i];
cfo_track->CFO_cnt[i]++;
}
/* 3 Update packet counter */
if (cfo_track->packet_count == 0xffffffff)
cfo_track->packet_count = 0;
else
cfo_track->packet_count++;
}
}

49
drivers/staging/rtlwifi/phydm/phydm_cfotracking.h
View File

@ -1,49 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/******************************************************************************
*
* Copyright(c) 2007 - 2016 Realtek Corporation.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
#define CFO_TH_XTAL_HIGH 20 /* kHz */
#define CFO_TH_XTAL_LOW 10 /* kHz */
#define CFO_TH_ATC 80 /* kHz */
struct cfo_tracking {
bool is_atc_status;
bool large_cfo_hit;
bool is_adjust;
u8 crystal_cap;
u8 def_x_cap;
s32 CFO_tail[4];
u32 CFO_cnt[4];
s32 CFO_ave_pre;
u32 packet_count;
u32 packet_count_pre;
bool is_force_xtal_cap;
bool is_reset;
};
void odm_cfo_tracking_reset(void *dm_void);
void odm_cfo_tracking_init(void *dm_void);
void odm_cfo_tracking(void *dm_void);
void odm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
u8 num_ss);
#endif

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