mirror of https://gitee.com/openkylin/linux.git
ASoC: UDA1380: change decimator/interpolator register handling
If the UDA1380's interpolator or decimator are set to be clocked from the WSPLL (which syncs to the WSI signal), the DAI link must be running to change the interpolator/decimator registers (which include volume controls and digital mute setting). * Queue work in the alsa PCM_START .trigger to flush registers as soon as the link is running. This replaces the .prepare and .digital_mute callbacks. * Use the SILENCE override instead of MTM for muting and remove its alsa control to avoid confusion. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Philipp Zabel
Mark Brown
parent
a3c7729e6c
commit
ef9e5e5c31
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@ -25,6 +25,7 @@
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#include <linux/ioctl.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/workqueue.h>
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#include <sound/core.h>
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#include <sound/control.h>
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#include <sound/initval.h>
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@ -35,6 +36,9 @@
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#include "uda1380.h"
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static struct work_struct uda1380_work;
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static struct snd_soc_codec *uda1380_codec;
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/*
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* uda1380 register cache
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*/
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@ -50,6 +54,8 @@ static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
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0x0000, 0x8000, 0x0002, 0x0000,
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};
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static unsigned long uda1380_cache_dirty;
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/*
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* read uda1380 register cache
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*/
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@ -71,8 +77,11 @@ static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
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u16 reg, unsigned int value)
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{
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u16 *cache = codec->reg_cache;
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if (reg >= UDA1380_CACHEREGNUM)
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return;
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if ((reg >= 0x10) && (cache[reg] != value))
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set_bit(reg - 0x10, &uda1380_cache_dirty);
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cache[reg] = value;
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}
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@ -111,6 +120,8 @@ static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
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(data[0]<<8) | data[1]);
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return -EIO;
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}
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if (reg >= 0x10)
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clear_bit(reg - 0x10, &uda1380_cache_dirty);
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return 0;
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} else
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return -EIO;
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@ -118,6 +129,20 @@ static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
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#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
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static void uda1380_flush_work(struct work_struct *work)
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{
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int bit, reg;
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for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
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reg = 0x10 + bit;
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pr_debug("uda1380: flush reg %x val %x:\n", reg,
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uda1380_read_reg_cache(uda1380_codec, reg));
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uda1380_write(uda1380_codec, reg,
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uda1380_read_reg_cache(uda1380_codec, reg));
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clear_bit(bit, &uda1380_cache_dirty);
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}
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}
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/* declarations of ALSA reg_elem_REAL controls */
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static const char *uda1380_deemp[] = {
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"None",
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@ -252,7 +277,6 @@ static const struct snd_kcontrol_new uda1380_snd_controls[] = {
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SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
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SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
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SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
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SOC_SINGLE("Silence Switch", UDA1380_MIXER, 7, 1, 0), /* SILENCE, force DAC output to silence */
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SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
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SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
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SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
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@ -438,41 +462,28 @@ static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
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return 0;
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}
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/*
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* Flush reg cache
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* We can only write the interpolator and decimator registers
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* when the DAI is being clocked by the CPU DAI. It's up to the
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* machine and cpu DAI driver to do this before we are called.
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*/
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static int uda1380_pcm_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->card->codec;
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int reg, reg_start, reg_end, clk;
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int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_start = UDA1380_MVOL;
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reg_end = UDA1380_MIXER;
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} else {
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reg_start = UDA1380_DEC;
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reg_end = UDA1380_AGC;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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uda1380_write_reg_cache(codec, UDA1380_MIXER,
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mixer & ~R14_SILENCE);
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schedule_work(&uda1380_work);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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uda1380_write_reg_cache(codec, UDA1380_MIXER,
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mixer | R14_SILENCE);
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schedule_work(&uda1380_work);
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break;
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}
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/* FIXME disable DAC_CLK */
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clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
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uda1380_write(codec, UDA1380_CLK, clk & ~R00_DAC_CLK);
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for (reg = reg_start; reg <= reg_end; reg++) {
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pr_debug("uda1380: flush reg %x val %x:", reg,
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uda1380_read_reg_cache(codec, reg));
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uda1380_write(codec, reg, uda1380_read_reg_cache(codec, reg));
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}
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/* FIXME restore DAC_CLK */
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uda1380_write(codec, UDA1380_CLK, clk);
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return 0;
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}
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@ -538,24 +549,6 @@ static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
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uda1380_write(codec, UDA1380_CLK, clk);
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}
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static int uda1380_mute(struct snd_soc_dai *codec_dai, int mute)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u16 mute_reg = uda1380_read_reg_cache(codec, UDA1380_DEEMP) & ~R13_MTM;
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/* FIXME: mute(codec,0) is called when the magician clock is already
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* set to WSPLL, but for some unknown reason writing to interpolator
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* registers works only when clocked by SYSCLK */
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u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
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uda1380_write(codec, UDA1380_CLK, ~R00_DAC_CLK & clk);
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if (mute)
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uda1380_write(codec, UDA1380_DEEMP, mute_reg | R13_MTM);
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else
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uda1380_write(codec, UDA1380_DEEMP, mute_reg);
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uda1380_write(codec, UDA1380_CLK, clk);
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return 0;
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}
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static int uda1380_set_bias_level(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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@ -597,10 +590,9 @@ struct snd_soc_dai uda1380_dai[] = {
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.rates = UDA1380_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = {
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.trigger = uda1380_trigger,
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.hw_params = uda1380_pcm_hw_params,
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.shutdown = uda1380_pcm_shutdown,
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.prepare = uda1380_pcm_prepare,
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.digital_mute = uda1380_mute,
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.set_fmt = uda1380_set_dai_fmt_both,
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},
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},
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@ -614,10 +606,9 @@ struct snd_soc_dai uda1380_dai[] = {
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = {
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.trigger = uda1380_trigger,
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.hw_params = uda1380_pcm_hw_params,
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.shutdown = uda1380_pcm_shutdown,
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.prepare = uda1380_pcm_prepare,
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.digital_mute = uda1380_mute,
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.set_fmt = uda1380_set_dai_fmt_playback,
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},
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},
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@ -631,9 +622,9 @@ struct snd_soc_dai uda1380_dai[] = {
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = {
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.trigger = uda1380_trigger,
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.hw_params = uda1380_pcm_hw_params,
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.shutdown = uda1380_pcm_shutdown,
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.prepare = uda1380_pcm_prepare,
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.set_fmt = uda1380_set_dai_fmt_capture,
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},
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},
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@ -692,6 +683,9 @@ static int uda1380_init(struct snd_soc_device *socdev, int dac_clk)
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codec->reg_cache_step = 1;
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uda1380_reset(codec);
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uda1380_codec = codec;
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INIT_WORK(&uda1380_work, uda1380_flush_work);
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/* register pcms */
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ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
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if (ret < 0) {
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