mirror of https://gitee.com/openkylin/linux.git
Merge branch 'master' of git://git.infradead.org/users/dwmw2/solos-2.6
This commit is contained in:
commit
efb064dec6
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@ -25,6 +25,10 @@ SOLOS_ATTR_RO(RSCorrectedErrorsUp)
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SOLOS_ATTR_RO(RSUnCorrectedErrorsUp)
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SOLOS_ATTR_RO(InterleaveRDn)
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SOLOS_ATTR_RO(InterleaveRUp)
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SOLOS_ATTR_RO(BisRDn)
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SOLOS_ATTR_RO(BisRUp)
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SOLOS_ATTR_RO(INPdown)
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SOLOS_ATTR_RO(INPup)
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SOLOS_ATTR_RO(ShowtimeStart)
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SOLOS_ATTR_RO(ATURVendor)
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SOLOS_ATTR_RO(ATUCCountry)
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@ -62,6 +66,13 @@ SOLOS_ATTR_RW(Defaults)
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SOLOS_ATTR_RW(LineMode)
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SOLOS_ATTR_RW(Profile)
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SOLOS_ATTR_RW(DetectNoise)
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SOLOS_ATTR_RW(BisAForceSNRMarginDn)
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SOLOS_ATTR_RW(BisMForceSNRMarginDn)
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SOLOS_ATTR_RW(BisAMaxMargin)
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SOLOS_ATTR_RW(BisMMaxMargin)
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SOLOS_ATTR_RW(AnnexAForceSNRMarginDn)
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SOLOS_ATTR_RW(AnnexAMaxMargin)
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SOLOS_ATTR_RW(AnnexMMaxMargin)
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SOLOS_ATTR_RO(SupportedAnnexes)
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SOLOS_ATTR_RO(Status)
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SOLOS_ATTR_RO(TotalStart)
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@ -59,21 +59,29 @@
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#define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
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#define DATA_RAM_SIZE 32768
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#define BUF_SIZE 4096
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#define BUF_SIZE 2048
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#define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
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#define FPGA_PAGE 528 /* FPGA flash page size*/
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#define SOLOS_PAGE 512 /* Solos flash page size*/
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#define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
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#define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
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#define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
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#define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
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#define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
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#define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
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#define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
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#define RX_DMA_SIZE 2048
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#define FPGA_VERSION(a,b) (((a) << 8) + (b))
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#define LEGACY_BUFFERS 2
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#define DMA_SUPPORTED 4
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static int reset = 0;
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static int atmdebug = 0;
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static int firmware_upgrade = 0;
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static int fpga_upgrade = 0;
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static int db_firmware_upgrade = 0;
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static int db_fpga_upgrade = 0;
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struct pkt_hdr {
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__le16 size;
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@ -116,6 +124,8 @@ struct solos_card {
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wait_queue_head_t param_wq;
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wait_queue_head_t fw_wq;
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int using_dma;
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int fpga_version;
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int buffer_size;
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};
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@ -136,10 +146,14 @@ MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
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MODULE_PARM_DESC(atmdebug, "Print ATM data");
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MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
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MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
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MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
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MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
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module_param(reset, int, 0444);
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module_param(atmdebug, int, 0644);
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module_param(firmware_upgrade, int, 0444);
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module_param(fpga_upgrade, int, 0444);
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module_param(db_firmware_upgrade, int, 0444);
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module_param(db_fpga_upgrade, int, 0444);
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static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
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struct atm_vcc *vcc);
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@ -517,10 +531,32 @@ static int flash_upgrade(struct solos_card *card, int chip)
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if (chip == 0) {
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fw_name = "solos-FPGA.bin";
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blocksize = FPGA_BLOCK;
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} else {
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}
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if (chip == 1) {
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fw_name = "solos-Firmware.bin";
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blocksize = SOLOS_BLOCK;
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}
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if (chip == 2){
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if (card->fpga_version > LEGACY_BUFFERS){
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fw_name = "solos-db-FPGA.bin";
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blocksize = FPGA_BLOCK;
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} else {
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dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n");
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return -EPERM;
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}
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}
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if (chip == 3){
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if (card->fpga_version > LEGACY_BUFFERS){
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fw_name = "solos-Firmware.bin";
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blocksize = SOLOS_BLOCK;
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} else {
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dev_info(&card->dev->dev, "FPGA version doesn't support daughter board upgrades\n");
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return -EPERM;
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}
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}
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if (request_firmware(&fw, fw_name, &card->dev->dev))
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return -ENOENT;
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@ -536,8 +572,10 @@ static int flash_upgrade(struct solos_card *card, int chip)
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data32 = ioread32(card->config_regs + FPGA_MODE);
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/* Set mode to Chip Erase */
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dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
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chip?"Solos":"FPGA");
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if(chip == 0 || chip == 2)
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dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
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if(chip == 1 || chip == 3)
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dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
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iowrite32((chip * 2), card->config_regs + FLASH_MODE);
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@ -557,7 +595,10 @@ static int flash_upgrade(struct solos_card *card, int chip)
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/* Copy block to buffer, swapping each 16 bits */
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for(i = 0; i < blocksize; i += 4) {
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uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
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iowrite32(word, RX_BUF(card, 3) + i);
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if(card->fpga_version > LEGACY_BUFFERS)
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iowrite32(word, FLASH_BUF + i);
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else
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iowrite32(word, RX_BUF(card, 3) + i);
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}
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/* Specify block number and then trigger flash write */
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@ -630,6 +671,10 @@ void solos_bh(unsigned long card_arg)
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memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
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size = le16_to_cpu(header->size);
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if (size > (card->buffer_size - sizeof(*header))){
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dev_warn(&card->dev->dev, "Invalid buffer size\n");
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continue;
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}
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skb = alloc_skb(size + 1, GFP_ATOMIC);
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if (!skb) {
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@ -1094,12 +1139,18 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
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fpga_ver = (data32 & 0x0000FFFF);
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major_ver = ((data32 & 0xFF000000) >> 24);
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minor_ver = ((data32 & 0x00FF0000) >> 16);
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card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
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if (card->fpga_version > LEGACY_BUFFERS)
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card->buffer_size = BUF_SIZE;
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else
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card->buffer_size = OLD_BUF_SIZE;
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dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
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major_ver, minor_ver, fpga_ver);
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if (0 && fpga_ver > 27)
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if (card->fpga_version >= DMA_SUPPORTED){
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card->using_dma = 1;
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else {
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} else {
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card->using_dma = 0;
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/* Set RX empty flag for all ports */
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iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
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}
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@ -1131,6 +1182,12 @@ static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
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if (firmware_upgrade)
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flash_upgrade(card, 1);
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if (db_fpga_upgrade)
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flash_upgrade(card, 2);
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if (db_firmware_upgrade)
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flash_upgrade(card, 3);
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err = atm_init(card);
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if (err)
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goto out_free_irq;
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