mirror of https://gitee.com/openkylin/linux.git
perf_events: Update Intel extra regs shared constraints management
This patch improves the code managing the extra shared registers used for offcore_response events on Intel Nehalem/Westmere. The idea is to use static allocation instead of dynamic allocation. This simplifies greatly the get and put constraint routines for those events. The patch also renames per_core to shared_regs because the same data structure gets used whether or not HT is on. When HT is off, those events still need to coordination because they use a extra MSR that has to be shared within an event group. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20110606145703.GA7258@quad Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Stephane Eranian
Ingo Molnar
parent
a7ac67ea02
commit
efc9f05df2
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@ -44,6 +44,29 @@ do { \
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} while (0)
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#endif
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/*
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* | NHM/WSM | SNB |
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* register -------------------------------
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* | HT | no HT | HT | no HT |
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*-----------------------------------------
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* offcore | core | core | cpu | core |
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* lbr_sel | core | core | cpu | core |
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* ld_lat | cpu | core | cpu | core |
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*-----------------------------------------
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*
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* Given that there is a small number of shared regs,
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* we can pre-allocate their slot in the per-cpu
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* per-core reg tables.
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*/
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enum extra_reg_type {
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EXTRA_REG_NONE = -1, /* not used */
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EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
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EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
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EXTRA_REG_MAX /* number of entries needed */
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};
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/*
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* best effort, GUP based copy_from_user() that assumes IRQ or NMI context
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*/
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@ -132,11 +155,10 @@ struct cpu_hw_events {
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struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
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/*
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* Intel percore register state.
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* Coordinate shared resources between HT threads.
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* manage shared (per-core, per-cpu) registers
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* used on Intel NHM/WSM/SNB
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*/
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int percore_used; /* Used by this CPU? */
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struct intel_percore *per_core;
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struct intel_shared_regs *shared_regs;
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/*
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* AMD specific bits
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@ -186,27 +208,46 @@ struct cpu_hw_events {
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#define for_each_event_constraint(e, c) \
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for ((e) = (c); (e)->weight; (e)++)
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/*
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* Per register state.
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*/
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struct er_account {
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raw_spinlock_t lock; /* per-core: protect structure */
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u64 config; /* extra MSR config */
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u64 reg; /* extra MSR number */
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atomic_t ref; /* reference count */
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};
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/*
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* Extra registers for specific events.
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*
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* Some events need large masks and require external MSRs.
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* Define a mapping to these extra registers.
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* Those extra MSRs end up being shared for all events on
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* a PMU and sometimes between PMU of sibling HT threads.
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* In either case, the kernel needs to handle conflicting
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* accesses to those extra, shared, regs. The data structure
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* to manage those registers is stored in cpu_hw_event.
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*/
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struct extra_reg {
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unsigned int event;
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unsigned int msr;
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u64 config_mask;
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u64 valid_mask;
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int idx; /* per_xxx->regs[] reg index */
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};
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#define EVENT_EXTRA_REG(e, ms, m, vm) { \
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#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
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.event = (e), \
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.msr = (ms), \
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.config_mask = (m), \
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.valid_mask = (vm), \
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.idx = EXTRA_REG_##i \
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}
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#define INTEL_EVENT_EXTRA_REG(event, msr, vm) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
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#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
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#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
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#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
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union perf_capabilities {
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struct {
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@ -253,7 +294,6 @@ struct x86_pmu {
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void (*put_event_constraints)(struct cpu_hw_events *cpuc,
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struct perf_event *event);
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struct event_constraint *event_constraints;
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struct event_constraint *percore_constraints;
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void (*quirks)(void);
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int perfctr_second_write;
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@ -400,10 +440,10 @@ static inline unsigned int x86_pmu_event_addr(int index)
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*/
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static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
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{
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struct hw_perf_event_extra *reg;
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struct extra_reg *er;
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event->hw.extra_reg = 0;
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event->hw.extra_config = 0;
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reg = &event->hw.extra_reg;
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if (!x86_pmu.extra_regs)
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return 0;
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@ -413,8 +453,10 @@ static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
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continue;
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if (event->attr.config1 & ~er->valid_mask)
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return -EINVAL;
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event->hw.extra_reg = er->msr;
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event->hw.extra_config = event->attr.config1;
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reg->idx = er->idx;
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reg->config = event->attr.config1;
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reg->reg = er->msr;
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break;
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}
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return 0;
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@ -713,6 +755,9 @@ static int __x86_pmu_event_init(struct perf_event *event)
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event->hw.last_cpu = -1;
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event->hw.last_tag = ~0ULL;
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/* mark unused */
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event->hw.extra_reg.idx = EXTRA_REG_NONE;
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return x86_pmu.hw_config(event);
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}
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@ -754,8 +799,8 @@ static void x86_pmu_disable(struct pmu *pmu)
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
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u64 enable_mask)
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{
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if (hwc->extra_reg)
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wrmsrl(hwc->extra_reg, hwc->extra_config);
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if (hwc->extra_reg.reg)
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wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
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wrmsrl(hwc->config_base, hwc->config | enable_mask);
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}
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@ -1692,7 +1737,6 @@ static int validate_group(struct perf_event *event)
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fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
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if (!fake_cpuc)
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goto out;
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/*
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* the event is not yet connected with its
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* siblings therefore we must first collect
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@ -1,25 +1,15 @@
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#ifdef CONFIG_CPU_SUP_INTEL
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#define MAX_EXTRA_REGS 2
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/*
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* Per register state.
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* Per core/cpu state
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*
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* Used to coordinate shared registers between HT threads or
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* among events on a single PMU.
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*/
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struct er_account {
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int ref; /* reference count */
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unsigned int extra_reg; /* extra MSR number */
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u64 extra_config; /* extra MSR config */
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};
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/*
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* Per core state
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* This used to coordinate shared registers for HT threads.
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*/
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struct intel_percore {
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raw_spinlock_t lock; /* protect structure */
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struct er_account regs[MAX_EXTRA_REGS];
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int refcnt; /* number of threads */
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unsigned core_id;
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struct intel_shared_regs {
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struct er_account regs[EXTRA_REG_MAX];
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int refcnt; /* per-core: #HT threads */
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unsigned core_id; /* per-core: core id */
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};
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/*
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@ -88,16 +78,10 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
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static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
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{
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INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff),
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INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
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EVENT_EXTRA_END
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};
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static struct event_constraint intel_nehalem_percore_constraints[] __read_mostly =
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{
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INTEL_EVENT_CONSTRAINT(0xb7, 0),
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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@ -125,18 +109,11 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
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static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
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{
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INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff),
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INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff),
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INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
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INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
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EVENT_EXTRA_END
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};
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static struct event_constraint intel_westmere_percore_constraints[] __read_mostly =
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{
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INTEL_EVENT_CONSTRAINT(0xb7, 0),
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INTEL_EVENT_CONSTRAINT(0xbb, 0),
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_gen_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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@ -1037,65 +1014,89 @@ intel_bts_constraints(struct perf_event *event)
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return NULL;
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}
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/*
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* manage allocation of shared extra msr for certain events
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*
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* sharing can be:
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* per-cpu: to be shared between the various events on a single PMU
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* per-core: per-cpu + shared by HT threads
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*/
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static struct event_constraint *
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intel_percore_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
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__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
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struct hw_perf_event_extra *reg)
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{
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struct hw_perf_event *hwc = &event->hw;
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unsigned int e = hwc->config & ARCH_PERFMON_EVENTSEL_EVENT;
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struct event_constraint *c;
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struct intel_percore *pc;
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struct event_constraint *c = &emptyconstraint;
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struct er_account *era;
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int i;
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int free_slot;
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int found;
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if (!x86_pmu.percore_constraints || hwc->extra_alloc)
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return NULL;
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/* already allocated shared msr */
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if (reg->alloc || !cpuc->shared_regs)
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return &unconstrained;
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for (c = x86_pmu.percore_constraints; c->cmask; c++) {
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if (e != c->code)
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continue;
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era = &cpuc->shared_regs->regs[reg->idx];
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raw_spin_lock(&era->lock);
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if (!atomic_read(&era->ref) || era->config == reg->config) {
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/* lock in msr value */
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era->config = reg->config;
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era->reg = reg->reg;
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/* one more user */
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atomic_inc(&era->ref);
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/* no need to reallocate during incremental event scheduling */
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reg->alloc = 1;
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/*
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* Allocate resource per core.
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* All events using extra_reg are unconstrained.
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* Avoids calling x86_get_event_constraints()
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*
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* Must revisit if extra_reg controlling events
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* ever have constraints. Worst case we go through
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* the regular event constraint table.
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*/
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pc = cpuc->per_core;
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if (!pc)
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break;
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c = &emptyconstraint;
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raw_spin_lock(&pc->lock);
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free_slot = -1;
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found = 0;
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for (i = 0; i < MAX_EXTRA_REGS; i++) {
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era = &pc->regs[i];
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if (era->ref > 0 && hwc->extra_reg == era->extra_reg) {
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/* Allow sharing same config */
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if (hwc->extra_config == era->extra_config) {
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era->ref++;
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cpuc->percore_used = 1;
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hwc->extra_alloc = 1;
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c = NULL;
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}
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/* else conflict */
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found = 1;
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break;
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} else if (era->ref == 0 && free_slot == -1)
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free_slot = i;
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}
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if (!found && free_slot != -1) {
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era = &pc->regs[free_slot];
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era->ref = 1;
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era->extra_reg = hwc->extra_reg;
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era->extra_config = hwc->extra_config;
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cpuc->percore_used = 1;
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hwc->extra_alloc = 1;
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c = NULL;
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}
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raw_spin_unlock(&pc->lock);
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return c;
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c = &unconstrained;
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}
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raw_spin_unlock(&era->lock);
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return NULL;
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return c;
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}
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static void
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__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
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struct hw_perf_event_extra *reg)
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{
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struct er_account *era;
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/*
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* only put constraint if extra reg was actually
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* allocated. Also takes care of event which do
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* not use an extra shared reg
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*/
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if (!reg->alloc)
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return;
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era = &cpuc->shared_regs->regs[reg->idx];
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/* one fewer user */
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atomic_dec(&era->ref);
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/* allocate again next time */
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reg->alloc = 0;
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}
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static struct event_constraint *
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intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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struct event_constraint *c = NULL;
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struct hw_perf_event_extra *xreg;
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xreg = &event->hw.extra_reg;
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if (xreg->idx != EXTRA_REG_NONE)
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c = __intel_shared_reg_get_constraints(cpuc, xreg);
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return c;
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}
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static struct event_constraint *
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@ -1111,49 +1112,28 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event
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if (c)
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return c;
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c = intel_percore_constraints(cpuc, event);
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c = intel_shared_regs_constraints(cpuc, event);
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if (c)
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return c;
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return x86_get_event_constraints(cpuc, event);
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}
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static void
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intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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struct hw_perf_event_extra *reg;
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reg = &event->hw.extra_reg;
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if (reg->idx != EXTRA_REG_NONE)
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__intel_shared_reg_put_constraints(cpuc, reg);
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}
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static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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struct extra_reg *er;
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struct intel_percore *pc;
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struct er_account *era;
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struct hw_perf_event *hwc = &event->hw;
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int i, allref;
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if (!cpuc->percore_used)
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return;
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for (er = x86_pmu.extra_regs; er->msr; er++) {
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if (er->event != (hwc->config & er->config_mask))
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continue;
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pc = cpuc->per_core;
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raw_spin_lock(&pc->lock);
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for (i = 0; i < MAX_EXTRA_REGS; i++) {
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era = &pc->regs[i];
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if (era->ref > 0 &&
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era->extra_config == hwc->extra_config &&
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era->extra_reg == er->msr) {
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era->ref--;
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hwc->extra_alloc = 0;
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break;
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}
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}
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allref = 0;
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for (i = 0; i < MAX_EXTRA_REGS; i++)
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allref += pc->regs[i].ref;
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if (allref == 0)
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cpuc->percore_used = 0;
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raw_spin_unlock(&pc->lock);
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break;
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}
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intel_put_shared_regs_event_constraints(cpuc, event);
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}
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static int intel_pmu_hw_config(struct perf_event *event)
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@ -1231,20 +1211,36 @@ static __initconst const struct x86_pmu core_pmu = {
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.event_constraints = intel_core_event_constraints,
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};
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static struct intel_shared_regs *allocate_shared_regs(int cpu)
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{
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struct intel_shared_regs *regs;
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int i;
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regs = kzalloc_node(sizeof(struct intel_shared_regs),
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GFP_KERNEL, cpu_to_node(cpu));
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if (regs) {
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/*
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* initialize the locks to keep lockdep happy
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*/
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for (i = 0; i < EXTRA_REG_MAX; i++)
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raw_spin_lock_init(®s->regs[i].lock);
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regs->core_id = -1;
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}
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return regs;
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||||
}
|
||||
|
||||
static int intel_pmu_cpu_prepare(int cpu)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
|
||||
|
||||
if (!cpu_has_ht_siblings())
|
||||
if (!x86_pmu.extra_regs)
|
||||
return NOTIFY_OK;
|
||||
|
||||
cpuc->per_core = kzalloc_node(sizeof(struct intel_percore),
|
||||
GFP_KERNEL, cpu_to_node(cpu));
|
||||
if (!cpuc->per_core)
|
||||
cpuc->shared_regs = allocate_shared_regs(cpu);
|
||||
if (!cpuc->shared_regs)
|
||||
return NOTIFY_BAD;
|
||||
|
||||
raw_spin_lock_init(&cpuc->per_core->lock);
|
||||
cpuc->per_core->core_id = -1;
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1260,32 +1256,34 @@ static void intel_pmu_cpu_starting(int cpu)
|
|||
*/
|
||||
intel_pmu_lbr_reset();
|
||||
|
||||
if (!cpu_has_ht_siblings())
|
||||
if (!cpuc->shared_regs)
|
||||
return;
|
||||
|
||||
for_each_cpu(i, topology_thread_cpumask(cpu)) {
|
||||
struct intel_percore *pc = per_cpu(cpu_hw_events, i).per_core;
|
||||
struct intel_shared_regs *pc;
|
||||
|
||||
pc = per_cpu(cpu_hw_events, i).shared_regs;
|
||||
if (pc && pc->core_id == core_id) {
|
||||
kfree(cpuc->per_core);
|
||||
cpuc->per_core = pc;
|
||||
kfree(cpuc->shared_regs);
|
||||
cpuc->shared_regs = pc;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cpuc->per_core->core_id = core_id;
|
||||
cpuc->per_core->refcnt++;
|
||||
cpuc->shared_regs->core_id = core_id;
|
||||
cpuc->shared_regs->refcnt++;
|
||||
}
|
||||
|
||||
static void intel_pmu_cpu_dying(int cpu)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
|
||||
struct intel_percore *pc = cpuc->per_core;
|
||||
struct intel_shared_regs *pc;
|
||||
|
||||
pc = cpuc->shared_regs;
|
||||
if (pc) {
|
||||
if (pc->core_id == -1 || --pc->refcnt == 0)
|
||||
kfree(pc);
|
||||
cpuc->per_core = NULL;
|
||||
cpuc->shared_regs = NULL;
|
||||
}
|
||||
|
||||
fini_debug_store_on_cpu(cpu);
|
||||
|
|
@ -1436,7 +1434,6 @@ static __init int intel_pmu_init(void)
|
|||
|
||||
x86_pmu.event_constraints = intel_nehalem_event_constraints;
|
||||
x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
|
||||
x86_pmu.percore_constraints = intel_nehalem_percore_constraints;
|
||||
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
||||
x86_pmu.extra_regs = intel_nehalem_extra_regs;
|
||||
|
||||
|
|
@ -1481,7 +1478,6 @@ static __init int intel_pmu_init(void)
|
|||
intel_pmu_lbr_init_nhm();
|
||||
|
||||
x86_pmu.event_constraints = intel_westmere_event_constraints;
|
||||
x86_pmu.percore_constraints = intel_westmere_percore_constraints;
|
||||
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
||||
x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
|
||||
x86_pmu.extra_regs = intel_westmere_extra_regs;
|
||||
|
|
|
|||
|
|
@ -536,6 +536,16 @@ struct perf_branch_stack {
|
|||
|
||||
struct task_struct;
|
||||
|
||||
/*
|
||||
* extra PMU register associated with an event
|
||||
*/
|
||||
struct hw_perf_event_extra {
|
||||
u64 config; /* register value */
|
||||
unsigned int reg; /* register address or index */
|
||||
int alloc; /* extra register already allocated */
|
||||
int idx; /* index in shared_regs->regs[] */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hw_perf_event - performance event hardware details:
|
||||
*/
|
||||
|
|
@ -549,9 +559,7 @@ struct hw_perf_event {
|
|||
unsigned long event_base;
|
||||
int idx;
|
||||
int last_cpu;
|
||||
unsigned int extra_reg;
|
||||
u64 extra_config;
|
||||
int extra_alloc;
|
||||
struct hw_perf_event_extra extra_reg;
|
||||
};
|
||||
struct { /* software */
|
||||
struct hrtimer hrtimer;
|
||||
|
|
|
|||
Loading…
Reference in New Issue