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x86, mce: clean up k7.c 

Make the coding style match that of the rest of the x86 arch code.

[ Impact: cleanup ]

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Ingo Molnar 2009-04-08 12:31:20 +02:00 committed by H. Peter Anvin
parent ea2566ff80
commit efee4ca809
1 changed files with 27 additions and 15 deletions
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42
arch/x86/kernel/cpu/mcheck/k7.c
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@ -2,11 +2,10 @@
* Athlon specific Machine Check Exception Reporting * Athlon specific Machine Check Exception Reporting
* (C) Copyright 2002 Dave Jones <davej@redhat.com> * (C) Copyright 2002 Dave Jones <davej@redhat.com>
*/ */
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <asm/processor.h> #include <asm/processor.h>
@ -15,12 +14,12 @@
#include "mce.h" #include "mce.h"
/* Machine Check Handler For AMD Athlon/Duron */ /* Machine Check Handler For AMD Athlon/Duron: */
static void k7_machine_check(struct pt_regs *regs, long error_code) static void k7_machine_check(struct pt_regs *regs, long error_code)
{ {
int recover = 1;
u32 alow, ahigh, high, low; u32 alow, ahigh, high, low;
u32 mcgstl, mcgsth; u32 mcgstl, mcgsth;
int recover = 1;
int i; int i;
rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
@ -32,15 +31,19 @@ static void k7_machine_check(struct pt_regs *regs, long error_code)
for (i = 1; i < nr_mce_banks; i++) { for (i = 1; i < nr_mce_banks; i++) {
rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high); rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
if (high&(1<<31)) { if (high & (1<<31)) {
char misc[20]; char misc[20];
char addr[24]; char addr[24];
misc[0] = addr[0] = '\0';
misc[0] = '\0';
addr[0] = '\0';
if (high & (1<<29)) if (high & (1<<29))
recover |= 1; recover |= 1;
if (high & (1<<25)) if (high & (1<<25))
recover |= 2; recover |= 2;
high &= ~(1<<31); high &= ~(1<<31);
if (high & (1<<27)) { if (high & (1<<27)) {
rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh); rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
snprintf(misc, 20, "[%08x%08x]", ahigh, alow); snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
@ -49,27 +52,31 @@ static void k7_machine_check(struct pt_regs *regs, long error_code)
rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh); rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
snprintf(addr, 24, " at %08x%08x", ahigh, alow); snprintf(addr, 24, " at %08x%08x", ahigh, alow);
} }
printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n", printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
smp_processor_id(), i, high, low, misc, addr); smp_processor_id(), i, high, low, misc, addr);
/* Clear it */
/* Clear it: */
wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL); wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
/* Serialize */ /* Serialize: */
wmb(); wmb();
add_taint(TAINT_MACHINE_CHECK); add_taint(TAINT_MACHINE_CHECK);
} }
} }
if (recover&2) if (recover & 2)
panic("CPU context corrupt"); panic("CPU context corrupt");
if (recover&1) if (recover & 1)
panic("Unable to continue"); panic("Unable to continue");
printk(KERN_EMERG "Attempting to continue.\n"); printk(KERN_EMERG "Attempting to continue.\n");
mcgstl &= ~(1<<2); mcgstl &= ~(1<<2);
wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth); wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
} }
/* AMD K7 machine check is Intel like */ /* AMD K7 machine check is Intel like: */
void amd_mcheck_init(struct cpuinfo_x86 *c) void amd_mcheck_init(struct cpuinfo_x86 *c)
{ {
u32 l, h; u32 l, h;
@ -79,21 +86,26 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
return; return;
machine_check_vector = k7_machine_check; machine_check_vector = k7_machine_check;
/* Make sure the vector pointer is visible before we enable MCEs: */
wmb(); wmb();
printk(KERN_INFO "Intel machine check architecture supported.\n"); printk(KERN_INFO "Intel machine check architecture supported.\n");
rdmsr(MSR_IA32_MCG_CAP, l, h); rdmsr(MSR_IA32_MCG_CAP, l, h);
if (l & (1<<8)) /* Control register present ? */ if (l & (1<<8)) /* Control register present ? */
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
nr_mce_banks = l & 0xff; nr_mce_banks = l & 0xff;
/* Clear status for MC index 0 separately, we don't touch CTL, /*
* as some K7 Athlons cause spurious MCEs when its enabled. */ * Clear status for MC index 0 separately, we don't touch CTL,
* as some K7 Athlons cause spurious MCEs when its enabled:
*/
if (boot_cpu_data.x86 == 6) { if (boot_cpu_data.x86 == 6) {
wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0); wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
i = 1; i = 1;
} else } else
i = 0; i = 0;
for (; i < nr_mce_banks; i++) { for (; i < nr_mce_banks; i++) {
wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff); wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0); wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);