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dt: Document a compatible entry for MDIO ethernet Phys 

This describes a compatible entry of the form:
  ethernet-phy-idAAAA,BBBB
Which is modelled after the PCI structured compatible entry
(pciVVVV,DDDD.SSSS.ssss.RR)

If present the OF core will be able to use this information to
directly create the correct phy without auto probing the bus.

Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jason Gunthorpe 2014-03-19 16:15:23 -06:00 committed by David S. Miller
parent 418ebec015
commit f00e756ed1
1 changed files with 9 additions and 1 deletions
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10
Documentation/devicetree/bindings/net/phy.txt
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@ -21,10 +21,18 @@ Optional Properties:
elements. elements.
- max-speed: Maximum PHY supported speed (10, 100, 1000...) - max-speed: Maximum PHY supported speed (10, 100, 1000...)
If the phy's identifier is known then the list may contain an entry
of the form: "ethernet-phy-idAAAA.BBBB" where
AAAA - The value of the 16 bit Phy Identifier 1 register as
4 hex digits. This is the chip vendor OUI bits 3:18
BBBB - The value of the 16 bit Phy Identifier 2 register as
4 hex digits. This is the chip vendor OUI bits 19:24,
followed by 10 bits of a vendor specific ID.
Example: Example:
ethernet-phy@0 { ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
interrupt-parent = <40000>; interrupt-parent = <40000>;
interrupts = <35 1>; interrupts = <35 1>;
reg = <0>; reg = <0>;