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memory: tegra: Print out info-level once per driver probe
Probing of EMC drivers may be deferred and in this case we get duplicated info messages during kernel boot. Use dev_info_once() helper to silence the duplicated messages. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20210330230445.26619-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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@ -905,7 +905,7 @@ static int emc_init(struct tegra_emc *emc)
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else
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emc->dram_bus_width = 32;
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dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
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dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
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emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
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emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
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@ -1419,7 +1419,7 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
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goto put_hw_table;
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}
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dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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hw_version, clk_get_rate(emc->clk) / 1000000);
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/* first dummy rate-set initializes voltage state */
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@ -1475,7 +1475,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
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if (err)
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return err;
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} else {
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dev_info(&pdev->dev,
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dev_info_once(&pdev->dev,
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"no memory timings for RAM code %u found in DT\n",
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ram_code);
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}
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@ -411,7 +411,7 @@ static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
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sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
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NULL);
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dev_info(emc->dev,
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dev_info_once(emc->dev,
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"got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
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emc->num_timings,
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tegra_read_ram_code(),
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@ -429,7 +429,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)
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int err;
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if (of_get_child_count(dev->of_node) == 0) {
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dev_info(dev, "device-tree doesn't have memory timings\n");
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dev_info_once(dev, "device-tree doesn't have memory timings\n");
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return NULL;
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}
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@ -496,7 +496,7 @@ static int emc_setup_hw(struct tegra_emc *emc)
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else
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emc->dram_bus_width = 32;
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dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
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dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
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return 0;
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}
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@ -931,7 +931,7 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
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goto put_hw_table;
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}
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dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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hw_version, clk_get_rate(emc->clk) / 1000000);
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/* first dummy rate-set initializes voltage state */
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@ -998,7 +998,7 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc,
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if (err)
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return err;
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dev_info(emc->dev,
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dev_info_once(emc->dev,
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"got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
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emc->num_timings,
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tegra_read_ram_code(),
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@ -1015,7 +1015,7 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev)
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int err;
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if (of_get_child_count(dev->of_node) == 0) {
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dev_info(dev, "device-tree doesn't have memory timings\n");
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dev_info_once(dev, "device-tree doesn't have memory timings\n");
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return NULL;
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}
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@ -1503,7 +1503,7 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc)
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goto put_hw_table;
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}
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dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
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hw_version, clk_get_rate(emc->clk) / 1000000);
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/* first dummy rate-set initializes voltage state */
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