mirror of https://gitee.com/openkylin/linux.git
sparc64: Enable sun4v dma ops to use IOMMU v2 APIs
Add Hypervisor IOMMU v2 APIs pci_iotsb_map(), pci_iotsb_demap() and enable sun4v dma ops to use IOMMU v2 API for all PCIe devices with 64bit DMA mask. Signed-off-by: Tushar Dave <tushar.n.dave@oracle.com> Reviewed-by: chris hyser <chris.hyser@oracle.com> Acked-by: Sowmini Varadhan <sowmini.varadhan@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tushar Dave
David S. Miller
parent
5116ab4eab
commit
f08978b0fd
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@ -2377,6 +2377,12 @@ unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
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* iotsb_index Zero-based IOTTE number within an IOTSB.
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*/
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/* The index_count argument consists of two fields:
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* bits 63:48 #iottes and bits 47:0 iotsb_index
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*/
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#define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \
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(((u64)(__iottes) << 48UL) | ((u64)(__iotsb_index)))
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/* pci_iotsb_conf()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_PCI_IOTSB_CONF
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@ -72,34 +72,57 @@ static inline void iommu_batch_start(struct device *dev, unsigned long prot, uns
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}
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/* Interrupts must be disabled. */
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static long iommu_batch_flush(struct iommu_batch *p)
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static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
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{
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struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
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u64 *pglist = p->pglist;
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u64 index_count;
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unsigned long devhandle = pbm->devhandle;
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unsigned long prot = p->prot;
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unsigned long entry = p->entry;
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u64 *pglist = p->pglist;
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unsigned long npages = p->npages;
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unsigned long iotsb_num;
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unsigned long ret;
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long num;
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/* VPCI maj=1, min=[0,1] only supports read and write */
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if (vpci_major < 2)
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prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
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while (npages != 0) {
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long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist));
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if (unlikely(num < 0)) {
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if (printk_ratelimit())
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printk("iommu_batch_flush: IOMMU map of "
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"[%08lx:%08llx:%lx:%lx:%lx] failed with "
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"status %ld\n",
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devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist), num);
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return -1;
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if (mask <= DMA_BIT_MASK(32)) {
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num = pci_sun4v_iommu_map(devhandle,
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HV_PCI_TSBID(0, entry),
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npages,
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prot,
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__pa(pglist));
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if (unlikely(num < 0)) {
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pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
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__func__,
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devhandle,
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HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist),
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num);
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return -1;
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}
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} else {
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index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
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iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
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ret = pci_sun4v_iotsb_map(devhandle,
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iotsb_num,
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index_count,
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prot,
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__pa(pglist),
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&num);
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if (unlikely(ret != HV_EOK)) {
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pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
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__func__,
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devhandle, iotsb_num,
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index_count, prot,
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__pa(pglist), ret);
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return -1;
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}
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}
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entry += num;
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npages -= num;
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pglist += num;
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@ -111,19 +134,19 @@ static long iommu_batch_flush(struct iommu_batch *p)
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return 0;
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}
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static inline void iommu_batch_new_entry(unsigned long entry)
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static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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if (p->entry + p->npages == entry)
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return;
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if (p->entry != ~0UL)
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iommu_batch_flush(p);
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iommu_batch_flush(p, mask);
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p->entry = entry;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_add(u64 phys_page)
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static inline long iommu_batch_add(u64 phys_page, u64 mask)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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@ -131,28 +154,31 @@ static inline long iommu_batch_add(u64 phys_page)
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p->pglist[p->npages++] = phys_page;
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if (p->npages == PGLIST_NENTS)
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return iommu_batch_flush(p);
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return iommu_batch_flush(p, mask);
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_end(void)
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static inline long iommu_batch_end(u64 mask)
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{
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struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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return iommu_batch_flush(p);
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return iommu_batch_flush(p, mask);
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}
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static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp,
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unsigned long attrs)
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{
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u64 mask;
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unsigned long flags, order, first_page, npages, n;
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unsigned long prot = 0;
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struct iommu *iommu;
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struct atu *atu;
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struct iommu_map_table *tbl;
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struct page *page;
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void *ret;
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long entry;
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@ -177,14 +203,21 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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atu = iommu->atu;
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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mask = dev->coherent_dma_mask;
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if (mask <= DMA_BIT_MASK(32))
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tbl = &iommu->tbl;
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else
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tbl = &atu->tbl;
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entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == IOMMU_ERROR_CODE))
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goto range_alloc_fail;
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*dma_addrp = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));
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*dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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first_page = __pa(first_page);
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@ -196,12 +229,12 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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entry);
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for (n = 0; n < npages; n++) {
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long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
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long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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if (unlikely(iommu_batch_end(mask) < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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@ -209,7 +242,7 @@ static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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return ret;
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iommu_map_fail:
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iommu_tbl_range_free(&iommu->tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
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iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
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range_alloc_fail:
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free_pages(first_page, order);
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@ -253,18 +286,27 @@ unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
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return 0;
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}
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static void dma_4v_iommu_demap(void *demap_arg, unsigned long entry,
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unsigned long npages)
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static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
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dma_addr_t dvma, unsigned long iotsb_num,
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unsigned long entry, unsigned long npages)
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{
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u32 devhandle = *(u32 *)demap_arg;
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unsigned long num, flags;
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unsigned long ret;
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local_irq_save(flags);
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do {
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num = pci_sun4v_iommu_demap(devhandle,
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HV_PCI_TSBID(0, entry),
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npages);
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if (dvma <= DMA_BIT_MASK(32)) {
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num = pci_sun4v_iommu_demap(devhandle,
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HV_PCI_TSBID(0, entry),
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npages);
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} else {
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ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
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entry, npages, &num);
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if (unlikely(ret != HV_EOK)) {
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pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
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ret);
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}
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}
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entry += num;
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npages -= num;
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} while (npages != 0);
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@ -276,16 +318,28 @@ static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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struct atu *atu;
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struct iommu_map_table *tbl;
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unsigned long order, npages, entry;
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unsigned long iotsb_num;
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u32 devhandle;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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atu = iommu->atu;
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devhandle = pbm->devhandle;
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entry = ((dvma - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT);
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dma_4v_iommu_demap(&devhandle, entry, npages);
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iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE);
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if (dvma <= DMA_BIT_MASK(32)) {
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tbl = &iommu->tbl;
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iotsb_num = 0; /* we don't care for legacy iommu */
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} else {
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tbl = &atu->tbl;
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iotsb_num = atu->iotsb->iotsb_num;
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}
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entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
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dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
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iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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@ -297,13 +351,17 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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unsigned long attrs)
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{
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struct iommu *iommu;
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struct atu *atu;
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struct iommu_map_table *tbl;
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u64 mask;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr;
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u32 bus_addr, ret;
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unsigned long prot;
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dma_addr_t bus_addr, ret;
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long entry;
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iommu = dev->archdata.iommu;
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atu = iommu->atu;
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if (unlikely(direction == DMA_NONE))
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goto bad;
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@ -312,13 +370,19 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL,
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mask = *dev->dma_mask;
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if (mask <= DMA_BIT_MASK(32))
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tbl = &iommu->tbl;
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else
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tbl = &atu->tbl;
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entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
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(unsigned long)(-1), 0);
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if (unlikely(entry == IOMMU_ERROR_CODE))
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goto bad;
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bus_addr = (iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT));
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bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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prot = HV_PCI_MAP_ATTR_READ;
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@ -333,11 +397,11 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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iommu_batch_start(dev, prot, entry);
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for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
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long err = iommu_batch_add(base_paddr);
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long err = iommu_batch_add(base_paddr, mask);
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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if (unlikely(iommu_batch_end(mask) < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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@ -350,7 +414,7 @@ static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
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return DMA_ERROR_CODE;
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iommu_map_fail:
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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return DMA_ERROR_CODE;
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}
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@ -360,7 +424,10 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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struct atu *atu;
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struct iommu_map_table *tbl;
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unsigned long npages;
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unsigned long iotsb_num;
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long entry;
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u32 devhandle;
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@ -372,14 +439,23 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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atu = iommu->atu;
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devhandle = pbm->devhandle;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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entry = (bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT;
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dma_4v_iommu_demap(&devhandle, entry, npages);
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iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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if (bus_addr <= DMA_BIT_MASK(32)) {
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iotsb_num = 0; /* we don't care for legacy iommu */
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tbl = &iommu->tbl;
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} else {
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iotsb_num = atu->iotsb->iotsb_num;
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tbl = &atu->tbl;
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}
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entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
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dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
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iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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}
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static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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@ -393,12 +469,17 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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unsigned long seg_boundary_size;
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int outcount, incount, i;
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struct iommu *iommu;
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struct atu *atu;
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struct iommu_map_table *tbl;
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u64 mask;
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unsigned long base_shift;
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long err;
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BUG_ON(direction == DMA_NONE);
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iommu = dev->archdata.iommu;
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atu = iommu->atu;
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if (nelems == 0 || !iommu)
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return 0;
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@ -424,7 +505,15 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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max_seg_size = dma_get_max_seg_size(dev);
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seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
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base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT;
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mask = *dev->dma_mask;
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if (mask <= DMA_BIT_MASK(32))
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tbl = &iommu->tbl;
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else
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tbl = &atu->tbl;
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base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
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for_each_sg(sglist, s, nelems, i) {
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unsigned long paddr, npages, entry, out_entry = 0, slen;
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@ -437,27 +526,26 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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/* Allocate iommu entries for that segment */
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paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
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npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
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entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages,
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entry = iommu_tbl_range_alloc(dev, tbl, npages,
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&handle, (unsigned long)(-1), 0);
|
||||
|
||||
/* Handle failure */
|
||||
if (unlikely(entry == IOMMU_ERROR_CODE)) {
|
||||
if (printk_ratelimit())
|
||||
printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
|
||||
" npages %lx\n", iommu, paddr, npages);
|
||||
pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
|
||||
tbl, paddr, npages);
|
||||
goto iommu_map_failed;
|
||||
}
|
||||
|
||||
iommu_batch_new_entry(entry);
|
||||
iommu_batch_new_entry(entry, mask);
|
||||
|
||||
/* Convert entry to a dma_addr_t */
|
||||
dma_addr = iommu->tbl.table_map_base + (entry << IO_PAGE_SHIFT);
|
||||
dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
|
||||
dma_addr |= (s->offset & ~IO_PAGE_MASK);
|
||||
|
||||
/* Insert into HW table */
|
||||
paddr &= IO_PAGE_MASK;
|
||||
while (npages--) {
|
||||
err = iommu_batch_add(paddr);
|
||||
err = iommu_batch_add(paddr, mask);
|
||||
if (unlikely(err < 0L))
|
||||
goto iommu_map_failed;
|
||||
paddr += IO_PAGE_SIZE;
|
||||
|
|
@ -492,7 +580,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
dma_next = dma_addr + slen;
|
||||
}
|
||||
|
||||
err = iommu_batch_end();
|
||||
err = iommu_batch_end(mask);
|
||||
|
||||
if (unlikely(err < 0L))
|
||||
goto iommu_map_failed;
|
||||
|
|
@ -515,7 +603,7 @@ static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
|
|||
vaddr = s->dma_address & IO_PAGE_MASK;
|
||||
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
||||
IO_PAGE_SIZE);
|
||||
iommu_tbl_range_free(&iommu->tbl, vaddr, npages,
|
||||
iommu_tbl_range_free(tbl, vaddr, npages,
|
||||
IOMMU_ERROR_CODE);
|
||||
/* XXX demap? XXX */
|
||||
s->dma_address = DMA_ERROR_CODE;
|
||||
|
|
@ -536,13 +624,16 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|||
struct pci_pbm_info *pbm;
|
||||
struct scatterlist *sg;
|
||||
struct iommu *iommu;
|
||||
struct atu *atu;
|
||||
unsigned long flags, entry;
|
||||
unsigned long iotsb_num;
|
||||
u32 devhandle;
|
||||
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
||||
iommu = dev->archdata.iommu;
|
||||
pbm = dev->archdata.host_controller;
|
||||
atu = iommu->atu;
|
||||
devhandle = pbm->devhandle;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
|
@ -552,15 +643,24 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|||
dma_addr_t dma_handle = sg->dma_address;
|
||||
unsigned int len = sg->dma_length;
|
||||
unsigned long npages;
|
||||
struct iommu_map_table *tbl = &iommu->tbl;
|
||||
struct iommu_map_table *tbl;
|
||||
unsigned long shift = IO_PAGE_SHIFT;
|
||||
|
||||
if (!len)
|
||||
break;
|
||||
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
||||
|
||||
if (dma_handle <= DMA_BIT_MASK(32)) {
|
||||
iotsb_num = 0; /* we don't care for legacy iommu */
|
||||
tbl = &iommu->tbl;
|
||||
} else {
|
||||
iotsb_num = atu->iotsb->iotsb_num;
|
||||
tbl = &atu->tbl;
|
||||
}
|
||||
entry = ((dma_handle - tbl->table_map_base) >> shift);
|
||||
dma_4v_iommu_demap(&devhandle, entry, npages);
|
||||
iommu_tbl_range_free(&iommu->tbl, dma_handle, npages,
|
||||
dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
|
||||
entry, npages);
|
||||
iommu_tbl_range_free(tbl, dma_handle, npages,
|
||||
IOMMU_ERROR_CODE);
|
||||
sg = sg_next(sg);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,4 +99,15 @@ unsigned long pci_sun4v_iotsb_conf(unsigned long devhandle,
|
|||
unsigned long pci_sun4v_iotsb_bind(unsigned long devhandle,
|
||||
unsigned long iotsb_num,
|
||||
unsigned int pci_device);
|
||||
unsigned long pci_sun4v_iotsb_map(unsigned long devhandle,
|
||||
unsigned long iotsb_num,
|
||||
unsigned long iotsb_index_iottes,
|
||||
unsigned long io_attributes,
|
||||
unsigned long io_page_list_pa,
|
||||
long *mapped);
|
||||
unsigned long pci_sun4v_iotsb_demap(unsigned long devhandle,
|
||||
unsigned long iotsb_num,
|
||||
unsigned long iotsb_index,
|
||||
unsigned long iottes,
|
||||
unsigned long *demapped);
|
||||
#endif /* !(_PCI_SUN4V_H) */
|
||||
|
|
|
|||
|
|
@ -392,3 +392,39 @@ ENTRY(pci_sun4v_iotsb_bind)
|
|||
retl
|
||||
nop
|
||||
ENDPROC(pci_sun4v_iotsb_bind)
|
||||
|
||||
/*
|
||||
* %o0: devhandle
|
||||
* %o1: iotsb_num/iotsb_handle
|
||||
* %o2: index_count
|
||||
* %o3: iotte_attributes
|
||||
* %o4: io_page_list_p
|
||||
* %o5: &mapped
|
||||
*
|
||||
* returns %o0: status
|
||||
* %o1: #mapped
|
||||
*/
|
||||
ENTRY(pci_sun4v_iotsb_map)
|
||||
mov %o5, %g1
|
||||
mov HV_FAST_PCI_IOTSB_MAP, %o5
|
||||
ta HV_FAST_TRAP
|
||||
retl
|
||||
stx %o1, [%g1]
|
||||
ENDPROC(pci_sun4v_iotsb_map)
|
||||
|
||||
/*
|
||||
* %o0: devhandle
|
||||
* %o1: iotsb_num/iotsb_handle
|
||||
* %o2: iotsb_index
|
||||
* %o3: #iottes
|
||||
* %o4: &demapped
|
||||
*
|
||||
* returns %o0: status
|
||||
* %o1: #demapped
|
||||
*/
|
||||
ENTRY(pci_sun4v_iotsb_demap)
|
||||
mov HV_FAST_PCI_IOTSB_DEMAP, %o5
|
||||
ta HV_FAST_TRAP
|
||||
retl
|
||||
stx %o1, [%o4]
|
||||
ENDPROC(pci_sun4v_iotsb_demap)
|
||||
|
|
|
|||
Loading…
Reference in New Issue