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arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC 

Correct X-Gene 2 timer interrupt polarity as low-level triggered.

Signed-off-by: Duc Dang <dhdang@apm.com>
This commit is contained in:
Duc Dang 2016-06-20 18:26:35 -07:00
parent 0e999c79c0
commit f0a78909bd
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
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@ -198,10 +198,10 @@ pmu {
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff04>, /* Non-secure Phys IRQ */ <1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff04>, /* Virt IRQ */ <1 14 0xff08>, /* Virt IRQ */
<1 15 0xff04>; /* Hyp IRQ */ <1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };