mirror of https://gitee.com/openkylin/linux.git
drm/nouveau: allow accelerated buffer moves even when gr isn't present
There's no need to avoid using copy engines if gr init fails for some reason (usually missing FW, or incomplete bring-up). It's not terribly useful for an end-user, but it'll slightly speed up suspend/resume when saving fb contents, and allow for host/ce code to be validated. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
0f9976dd97
commit
f0eee9aec0
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@ -282,18 +282,134 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
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}
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static void
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nouveau_accel_fini(struct nouveau_drm *drm)
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nouveau_accel_ce_fini(struct nouveau_drm *drm)
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{
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nouveau_channel_idle(drm->cechan);
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nvif_object_fini(&drm->ttm.copy);
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nouveau_channel_del(&drm->cechan);
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}
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static void
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nouveau_accel_ce_init(struct nouveau_drm *drm)
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{
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struct nvif_device *device = &drm->client.device;
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int ret = 0;
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/* Allocate channel that has access to a (preferably async) copy
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* engine, to use for TTM buffer moves.
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*/
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if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
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ret = nouveau_channel_new(drm, device,
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nvif_fifo_runlist_ce(device), 0,
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true, &drm->cechan);
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} else
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if (device->info.chipset >= 0xa3 &&
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device->info.chipset != 0xaa &&
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device->info.chipset != 0xac) {
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/* Prior to Kepler, there's only a single runlist, so all
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* engines can be accessed from any channel.
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*
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* We still want to use a separate channel though.
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*/
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ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
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&drm->cechan);
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}
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if (ret)
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NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
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}
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static void
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nouveau_accel_gr_fini(struct nouveau_drm *drm)
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{
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nouveau_channel_idle(drm->channel);
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nvif_object_fini(&drm->ntfy);
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nvkm_gpuobj_del(&drm->notify);
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nvif_object_fini(&drm->nvsw);
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nouveau_channel_del(&drm->channel);
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}
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nouveau_channel_idle(drm->cechan);
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nvif_object_fini(&drm->ttm.copy);
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nouveau_channel_del(&drm->cechan);
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static void
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nouveau_accel_gr_init(struct nouveau_drm *drm)
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{
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struct nvif_device *device = &drm->client.device;
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u32 arg0, arg1;
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int ret;
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/* Allocate channel that has access to the graphics engine. */
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if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
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arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
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arg1 = 1;
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} else {
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arg0 = NvDmaFB;
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arg1 = NvDmaTT;
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}
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ret = nouveau_channel_new(drm, device, arg0, arg1, false,
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&drm->channel);
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if (ret) {
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NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
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nouveau_accel_gr_fini(drm);
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return;
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}
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/* A SW class is used on pre-NV50 HW to assist with handling the
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* synchronisation of page flips, as well as to implement fences
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* on TNT/TNT2 HW that lacks any kind of support in host.
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*/
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if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
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ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
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nouveau_abi16_swclass(drm), NULL, 0,
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&drm->nvsw);
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if (ret == 0) {
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ret = RING_SPACE(drm->channel, 2);
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if (ret == 0) {
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BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
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OUT_RING (drm->channel, drm->nvsw.handle);
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}
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}
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if (ret) {
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NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
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nouveau_accel_gr_fini(drm);
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return;
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}
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}
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/* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
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* even if notification is never requested, so, allocate a ctxdma on
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* any GPU where it's possible we'll end up using M2MF for BO moves.
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*/
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if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
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ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
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&drm->notify);
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if (ret) {
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NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
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nouveau_accel_gr_fini(drm);
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return;
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}
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ret = nvif_object_init(&drm->channel->user, NvNotify0,
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NV_DMA_IN_MEMORY,
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&(struct nv_dma_v0) {
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.target = NV_DMA_V0_TARGET_VRAM,
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.access = NV_DMA_V0_ACCESS_RDWR,
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.start = drm->notify->addr,
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.limit = drm->notify->addr + 31
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}, sizeof(struct nv_dma_v0),
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&drm->ntfy);
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if (ret) {
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nouveau_accel_gr_fini(drm);
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return;
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}
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}
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}
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static void
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nouveau_accel_fini(struct nouveau_drm *drm)
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{
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nouveau_accel_ce_fini(drm);
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nouveau_accel_gr_fini(drm);
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if (drm->fence)
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nouveau_fence(drm)->dtor(drm);
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}
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@ -303,23 +419,16 @@ nouveau_accel_init(struct nouveau_drm *drm)
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{
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struct nvif_device *device = &drm->client.device;
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struct nvif_sclass *sclass;
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u32 arg0, arg1;
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int ret, i, n;
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if (nouveau_noaccel)
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return;
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/* Initialise global support for channels, and synchronisation. */
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ret = nouveau_channels_init(drm);
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if (ret)
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return;
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if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
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ret = nvif_user_init(device);
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if (ret)
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return;
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}
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/* initialise synchronisation routines */
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/*XXX: this is crap, but the fence/channel stuff is a little
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* backwards in some places. this will be fixed.
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*/
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@ -366,84 +475,18 @@ nouveau_accel_init(struct nouveau_drm *drm)
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return;
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}
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if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
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ret = nouveau_channel_new(drm, &drm->client.device,
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nvif_fifo_runlist_ce(device), 0,
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true, &drm->cechan);
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/* Volta requires access to a doorbell register for kickoff. */
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if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
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ret = nvif_user_init(device);
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if (ret)
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NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
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arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
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arg1 = 1;
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} else
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if (device->info.chipset >= 0xa3 &&
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device->info.chipset != 0xaa &&
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device->info.chipset != 0xac) {
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ret = nouveau_channel_new(drm, &drm->client.device,
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NvDmaFB, NvDmaTT, false,
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&drm->cechan);
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if (ret)
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NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
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arg0 = NvDmaFB;
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arg1 = NvDmaTT;
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} else {
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arg0 = NvDmaFB;
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arg1 = NvDmaTT;
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}
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ret = nouveau_channel_new(drm, &drm->client.device,
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arg0, arg1, false, &drm->channel);
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if (ret) {
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NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
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nouveau_accel_fini(drm);
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return;
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}
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if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
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ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
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nouveau_abi16_swclass(drm), NULL, 0,
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&drm->nvsw);
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if (ret == 0) {
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ret = RING_SPACE(drm->channel, 2);
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if (ret == 0) {
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BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
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OUT_RING (drm->channel, drm->nvsw.handle);
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}
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}
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if (ret) {
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NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
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nouveau_accel_fini(drm);
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return;
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}
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}
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if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
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ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0,
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false, NULL, &drm->notify);
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if (ret) {
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NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
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nouveau_accel_fini(drm);
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return;
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}
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ret = nvif_object_init(&drm->channel->user, NvNotify0,
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NV_DMA_IN_MEMORY,
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&(struct nv_dma_v0) {
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.target = NV_DMA_V0_TARGET_VRAM,
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.access = NV_DMA_V0_ACCESS_RDWR,
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.start = drm->notify->addr,
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.limit = drm->notify->addr + 31
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}, sizeof(struct nv_dma_v0),
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&drm->ntfy);
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if (ret) {
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nouveau_accel_fini(drm);
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return;
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}
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}
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/* Allocate channels we need to support various functions. */
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nouveau_accel_gr_init(drm);
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nouveau_accel_ce_init(drm);
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/* Initialise accelerated TTM buffer moves. */
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nouveau_bo_move_init(drm);
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}
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