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ARM: dts: r8a7744: Add SMP support 

Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".

Also add cpu1 phandle node to the PMU interrupt-affinity property.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Biju Das 2018-11-30 15:26:21 +00:00 committed by Simon Horman
parent d94369fe69
commit f1546da8a5
1 changed files with 32 additions and 6 deletions
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38
arch/arm/boot/dts/r8a7744.dtsi
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@ -49,6 +49,7 @@ can_clk: can {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@ -69,6 +70,25 @@ cpu0: cpu@0 {
< 375000 1000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
<1312500 1000000>,
<1125000 1000000>,
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
};
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@ -96,7 +116,7 @@ pmu {
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
@ -250,6 +270,12 @@ cpg: clock-controller@e6150000 {
#reset-cells = <1>;
};
apmu@e6152000 {
compatible = "renesas,r8a7744-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe6160000 0 0x100>;
@ -483,7 +509,7 @@ gic: interrupt-controller@f1001000 {
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@ -520,10 +546,10 @@ prr: chipid@ff000044 {
timer {
compatible = "arm,armv7-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */