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OMAPDSS: HDMI: Modify logic to configure MCLK 

The MCLK mode defines a factor to divide the clock that is used to
generate the Audio Clock Regeneration packets, MCLK.

The divisor is not used when the CTS value is calculated by HW.
When the value is calculated by SW, it depends on the silicon
revision.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Ricardo Neri 2012-01-31 15:56:16 -06:00 committed by Tomi Valkeinen
parent d8989d96eb
commit f15511e23d
1 changed files with 4 additions and 2 deletions
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6
drivers/video/omap2/dss/hdmi.c
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@ -667,13 +667,15 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
core_cfg.aud_par_busclk = 0;
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
core_cfg.use_mclk = false;
core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
} else {
core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
core_cfg.use_mclk = true;
core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
}
if (core_cfg.use_mclk)
core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
core_cfg.en_spdif = false;
/* Use sample frequency from channel status word */