mirror of https://gitee.com/openkylin/linux.git
drm/i915: get mode clock when reading the pipe config v9
We need this for comparing modes between configuration changes.
The tricky part is to allow us to reuse the new get_clock stuff to
recover the lvds clock on gen2/3 when neither the vbt has an lvds mode
nor the panel a (useful) EDID.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
v3: drop get_clock now that the pixel_multiply has been moved into
get_pipe_config
v4: re-add get_clock; we need to get the pixel multiplier in the
encoder, so need to calculate the clock value after the encoder's
get_config is called
v5: drop hsw clock_get, still needs to be written
v6: add fuzzy clock check (Daniel)
v7: wrap fuzzy clock check under !IS_HASWELL
use port_clock field rather than a new CPU eDP clock field in crtc_config
v8: remove stale pixel_multiplier sets (Daniel)
multiply by pixel_multiplier in 9xx clock get too (Daniel)
v9: make sure we set pixel_multiplier before calling clock_get from mode_get
for LVDS (Daniel)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Add some explanation to the commit message about why we have
to jump through a few hoops. Also remove the rebase-fail hunk from
intel_sdvo.c]
[danvet: Squash in the fixup from Jesse to also call ->get_clock in
the modeset state checker.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
2385bdf078
commit
f1f644dc66
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@ -367,6 +367,7 @@ struct drm_i915_display_funcs {
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* fills out the pipe-config with the hw state. */
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bool (*get_pipe_config)(struct intel_crtc *,
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struct intel_crtc_config *);
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void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
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int (*crtc_mode_set)(struct drm_crtc *crtc,
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int x, int y,
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struct drm_framebuffer *old_fb);
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@ -45,6 +45,11 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config);
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static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config);
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typedef struct {
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int min, max;
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} intel_range_t;
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@ -6853,11 +6858,12 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
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}
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/* Returns the clock of the currently programmed mode of the given pipe. */
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static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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int pipe = pipe_config->cpu_transcoder;
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u32 dpll = I915_READ(DPLL(pipe));
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u32 fp;
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intel_clock_t clock;
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@ -6896,7 +6902,8 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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default:
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DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
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"mode\n", (int)(dpll & DPLL_MODE_MASK));
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return 0;
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pipe_config->adjusted_mode.clock = 0;
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return;
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}
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if (IS_PINEVIEW(dev))
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@ -6933,12 +6940,55 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
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}
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}
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/* XXX: It would be nice to validate the clocks, but we can't reuse
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* i830PllIsValid() because it relies on the xf86_config connector
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* configuration being accurate, which it isn't necessarily.
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pipe_config->adjusted_mode.clock = clock.dot *
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pipe_config->pixel_multiplier;
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}
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static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
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int link_freq, repeat;
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u64 clock;
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u32 link_m, link_n;
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repeat = pipe_config->pixel_multiplier;
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/*
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* The calculation for the data clock is:
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* pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
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* But we want to avoid losing precison if possible, so:
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* pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
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*
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* and the link clock is simpler:
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* link_clock = (m * link_clock * repeat) / n
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*/
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return clock.dot;
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/*
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* We need to get the FDI or DP link clock here to derive
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* the M/N dividers.
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*
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* For FDI, we read it from the BIOS or use a fixed 2.7GHz.
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* For DP, it's either 1.62GHz or 2.7GHz.
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* We do our calculations in 10*MHz since we don't need much precison.
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*/
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if (pipe_config->has_pch_encoder)
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link_freq = intel_fdi_link_freq(dev) * 10000;
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else
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link_freq = pipe_config->port_clock;
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link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
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link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
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if (!link_m || !link_n)
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return;
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clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
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do_div(clock, link_n);
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pipe_config->adjusted_mode.clock = clock;
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}
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/** Returns the currently programmed mode of the given pipe. */
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@ -6949,6 +6999,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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struct drm_display_mode *mode;
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struct intel_crtc_config pipe_config;
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int htot = I915_READ(HTOTAL(cpu_transcoder));
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int hsync = I915_READ(HSYNC(cpu_transcoder));
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int vtot = I915_READ(VTOTAL(cpu_transcoder));
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@ -6958,7 +7009,18 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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if (!mode)
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return NULL;
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mode->clock = intel_crtc_clock_get(dev, crtc);
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/*
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* Construct a pipe_config sufficient for getting the clock info
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* back out of crtc_clock_get.
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*
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* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
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* to use a real value here instead.
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*/
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pipe_config.cpu_transcoder = intel_crtc->pipe;
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pipe_config.pixel_multiplier = 1;
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i9xx_crtc_clock_get(intel_crtc, &pipe_config);
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mode->clock = pipe_config.adjusted_mode.clock;
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mode->hdisplay = (htot & 0xffff) + 1;
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mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
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mode->hsync_start = (hsync & 0xffff) + 1;
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@ -8019,6 +8081,28 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
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}
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static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
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struct intel_crtc_config *new)
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{
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int clock1, clock2, diff;
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clock1 = cur->adjusted_mode.clock;
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clock2 = new->adjusted_mode.clock;
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if (clock1 == clock2)
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return true;
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if (!clock1 || !clock2)
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return false;
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diff = abs(clock1 - clock2);
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if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
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return true;
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return false;
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}
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#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
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list_for_each_entry((intel_crtc), \
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&(dev)->mode_config.crtc_list, \
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@ -8124,6 +8208,15 @@ intel_pipe_config_compare(struct drm_device *dev,
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#undef PIPE_CONF_CHECK_FLAGS
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#undef PIPE_CONF_QUIRK
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if (!IS_HASWELL(dev)) {
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if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
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DRM_ERROR("mismatch in clock (expected %d, found %d\n",
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current_config->adjusted_mode.clock,
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pipe_config->adjusted_mode.clock);
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return false;
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}
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}
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return true;
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}
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@ -8249,8 +8342,12 @@ check_crtc_state(struct drm_device *dev)
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base.head) {
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if (encoder->base.crtc != &crtc->base)
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continue;
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if (encoder->get_config)
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if (encoder->get_config &&
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dev_priv->display.get_clock) {
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encoder->get_config(encoder, &pipe_config);
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dev_priv->display.get_clock(crtc,
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&pipe_config);
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}
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}
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WARN(crtc->active != active,
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@ -9253,6 +9350,7 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_plane = ironlake_update_plane;
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} else if (HAS_PCH_SPLIT(dev)) {
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dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
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dev_priv->display.get_clock = ironlake_crtc_clock_get;
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dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
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dev_priv->display.crtc_enable = ironlake_crtc_enable;
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dev_priv->display.crtc_disable = ironlake_crtc_disable;
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@ -9260,6 +9358,7 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_plane = ironlake_update_plane;
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} else if (IS_VALLEYVIEW(dev)) {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_clock = i9xx_crtc_clock_get;
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dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
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dev_priv->display.crtc_enable = valleyview_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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@ -9267,6 +9366,7 @@ static void intel_init_display(struct drm_device *dev)
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dev_priv->display.update_plane = i9xx_update_plane;
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} else {
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dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
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dev_priv->display.get_clock = i9xx_crtc_clock_get;
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dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
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dev_priv->display.crtc_enable = i9xx_crtc_enable;
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dev_priv->display.crtc_disable = i9xx_crtc_disable;
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@ -9813,8 +9913,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
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if (encoder->get_hw_state(encoder, &pipe)) {
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crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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encoder->base.crtc = &crtc->base;
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if (encoder->get_config)
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if (encoder->get_config &&
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dev_priv->display.get_clock) {
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encoder->get_config(encoder, &crtc->config);
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dev_priv->display.get_clock(crtc,
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&crtc->config);
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}
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} else {
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encoder->base.crtc = NULL;
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}
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@ -1355,6 +1355,13 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
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}
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pipe_config->adjusted_mode.flags |= flags;
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if (dp_to_dig_port(intel_dp)->port == PORT_A) {
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if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
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pipe_config->port_clock = 162000;
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else
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pipe_config->port_clock = 270000;
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}
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}
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static void intel_disable_dp(struct intel_encoder *encoder)
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