mirror of https://gitee.com/openkylin/linux.git
tg3: Add 5720 H2BMC support
This patch adds support for the new Host to BMC feature. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
9b91b5f178
commit
f2096f94b5
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@ -4390,6 +4390,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
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static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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{
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u32 val;
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int err;
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if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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@ -4400,7 +4401,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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err = tg3_setup_copper_phy(tp, force_reset);
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
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u32 val, scale;
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u32 scale;
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val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
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if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
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@ -4415,17 +4416,20 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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tw32(GRC_MISC_CFG, val);
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}
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val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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(6 << TX_LENGTHS_IPG_SHIFT);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
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val |= tr32(MAC_TX_LENGTHS) &
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(TX_LENGTHS_JMB_FRM_LEN_MSK |
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TX_LENGTHS_CNT_DWN_VAL_MSK);
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if (tp->link_config.active_speed == SPEED_1000 &&
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tp->link_config.active_duplex == DUPLEX_HALF)
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tw32(MAC_TX_LENGTHS,
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((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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(6 << TX_LENGTHS_IPG_SHIFT) |
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(0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
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tw32(MAC_TX_LENGTHS, val |
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(0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
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else
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tw32(MAC_TX_LENGTHS,
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((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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(6 << TX_LENGTHS_IPG_SHIFT) |
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(32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
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tw32(MAC_TX_LENGTHS, val |
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(32 << TX_LENGTHS_SLOT_TIME_SHIFT));
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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if (netif_carrier_ok(tp->dev)) {
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@ -4437,7 +4441,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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}
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if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
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u32 val = tr32(PCIE_PWR_MGMT_THRESH);
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val = tr32(PCIE_PWR_MGMT_THRESH);
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if (!netif_carrier_ok(tp->dev))
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val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
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tp->pwrmgmt_thresh;
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@ -8164,10 +8168,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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/* The slot time is changed by tg3_setup_phy if we
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* run at gigabit with half duplex.
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*/
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tw32(MAC_TX_LENGTHS,
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(2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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(6 << TX_LENGTHS_IPG_SHIFT) |
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(32 << TX_LENGTHS_SLOT_TIME_SHIFT));
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val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
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(6 << TX_LENGTHS_IPG_SHIFT) |
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(32 << TX_LENGTHS_SLOT_TIME_SHIFT);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
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val |= tr32(MAC_TX_LENGTHS) &
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(TX_LENGTHS_JMB_FRM_LEN_MSK |
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TX_LENGTHS_CNT_DWN_VAL_MSK);
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tw32(MAC_TX_LENGTHS, val);
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/* Receive rules. */
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tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
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@ -8214,6 +8224,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
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rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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@ -8447,9 +8460,17 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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}
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tp->tx_mode = TX_MODE_ENABLE;
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if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
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val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
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tp->tx_mode &= ~val;
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tp->tx_mode |= tr32(MAC_TX_MODE) & val;
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}
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tw32_f(MAC_TX_MODE, tp->tx_mode);
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udelay(100);
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@ -13880,7 +13901,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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/* Initialize data/descriptor byte/word swapping. */
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val = tr32(GRC_MODE);
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val &= GRC_MODE_HOST_STACKUP;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
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val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
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GRC_MODE_WORD_SWAP_B2HRX_DATA |
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GRC_MODE_B2HRX_ENABLE |
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GRC_MODE_HTX2B_ENABLE |
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GRC_MODE_HOST_STACKUP);
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else
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val &= GRC_MODE_HOST_STACKUP;
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tw32(GRC_MODE, val | tp->grc_mode);
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tg3_switch_clocks(tp);
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@ -479,6 +479,8 @@
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#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
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#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
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#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
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#define TX_MODE_JMB_FRM_LEN 0x00400000
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#define TX_MODE_CNT_DN_MODE 0x00800000
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#define MAC_TX_STATUS 0x00000460
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#define TX_STATUS_XOFFED 0x00000001
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#define TX_STATUS_SENT_XOFF 0x00000002
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@ -493,6 +495,8 @@
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#define TX_LENGTHS_IPG_SHIFT 8
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#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
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#define TX_LENGTHS_IPG_CRS_SHIFT 12
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#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
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#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
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#define MAC_RX_MODE 0x00000468
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#define RX_MODE_RESET 0x00000001
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#define RX_MODE_ENABLE 0x00000002
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@ -1330,6 +1334,7 @@
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#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
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#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
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#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
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#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
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#define RDMAC_STATUS 0x00004804
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#define RDMAC_STATUS_TGTABORT 0x00000004
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#define RDMAC_STATUS_MSTABORT 0x00000008
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@ -1622,6 +1627,8 @@
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#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
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#define GRC_MODE_BSWAP_DATA 0x00000010
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#define GRC_MODE_WSWAP_DATA 0x00000020
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#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
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#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
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#define GRC_MODE_SPLITHDR 0x00000100
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#define GRC_MODE_NOFRM_CRACKING 0x00000200
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#define GRC_MODE_INCL_CRC 0x00000400
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@ -1629,8 +1636,10 @@
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#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
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#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
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#define GRC_MODE_FORCE_PCI32BIT 0x00008000
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#define GRC_MODE_B2HRX_ENABLE 0x00008000
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#define GRC_MODE_HOST_STACKUP 0x00010000
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#define GRC_MODE_HOST_SENDBDS 0x00020000
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#define GRC_MODE_HTX2B_ENABLE 0x00040000
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#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
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#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
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#define GRC_MODE_PCIE_TL_SEL 0x00000000
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