mirror of https://gitee.com/openkylin/linux.git
drm fixes for 5.13-rc6
drm: - auth locking fix ttm: - locking fix amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes msm: - NULL ptr deref fix - CP_PROTECT reg programming fix - incorrect register shift fix - DSI blank screen fix sun4i: - hdmi output probing fix mcde: - DSI pipeline calc fix vc4: - out of bounds fix -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmDC2ZcACgkQDHTzWXnE hr4Quw/+JjLIJAIgOCmwP1KoJawDkhBkyV8nyKWmHjoL6QAGJBomaeTV/3pNE++s Ia2LruGYf8cjenNuIW80vsp2BV906SOjzpwNq2mp/X5oBLeX+1RbgPrzSP91timU jVV+6C4kUurbhJs8xC/GM4/skanq7MIJuBQQz+dlZzRe6/aeUTpOAVaoBoUwQnU6 NTCWmqaWSxvuL5dzhsrgOubciiv/UmgjltHPThjAtxM76K0gBnmUiw77rgoT8LCe l7yulaSb6O+ayLtZ5plYunaTB9KQQQZG0OLyXq0bpQpp3jWL7NHoXk0bygI+2y3A 76tvLUk2/e2FrTRRGrFk/nzn8DvdG4P6YrzGLu9Cww8IrU2bYI0mdedd7V7kx/Ri Buucb7HXovlbfCNKz0i0BOvYTdaJ6z2+Ljb0Kbxv/DsiD/ZbjmJG6ZitgqbVaI9U 1XtjMEZmTZL5osvquJ4oPeOYnA3K++bjO3+1NYFOzWPZt3/LPZ08BGWrX5W57UrB 8JcJ+t2v2JHfmkNaTBrD7HQAG9OMHzbEaCgVRmSxPNwVmgpTOlQMDjS/8I6o1axV D0Fo93AtJXwQ5tsjqrdUXZcBWFCBGZQIFtmcYEfosRzrM7/G4SC3kxoZ96YG7e1t 3oXQdTP6M6rPSLTe7/jCUxMEV8oT18L+UIPFHvq7Rq2PDr1vEus= =cy9b -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Another week of fixes, nothing too crazy, but a few all over the place. Two locking fixes in the core/ttm area, a couple of small driver fixes (radeon, sun4i, mcde, vc4). Then msm and amdgpu have a set of fixes each, mostly for smaller things, though the msm has a DSI fix for a black screen. I haven't seen any intel fixes this week so they may have a few that may or may not wait for next week. drm: - auth locking fix ttm: - locking fix amdgpu: - Use kvzmalloc in amdgu_bo_create - Use drm_dbg_kms for reporting failure to get a GEM FB - Fix some register offsets for Sienna Cichlid - Fix fall-through warning radeon: - memcpy_to/from_io fixes msm: - NULL ptr deref fix - CP_PROTECT reg programming fix - incorrect register shift fix - DSI blank screen fix sun4i: - hdmi output probing fix mcde: - DSI pipeline calc fix vc4: - out of bounds fix" * tag 'drm-fixes-2021-06-11' of git://anongit.freedesktop.org/drm/drm: drm/msm/dsi: Stash away calculated vco frequency on recalc drm: Lock pointer access in drm_master_release() drm/mcde: Fix off by 10^3 in calculation drm/msm/a6xx: avoid shadow NULL reference in failure path drm/msm/a6xx: fix incorrectly set uavflagprd_inv field for A650 drm/msm/a6xx: update/fix CP_PROTECT initialization radeon: use memcpy_to/fromio for UVD fw upload drm/amd/pm: Fix fall-through warning for Clang drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FB drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_create drm/msm: Init mm_list before accessing it for use_vram path drm: Fix use-after-free read in drm_getunique() drm/vc4: fix vc4_atomic_commit_tail() logic drm/ttm: fix deref of bo->ttm without holding the lock v2 drm/sun4i: dw-hdmi: Make HDMI PHY into a platform device
This commit is contained in:
Linus Torvalds
commit
f21b807c3c
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@ -1057,7 +1057,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev,
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return 0;
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err:
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drm_err(dev, "Failed to init gem fb: %d\n", ret);
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drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
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rfb->base.obj[0] = NULL;
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return ret;
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}
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@ -1094,7 +1094,7 @@ int amdgpu_display_gem_fb_verify_and_init(
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return 0;
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err:
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drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
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drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
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rfb->base.obj[0] = NULL;
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return ret;
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}
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@ -100,7 +100,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
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kfree(ubo->metadata);
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}
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kfree(bo);
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kvfree(bo);
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}
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/**
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@ -552,7 +552,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
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BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
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*bo_ptr = NULL;
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bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
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bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
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@ -173,6 +173,9 @@
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#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
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#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
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#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
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#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
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#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)
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#define GFX_RLCG_GC_WRITE (0x0 << 28)
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#define GFX_RLCG_GC_READ (0x1 << 28)
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@ -1480,8 +1483,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
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(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
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scratch_reg3 = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
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spare_int = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
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spare_int = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
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+ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
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} else {
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spare_int = adev->rmmio +
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(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
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}
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grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
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grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
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@ -7349,9 +7359,15 @@ static int gfx_v10_0_hw_fini(void *handle)
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if (amdgpu_sriov_vf(adev)) {
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gfx_v10_0_cp_gfx_enable(adev, false);
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/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
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tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
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tmp &= 0xffffff00;
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WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
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if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
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tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
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tmp &= 0xffffff00;
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WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
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} else {
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tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
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tmp &= 0xffffff00;
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WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
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}
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return 0;
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}
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@ -810,6 +810,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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break;
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case AMD_DPM_FORCED_LEVEL_MANUAL:
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data->fine_grain_enabled = 1;
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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break;
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@ -314,9 +314,10 @@ int drm_master_open(struct drm_file *file_priv)
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void drm_master_release(struct drm_file *file_priv)
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{
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struct drm_device *dev = file_priv->minor->dev;
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struct drm_master *master = file_priv->master;
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struct drm_master *master;
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mutex_lock(&dev->master_mutex);
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master = file_priv->master;
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if (file_priv->magic)
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idr_remove(&file_priv->master->magic_map, file_priv->magic);
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@ -118,17 +118,18 @@ int drm_getunique(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_unique *u = data;
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struct drm_master *master = file_priv->master;
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struct drm_master *master;
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mutex_lock(&master->dev->master_mutex);
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mutex_lock(&dev->master_mutex);
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master = file_priv->master;
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if (u->unique_len >= master->unique_len) {
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if (copy_to_user(u->unique, master->unique, master->unique_len)) {
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mutex_unlock(&master->dev->master_mutex);
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mutex_unlock(&dev->master_mutex);
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return -EFAULT;
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}
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}
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u->unique_len = master->unique_len;
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mutex_unlock(&master->dev->master_mutex);
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mutex_unlock(&dev->master_mutex);
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return 0;
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}
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@ -577,7 +577,7 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d,
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* porches and sync.
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*/
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/* (ps/s) / (pixels/s) = ps/pixels */
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pclk = DIV_ROUND_UP_ULL(1000000000000, mode->clock);
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pclk = DIV_ROUND_UP_ULL(1000000000000, (mode->clock * 1000));
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dev_dbg(d->dev, "picoseconds between two pixels: %llu\n",
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pclk);
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@ -157,7 +157,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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* GPU registers so we need to add 0x1a800 to the register value on A630
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* to get the right value from PM4.
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*/
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get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
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get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
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rbmemptr_stats(ring, index, alwayson_start));
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/* Invalidate CCU depth and color */
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@ -187,7 +187,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
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rbmemptr_stats(ring, index, cpcycles_end));
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get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
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get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
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rbmemptr_stats(ring, index, alwayson_end));
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/* Write the fence to the scratch register */
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@ -206,8 +206,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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OUT_RING(ring, submit->seqno);
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trace_msm_gpu_submit_flush(submit,
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gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
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REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
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gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
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REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
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a6xx_flush(gpu, ring);
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}
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@ -462,6 +462,113 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
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gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
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}
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/* For a615, a616, a618, A619, a630, a640 and a680 */
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static const u32 a6xx_protect[] = {
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A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
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A6XX_PROTECT_RDONLY(0x00501, 0x0005),
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A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
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A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
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A6XX_PROTECT_NORDWR(0x00510, 0x0000),
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A6XX_PROTECT_NORDWR(0x00534, 0x0000),
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A6XX_PROTECT_NORDWR(0x00800, 0x0082),
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A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
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A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
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A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
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A6XX_PROTECT_NORDWR(0x00900, 0x004d),
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A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
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A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
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A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
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A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
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A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
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A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
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A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
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A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
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A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
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A6XX_PROTECT_NORDWR(0x09624, 0x01db),
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A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
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A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
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A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
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A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
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A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
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A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
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A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
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A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
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A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
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A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
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A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
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};
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/* These are for a620 and a650 */
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static const u32 a650_protect[] = {
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A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
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A6XX_PROTECT_RDONLY(0x00501, 0x0005),
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A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
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A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
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A6XX_PROTECT_NORDWR(0x00510, 0x0000),
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A6XX_PROTECT_NORDWR(0x00534, 0x0000),
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A6XX_PROTECT_NORDWR(0x00800, 0x0082),
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A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
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A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
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A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
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A6XX_PROTECT_NORDWR(0x00900, 0x004d),
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A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
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A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
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A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
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A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
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A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
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A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
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A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
|
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A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
|
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A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
|
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A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
|
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A6XX_PROTECT_NORDWR(0x09624, 0x01db),
|
||||
A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
|
||||
A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
|
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A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
|
||||
A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
|
||||
A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
|
||||
A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
|
||||
A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
|
||||
A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
|
||||
A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
|
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A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
|
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A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
|
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A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
|
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A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
|
||||
A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
|
||||
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
|
||||
A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
|
||||
A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
|
||||
};
|
||||
|
||||
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
const u32 *regs = a6xx_protect;
|
||||
unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
|
||||
|
||||
if (adreno_is_a650(adreno_gpu)) {
|
||||
regs = a650_protect;
|
||||
count = ARRAY_SIZE(a650_protect);
|
||||
count_max = 48;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable access protection to privileged registers, fault on an access
|
||||
* protect violation and select the last span to protect from the start
|
||||
* address all the way to the end of the register address space
|
||||
*/
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
|
||||
|
||||
for (i = 0; i < count - 1; i++)
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
|
||||
/* last CP_PROTECT to have "infinite" length on the last entry */
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
|
||||
}
|
||||
|
||||
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
|
|
@ -489,7 +596,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
|
|||
rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
|
||||
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
|
||||
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
|
||||
uavflagprd_inv >> 4 | lower_bit << 1);
|
||||
uavflagprd_inv << 4 | lower_bit << 1);
|
||||
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
|
||||
}
|
||||
|
||||
|
|
@ -776,41 +883,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
|
|||
}
|
||||
|
||||
/* Protect registers from the CP */
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
|
||||
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
|
||||
A6XX_PROTECT_RDONLY(0x600, 0x51));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
|
||||
A6XX_PROTECT_RDONLY(0xfc00, 0x3));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
|
||||
A6XX_PROTECT_RDONLY(0x0, 0x4f9));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
|
||||
A6XX_PROTECT_RDONLY(0x501, 0xa));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
|
||||
A6XX_PROTECT_RDONLY(0x511, 0x44));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
|
||||
A6XX_PROTECT_RW(0xbe20, 0x11f3));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
|
||||
A6XX_PROTECT_RDONLY(0x980, 0x4));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
|
||||
a6xx_set_cp_protect(gpu);
|
||||
|
||||
/* Enable expanded apriv for targets that support it */
|
||||
if (gpu->hw_apriv) {
|
||||
|
|
@ -1211,7 +1284,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
|
||||
if (a6xx_gpu->shadow_bo)
|
||||
for (i = 0; i < gpu->nr_rings; i++)
|
||||
a6xx_gpu->shadow[i] = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ struct a6xx_gpu {
|
|||
* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
|
||||
* registers starting at _reg.
|
||||
*/
|
||||
#define A6XX_PROTECT_RW(_reg, _len) \
|
||||
#define A6XX_PROTECT_NORDWR(_reg, _len) \
|
||||
((1 << 31) | \
|
||||
(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
|
||||
|
||||
|
|
|
|||
|
|
@ -432,6 +432,7 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
|
|||
pll_freq += div_u64(tmp64, multiplier);
|
||||
|
||||
vco_rate = pll_freq;
|
||||
pll_10nm->vco_current_rate = vco_rate;
|
||||
|
||||
DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
|
||||
pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
|
||||
|
|
|
|||
|
|
@ -460,6 +460,7 @@ static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
|
|||
pll_freq += div_u64(tmp64, multiplier);
|
||||
|
||||
vco_rate = pll_freq;
|
||||
pll_7nm->vco_current_rate = vco_rate;
|
||||
|
||||
DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
|
||||
pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
|
||||
|
|
|
|||
|
|
@ -1241,6 +1241,13 @@ static struct drm_gem_object *_msm_gem_new(struct drm_device *dev,
|
|||
|
||||
to_msm_bo(obj)->vram_node = &vma->node;
|
||||
|
||||
/* Call chain get_pages() -> update_inactive() tries to
|
||||
* access msm_obj->mm_list, but it is not initialized yet.
|
||||
* To avoid NULL pointer dereference error, initialize
|
||||
* mm_list to be empty.
|
||||
*/
|
||||
INIT_LIST_HEAD(&msm_obj->mm_list);
|
||||
|
||||
msm_gem_lock(obj);
|
||||
pages = get_pages(obj);
|
||||
msm_gem_unlock(obj);
|
||||
|
|
|
|||
|
|
@ -286,7 +286,7 @@ int radeon_uvd_resume(struct radeon_device *rdev)
|
|||
if (rdev->uvd.vcpu_bo == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
|
||||
memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
|
||||
|
||||
size = radeon_bo_size(rdev->uvd.vcpu_bo);
|
||||
size -= rdev->uvd_fw->size;
|
||||
|
|
@ -294,7 +294,7 @@ int radeon_uvd_resume(struct radeon_device *rdev)
|
|||
ptr = rdev->uvd.cpu_addr;
|
||||
ptr += rdev->uvd_fw->size;
|
||||
|
||||
memset(ptr, 0, size);
|
||||
memset_io((void __iomem *)ptr, 0, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
|
|||
goto err_disable_clk_tmds;
|
||||
}
|
||||
|
||||
ret = sun8i_hdmi_phy_probe(hdmi, phy_node);
|
||||
ret = sun8i_hdmi_phy_get(hdmi, phy_node);
|
||||
of_node_put(phy_node);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't get the HDMI PHY\n");
|
||||
|
|
@ -242,7 +242,6 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
|
|||
|
||||
cleanup_encoder:
|
||||
drm_encoder_cleanup(encoder);
|
||||
sun8i_hdmi_phy_remove(hdmi);
|
||||
err_disable_clk_tmds:
|
||||
clk_disable_unprepare(hdmi->clk_tmds);
|
||||
err_assert_ctrl_reset:
|
||||
|
|
@ -263,7 +262,6 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
|
|||
struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
|
||||
|
||||
dw_hdmi_unbind(hdmi->hdmi);
|
||||
sun8i_hdmi_phy_remove(hdmi);
|
||||
clk_disable_unprepare(hdmi->clk_tmds);
|
||||
reset_control_assert(hdmi->rst_ctrl);
|
||||
gpiod_set_value(hdmi->ddc_en, 0);
|
||||
|
|
@ -320,7 +318,32 @@ static struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
|
|||
.of_match_table = sun8i_dw_hdmi_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun8i_dw_hdmi_pltfm_driver);
|
||||
|
||||
static int __init sun8i_dw_hdmi_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_register(&sun8i_hdmi_phy_driver);
|
||||
if (ret) {
|
||||
platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit sun8i_dw_hdmi_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
|
||||
platform_driver_unregister(&sun8i_hdmi_phy_driver);
|
||||
}
|
||||
|
||||
module_init(sun8i_dw_hdmi_init);
|
||||
module_exit(sun8i_dw_hdmi_exit);
|
||||
|
||||
MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
|
||||
MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
|
||||
|
|
|
|||
|
|
@ -195,14 +195,15 @@ struct sun8i_dw_hdmi {
|
|||
struct gpio_desc *ddc_en;
|
||||
};
|
||||
|
||||
extern struct platform_driver sun8i_hdmi_phy_driver;
|
||||
|
||||
static inline struct sun8i_dw_hdmi *
|
||||
encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
|
||||
{
|
||||
return container_of(encoder, struct sun8i_dw_hdmi, encoder);
|
||||
}
|
||||
|
||||
int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
|
||||
void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi);
|
||||
int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
|
||||
|
||||
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
|
||||
void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include "sun8i_dw_hdmi.h"
|
||||
|
||||
|
|
@ -597,10 +598,30 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
||||
int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
||||
{
|
||||
struct platform_device *pdev = of_find_device_by_node(node);
|
||||
struct sun8i_hdmi_phy *phy;
|
||||
|
||||
if (!pdev)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
phy = platform_get_drvdata(pdev);
|
||||
if (!phy)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
hdmi->phy = phy;
|
||||
|
||||
put_device(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device *dev = hdmi->dev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct sun8i_hdmi_phy *phy;
|
||||
struct resource res;
|
||||
void __iomem *regs;
|
||||
|
|
@ -704,7 +725,7 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
|||
clk_prepare_enable(phy->clk_phy);
|
||||
}
|
||||
|
||||
hdmi->phy = phy;
|
||||
platform_set_drvdata(pdev, phy);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -728,9 +749,9 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
|||
return ret;
|
||||
}
|
||||
|
||||
void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
|
||||
static int sun8i_hdmi_phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sun8i_hdmi_phy *phy = hdmi->phy;
|
||||
struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(phy->clk_mod);
|
||||
clk_disable_unprepare(phy->clk_bus);
|
||||
|
|
@ -744,4 +765,14 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
|
|||
clk_put(phy->clk_pll1);
|
||||
clk_put(phy->clk_mod);
|
||||
clk_put(phy->clk_bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver sun8i_hdmi_phy_driver = {
|
||||
.probe = sun8i_hdmi_phy_probe,
|
||||
.remove = sun8i_hdmi_phy_remove,
|
||||
.driver = {
|
||||
.name = "sun8i-hdmi-phy",
|
||||
.of_match_table = sun8i_hdmi_phy_of_table,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1172,7 +1172,10 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
|
|||
if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked, NULL))
|
||||
return -EBUSY;
|
||||
|
||||
if (!ttm_bo_get_unless_zero(bo)) {
|
||||
if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) ||
|
||||
bo->ttm->page_flags & TTM_PAGE_FLAG_SG ||
|
||||
bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED ||
|
||||
!ttm_bo_get_unless_zero(bo)) {
|
||||
if (locked)
|
||||
dma_resv_unlock(bo->base.resv);
|
||||
return -EBUSY;
|
||||
|
|
|
|||
|
|
@ -143,14 +143,8 @@ int ttm_device_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx,
|
|||
|
||||
for (j = 0; j < TTM_MAX_BO_PRIORITY; ++j) {
|
||||
list_for_each_entry(bo, &man->lru[j], lru) {
|
||||
uint32_t num_pages;
|
||||
uint32_t num_pages = PFN_UP(bo->base.size);
|
||||
|
||||
if (!bo->ttm || !ttm_tt_is_populated(bo->ttm) ||
|
||||
bo->ttm->page_flags & TTM_PAGE_FLAG_SG ||
|
||||
bo->ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)
|
||||
continue;
|
||||
|
||||
num_pages = bo->ttm->num_pages;
|
||||
ret = ttm_bo_swapout(bo, ctx, gfp_flags);
|
||||
/* ttm_bo_swapout has dropped the lru_lock */
|
||||
if (!ret)
|
||||
|
|
|
|||
|
|
@ -372,7 +372,7 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
if (!old_hvs_state->fifo_state[channel].in_use)
|
||||
continue;
|
||||
|
||||
ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[i].pending_commit);
|
||||
ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit);
|
||||
if (ret)
|
||||
drm_err(dev, "Timed out waiting for commit\n");
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue