mirror of https://gitee.com/openkylin/linux.git
Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
This commit is contained in:
Stephen Boyd
commit
f2626ba965
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@ -450,8 +450,10 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra,
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struct emc_timing *timing = tegra->timings + (i++);
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err = load_one_timing_from_dt(tegra, timing, child);
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if (err)
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if (err) {
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of_node_put(child);
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return err;
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}
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timing->ram_code = ram_code;
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}
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@ -499,9 +501,9 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
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* fuses until the apbmisc driver is loaded.
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*/
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err = load_timings_from_dt(tegra, node, node_ram_code);
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of_node_put(node);
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if (err)
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return ERR_PTR(err);
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of_node_put(node);
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break;
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}
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@ -11,6 +11,7 @@ enum clk_id {
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tegra_clk_afi,
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tegra_clk_amx,
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tegra_clk_amx1,
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tegra_clk_apb2ape,
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tegra_clk_apbdma,
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tegra_clk_apbif,
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tegra_clk_ape,
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@ -86,15 +86,21 @@
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#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
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PLLE_SS_CNTL_SSC_BYP)
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#define PLLE_SS_MAX_MASK 0x1ff
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#define PLLE_SS_MAX_VAL 0x25
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#define PLLE_SS_MAX_VAL_TEGRA114 0x25
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#define PLLE_SS_MAX_VAL_TEGRA210 0x21
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#define PLLE_SS_INC_MASK (0xff << 16)
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#define PLLE_SS_INC_VAL (0x1 << 16)
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#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
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#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
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#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
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#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
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#define PLLE_SS_COEFFICIENTS_MASK \
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(PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
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#define PLLE_SS_COEFFICIENTS_VAL \
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(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
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#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
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(PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
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PLLE_SS_INCINTRV_VAL_TEGRA114)
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#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
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(PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
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PLLE_SS_INCINTRV_VAL_TEGRA210)
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#define PLLE_AUX_PLLP_SEL BIT(2)
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#define PLLE_AUX_USE_LOCKDET BIT(3)
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@ -880,7 +886,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll)
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static int clk_plle_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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struct tegra_clk_pll_freq_table sel;
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u32 val;
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int err;
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@ -1378,7 +1384,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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u32 val;
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int ret;
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unsigned long flags = 0;
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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return -EINVAL;
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@ -1401,7 +1407,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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val |= PLLE_MISC_IDDQ_SW_CTRL;
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val &= ~PLLE_MISC_IDDQ_SW_VALUE;
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val |= PLLE_MISC_PLLE_PTS;
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val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
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val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
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pll_writel_misc(val, pll);
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udelay(5);
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@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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val = pll_readl(PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
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val &= ~PLLE_SS_COEFFICIENTS_MASK;
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val |= PLLE_SS_COEFFICIENTS_VAL;
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val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
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pll_writel(val, PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
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pll_writel(val, PLLE_SS_CTRL, pll);
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@ -2012,9 +2018,9 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table sel;
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u32 val;
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int ret;
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int ret = 0;
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unsigned long flags = 0;
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unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
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unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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return -EINVAL;
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@ -2022,22 +2028,20 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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val = pll_readl(pll->params->aux_reg, pll);
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if (val & PLLE_AUX_SEQ_ENABLE)
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goto out;
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val = pll_readl_base(pll);
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val &= ~BIT(30); /* Disable lock override */
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pll_writel_base(val, pll);
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val = pll_readl(pll->params->aux_reg, pll);
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val |= PLLE_AUX_ENABLE_SWCTL;
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val &= ~PLLE_AUX_SEQ_ENABLE;
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pll_writel(val, pll->params->aux_reg, pll);
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udelay(1);
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val = pll_readl_misc(pll);
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val |= PLLE_MISC_LOCK_ENABLE;
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val |= PLLE_MISC_IDDQ_SW_CTRL;
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val &= ~PLLE_MISC_IDDQ_SW_VALUE;
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val |= PLLE_MISC_PLLE_PTS;
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val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
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val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
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pll_writel_misc(val, pll);
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udelay(5);
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@ -2067,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
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val = pll_readl(PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
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val &= ~PLLE_SS_COEFFICIENTS_MASK;
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val |= PLLE_SS_COEFFICIENTS_VAL;
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val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
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pll_writel(val, PLLE_SS_CTRL, pll);
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val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
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pll_writel(val, PLLE_SS_CTRL, pll);
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@ -2104,15 +2108,25 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw)
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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/* If PLLE HW sequencer is enabled, SW should not disable PLLE */
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val = pll_readl(pll->params->aux_reg, pll);
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if (val & PLLE_AUX_SEQ_ENABLE)
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goto out;
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val = pll_readl_base(pll);
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val &= ~PLLE_BASE_ENABLE;
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pll_writel_base(val, pll);
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val = pll_readl(pll->params->aux_reg, pll);
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val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
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pll_writel(val, pll->params->aux_reg, pll);
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val = pll_readl_misc(pll);
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val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
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pll_writel_misc(val, pll);
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udelay(1);
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out:
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = {
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XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
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XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
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MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
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MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
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MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
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MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
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MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
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MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
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@ -782,7 +782,7 @@ static struct tegra_periph_init_data periph_clks[] = {
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NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
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MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
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MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
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MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),
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I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
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MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
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MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
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MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
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@ -829,6 +829,7 @@ static struct tegra_periph_init_data gate_clks[] = {
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GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
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GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
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GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
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GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
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};
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static struct tegra_periph_init_data div_clks[] = {
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@ -67,7 +67,7 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p", "pll_p_out4", "unused",
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"unused", "pll_x", "pll_x_out0" };
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const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
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static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
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.gen = gen4,
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.sclk_parents = sclk_parents,
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.cclk_g_parents = cclk_g_parents,
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@ -93,7 +93,7 @@ static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unu
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"unused", "unused", "unused", "unused",
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"dfllCPU_out" };
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const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
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static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
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.gen = gen5,
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.sclk_parents = sclk_parents_gen5,
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.cclk_g_parents = cclk_g_parents_gen5,
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@ -171,7 +171,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
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*dt_clk = clk;
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}
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void __init tegra_super_clk_init(void __iomem *clk_base,
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static void __init tegra_super_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base,
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struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *params,
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@ -59,8 +59,8 @@
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#define PLLC3_MISC3 0x50c
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#define PLLM_BASE 0x90
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#define PLLM_MISC0 0x9c
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#define PLLM_MISC1 0x98
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#define PLLM_MISC2 0x9c
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#define PLLP_BASE 0xa0
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#define PLLP_MISC0 0xac
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#define PLLP_MISC1 0x680
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@ -99,7 +99,7 @@
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#define PLLC4_MISC0 0x5a8
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#define PLLC4_OUT 0x5e4
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#define PLLMB_BASE 0x5e8
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#define PLLMB_MISC0 0x5ec
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#define PLLMB_MISC1 0x5ec
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#define PLLA1_BASE 0x6a4
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#define PLLA1_MISC0 0x6a8
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#define PLLA1_MISC1 0x6ac
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@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
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};
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static const char *mux_pllmcp_clkm[] = {
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"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
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"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
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"pll_p",
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};
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#define mux_pllmcp_clkm_idx NULL
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@ -367,12 +368,12 @@ static const char *mux_pllmcp_clkm[] = {
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/* PLLMB */
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#define PLLMB_BASE_LOCK (1 << 27)
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#define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18)
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#define PLLMB_MISC0_IDDQ (1 << 17)
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#define PLLMB_MISC0_LOCK_ENABLE (1 << 16)
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#define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
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#define PLLMB_MISC1_IDDQ (1 << 17)
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#define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
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#define PLLMB_MISC0_DEFAULT_VALUE 0x00030000
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#define PLLMB_MISC0_WRITE_MASK 0x0007ffff
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#define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
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#define PLLMB_MISC1_WRITE_MASK 0x0007ffff
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||||
|
||||
/* PLLP */
|
||||
#define PLLP_BASE_OVERRIDE (1 << 28)
|
||||
|
|
@ -457,7 +458,8 @@ static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
|
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PLLCX_MISC3_WRITE_MASK);
|
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}
|
||||
|
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void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
|
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static void tegra210_pllcx_set_defaults(const char *name,
|
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struct tegra_clk_pll *pllcx)
|
||||
{
|
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pllcx->params->defaults_set = true;
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|
||||
|
|
@ -482,22 +484,22 @@ void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
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udelay(1);
|
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}
|
||||
|
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void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
|
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static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
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tegra210_pllcx_set_defaults("PLL_C", pllcx);
|
||||
}
|
||||
|
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void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_C2", pllcx);
|
||||
}
|
||||
|
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void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
|
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static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
|
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{
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tegra210_pllcx_set_defaults("PLL_C3", pllcx);
|
||||
}
|
||||
|
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void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_A1", pllcx);
|
||||
}
|
||||
|
|
@ -507,7 +509,7 @@ void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
|||
* PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
|
||||
* Fractional SDM is allowed to provide exact audio rates.
|
||||
*/
|
||||
void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
||||
static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + plla->params->base_reg);
|
||||
|
|
@ -559,7 +561,7 @@ void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
|||
* PLLD
|
||||
* PLL with fractional SDM.
|
||||
*/
|
||||
void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
|
||||
static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
|
||||
{
|
||||
u32 val;
|
||||
u32 mask = 0xffff;
|
||||
|
|
@ -698,7 +700,7 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
||||
static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
||||
{
|
||||
plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
|
||||
PLLD2_MISC1_CFG_DEFAULT_VALUE,
|
||||
|
|
@ -706,7 +708,7 @@ void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
|||
PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
|
||||
}
|
||||
|
||||
void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
||||
static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
||||
{
|
||||
plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
|
||||
PLLDP_MISC1_CFG_DEFAULT_VALUE,
|
||||
|
|
@ -719,7 +721,7 @@ void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
|||
* Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
|
||||
* VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
|
||||
*/
|
||||
void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
||||
static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
||||
{
|
||||
plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
|
||||
}
|
||||
|
|
@ -728,7 +730,7 @@ void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
|||
* PLLRE
|
||||
* VCO is exposed to the clock tree directly along with post-divider output
|
||||
*/
|
||||
void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
|
||||
static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
|
||||
|
|
@ -780,13 +782,13 @@ static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
|
|||
{
|
||||
unsigned long input_rate;
|
||||
|
||||
if (!IS_ERR_OR_NULL(hw->clk)) {
|
||||
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
/* cf rate */
|
||||
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
|
||||
} else {
|
||||
if (!IS_ERR_OR_NULL(hw->clk))
|
||||
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
else
|
||||
input_rate = 38400000;
|
||||
}
|
||||
|
||||
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
|
||||
|
||||
switch (input_rate) {
|
||||
case 12000000:
|
||||
|
|
@ -841,7 +843,7 @@ static void pllx_check_defaults(struct tegra_clk_pll *pll)
|
|||
PLLX_MISC5_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
||||
static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
||||
{
|
||||
u32 val;
|
||||
u32 step_a, step_b;
|
||||
|
|
@ -901,7 +903,7 @@ void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
|||
}
|
||||
|
||||
/* PLLMB */
|
||||
void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
||||
static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
||||
{
|
||||
u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
|
||||
|
||||
|
|
@ -914,15 +916,15 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
|||
* PLL is ON: check if defaults already set, then set those
|
||||
* that can be updated in flight.
|
||||
*/
|
||||
val = PLLMB_MISC0_DEFAULT_VALUE & (~PLLMB_MISC0_IDDQ);
|
||||
mask = PLLMB_MISC0_LOCK_ENABLE | PLLMB_MISC0_LOCK_OVERRIDE;
|
||||
val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
|
||||
mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
|
||||
_pll_misc_chk_default(clk_base, pllmb->params, 0, val,
|
||||
~mask & PLLMB_MISC0_WRITE_MASK);
|
||||
~mask & PLLMB_MISC1_WRITE_MASK);
|
||||
|
||||
/* Enable lock detect */
|
||||
val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
val &= ~mask;
|
||||
val |= PLLMB_MISC0_DEFAULT_VALUE & mask;
|
||||
val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
|
||||
writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
udelay(1);
|
||||
|
||||
|
|
@ -930,7 +932,7 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
|||
}
|
||||
|
||||
/* set IDDQ, enable lock detect */
|
||||
writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE,
|
||||
writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
|
||||
clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
udelay(1);
|
||||
}
|
||||
|
|
@ -960,7 +962,7 @@ static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
|
|||
~mask & PLLP_MISC1_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
|
||||
static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
|
||||
|
|
@ -1022,7 +1024,7 @@ static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control)
|
|||
~mask & PLLU_MISC1_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
|
||||
static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
|
||||
{
|
||||
u32 val = readl_relaxed(clk_base + pllu->params->base_reg);
|
||||
|
||||
|
|
@ -1212,7 +1214,8 @@ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
|
|||
cfg->m *= PLL_SDM_COEFF;
|
||||
}
|
||||
|
||||
unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
|
||||
static unsigned long
|
||||
tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long vco_min = params->vco_min;
|
||||
|
|
@ -1386,7 +1389,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.mdiv_default = 3,
|
||||
.div_nmp = &pllc_nmp,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1425,7 +1428,7 @@ static struct tegra_clk_pll_params pll_c2_params = {
|
|||
.ext_misc_reg[2] = PLLC2_MISC2,
|
||||
.ext_misc_reg[3] = PLLC2_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc2_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1455,7 +1458,7 @@ static struct tegra_clk_pll_params pll_c3_params = {
|
|||
.ext_misc_reg[2] = PLLC3_MISC2,
|
||||
.ext_misc_reg[3] = PLLC3_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc3_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1505,7 +1508,6 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
|
|||
.base_reg = PLLC4_BASE,
|
||||
.misc_reg = PLLC4_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLC4_MISC0,
|
||||
|
|
@ -1517,8 +1519,7 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
|
|||
.div_nmp = &pllss_nmp,
|
||||
.freq_table = pll_c4_vco_freq_table,
|
||||
.set_defaults = tegra210_pllc4_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
||||
|
|
@ -1559,15 +1560,15 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.vco_min = 800000000,
|
||||
.vco_max = 1866000000,
|
||||
.base_reg = PLLM_BASE,
|
||||
.misc_reg = PLLM_MISC1,
|
||||
.misc_reg = PLLM_MISC2,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLM_MISC0,
|
||||
.iddq_reg = PLLM_MISC2,
|
||||
.iddq_bit_idx = PLLM_IDDQ_BIT,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLM_MISC0,
|
||||
.ext_misc_reg[0] = PLLM_MISC1,
|
||||
.ext_misc_reg[0] = PLLM_MISC2,
|
||||
.ext_misc_reg[1] = PLLM_MISC1,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllm_nmp,
|
||||
|
|
@ -1586,19 +1587,18 @@ static struct tegra_clk_pll_params pll_mb_params = {
|
|||
.vco_min = 800000000,
|
||||
.vco_max = 1866000000,
|
||||
.base_reg = PLLMB_BASE,
|
||||
.misc_reg = PLLMB_MISC0,
|
||||
.misc_reg = PLLMB_MISC1,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLMB_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLMB_MISC0,
|
||||
.iddq_reg = PLLMB_MISC1,
|
||||
.iddq_bit_idx = PLLMB_IDDQ_BIT,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLMB_MISC0,
|
||||
.ext_misc_reg[0] = PLLMB_MISC1,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllm_nmp,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = tegra210_pllmb_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1671,7 +1671,6 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.base_reg = PLLRE_BASE,
|
||||
.misc_reg = PLLRE_MISC0,
|
||||
.lock_mask = PLLRE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLRE_MISC0,
|
||||
|
|
@ -1681,8 +1680,7 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllre_nmp,
|
||||
.freq_table = pll_re_vco_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllre_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1712,7 +1710,6 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.base_reg = PLLP_BASE,
|
||||
.misc_reg = PLLP_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLP_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLP_MISC0,
|
||||
.iddq_bit_idx = PLLXP_IDDQ_BIT,
|
||||
|
|
@ -1721,8 +1718,7 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.fixed_rate = 408000000,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllp_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1750,7 +1746,7 @@ static struct tegra_clk_pll_params pll_a1_params = {
|
|||
.ext_misc_reg[2] = PLLA1_MISC2,
|
||||
.ext_misc_reg[3] = PLLA1_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _plla1_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1787,7 +1783,6 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.base_reg = PLLA_BASE,
|
||||
.misc_reg = PLLA_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLA_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
|
|
@ -1802,8 +1797,7 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.ext_misc_reg[1] = PLLA_MISC1,
|
||||
.ext_misc_reg[2] = PLLA_MISC2,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
|
||||
.set_defaults = tegra210_plla_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
|
|
@ -1836,7 +1830,6 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.base_reg = PLLD_BASE,
|
||||
.misc_reg = PLLD_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLD_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.iddq_reg = PLLD_MISC0,
|
||||
.iddq_bit_idx = PLLD_IDDQ_BIT,
|
||||
|
|
@ -1850,7 +1843,7 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.ext_misc_reg[0] = PLLD_MISC0,
|
||||
.ext_misc_reg[1] = PLLD_MISC1,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.mdiv_default = 1,
|
||||
.set_defaults = tegra210_plld_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
|
|
@ -1876,7 +1869,6 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.base_reg = PLLD2_BASE,
|
||||
.misc_reg = PLLD2_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLD2_BASE,
|
||||
.iddq_bit_idx = PLLSS_IDDQ_BIT,
|
||||
|
|
@ -1897,7 +1889,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.mdiv_default = 1,
|
||||
.freq_table = tegra210_pll_d2_freq_table,
|
||||
.set_defaults = tegra210_plld2_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
.adjust_vco = tegra210_clk_adjust_vco_min,
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||||
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|
@ -1920,7 +1912,6 @@ static struct tegra_clk_pll_params pll_dp_params = {
|
|||
.base_reg = PLLDP_BASE,
|
||||
.misc_reg = PLLDP_MISC,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
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.iddq_reg = PLLDP_BASE,
|
||||
.iddq_bit_idx = PLLSS_IDDQ_BIT,
|
||||
|
|
@ -1941,7 +1932,7 @@ static struct tegra_clk_pll_params pll_dp_params = {
|
|||
.mdiv_default = 1,
|
||||
.freq_table = pll_dp_freq_table,
|
||||
.set_defaults = tegra210_plldp_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
.adjust_vco = tegra210_clk_adjust_vco_min,
|
||||
|
|
@ -1973,7 +1964,6 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
|
|||
.base_reg = PLLU_BASE,
|
||||
.misc_reg = PLLU_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.iddq_reg = PLLU_MISC0,
|
||||
.iddq_bit_idx = PLLU_IDDQ_BIT,
|
||||
|
|
@ -1983,8 +1973,7 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
|
|||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllu_nmp,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllu_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -2218,6 +2207,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
|
||||
[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
|
||||
[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
|
||||
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
|
||||
};
|
||||
|
||||
static struct tegra_devclk devclks[] __initdata = {
|
||||
|
|
@ -2519,7 +2509,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
|
|||
|
||||
/* PLLU_VCO */
|
||||
val = readl(clk_base + pll_u_vco_params.base_reg);
|
||||
val &= ~BIT(24); /* disable PLLU_OVERRIDE */
|
||||
val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
|
||||
writel(val, clk_base + pll_u_vco_params.base_reg);
|
||||
|
||||
clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
|
||||
|
|
@ -2738,8 +2728,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
|
||||
{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
/* 104 */
|
||||
/* 105 */
|
||||
#define TEGRA210_CLK_D_AUDIO 106
|
||||
/* 107 ( affects abp -> ape) */
|
||||
#define TEGRA210_CLK_APB2APE 107
|
||||
/* 108 */
|
||||
/* 109 */
|
||||
/* 110 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue