mirror of https://gitee.com/openkylin/linux.git
s390/cmpxchg: use compiler builtins
The kernel build for s390 fails for gcc compilers with version 3.x, set the minimum required version of gcc to version 4.3. As the atomic builtins are available with all gcc 4.x compilers, use the __sync_val_compare_and_swap and __sync_bool_compare_and_swap functions to replace the complex macro and inline assembler magic in include/asm/cmpxchg.h. The compiler can just-do-it and generates better code with the builtins. While we are at it use __sync_bool_compare_and_swap for the _raw_compare_and_swap function in the spinlock code as well. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky
parent
fcbe08d66f
commit
f318a1229b
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@ -11,201 +11,29 @@
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#include <linux/types.h>
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#include <linux/bug.h>
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, void *ptr, int size)
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{
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unsigned long addr, old;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" ((x & 0xff) << shift), "d" (~(0xff << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%4\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,%4\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) addr)
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: "d" ((x & 0xffff) << shift), "d" (~(0xffff << shift)),
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"Q" (*(int *) addr) : "memory", "cc", "0");
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return old >> shift;
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case 4:
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asm volatile(
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" l %0,%3\n"
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"0: cs %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=Q" (*(int *) ptr)
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: "d" (x), "Q" (*(int *) ptr)
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: "memory", "cc");
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return old;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" lg %0,%3\n"
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"0: csg %0,%2,%3\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "Q" (*(long *) ptr)
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: "memory", "cc");
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return old;
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#endif /* CONFIG_64BIT */
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr, x) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__xchg((unsigned long)(x), (void *)(ptr), sizeof(*(ptr)));\
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__ret; \
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __o = (o); \
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__typeof__(*(ptr)) __n = (n); \
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(__typeof__(*(ptr))) __sync_val_compare_and_swap((ptr),__o,__n);\
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})
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define cmpxchg64 cmpxchg
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#define cmpxchg_local cmpxchg
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#define cmpxchg64_local cmpxchg
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#define xchg(ptr, x) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old; \
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do { \
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__old = *__ptr; \
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} while (!__sync_bool_compare_and_swap(__ptr, __old, x)); \
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__old; \
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})
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#define __HAVE_ARCH_CMPXCHG
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long __cmpxchg(void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long addr, prev, tmp;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "+Q" (*(int *) addr)
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: "d" ((old & 0xff) << shift),
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"d" ((new & 0xff) << shift),
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"d" (~(0xff << shift))
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: "memory", "cc");
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,%2\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%3\n"
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" or %1,%4\n"
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" cs %0,%1,%2\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp), "+Q" (*(int *) addr)
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: "d" ((old & 0xffff) << shift),
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"d" ((new & 0xffff) << shift),
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"d" (~(0xffff << shift))
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: "memory", "cc");
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return prev >> shift;
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case 4:
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asm volatile(
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" cs %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(int *) ptr)
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: "0" (old), "d" (new), "Q" (*(int *) ptr)
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: "memory", "cc");
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return prev;
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#ifdef CONFIG_64BIT
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case 8:
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asm volatile(
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" csg %0,%3,%1\n"
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: "=&d" (prev), "=Q" (*(long *) ptr)
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: "0" (old), "d" (new), "Q" (*(long *) ptr)
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: "memory", "cc");
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return prev;
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#endif /* CONFIG_64BIT */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg((ptr), (unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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__ret; \
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})
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#ifdef CONFIG_64BIT
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#define cmpxchg64(ptr, o, n) \
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({ \
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cmpxchg((ptr), (o), (n)); \
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})
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#else /* CONFIG_64BIT */
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static inline unsigned long long __cmpxchg64(void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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register_pair rp_old = {.pair = old};
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register_pair rp_new = {.pair = new};
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unsigned long long *ullptr = ptr;
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asm volatile(
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" cds %0,%2,%1"
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: "+d" (rp_old), "+Q" (*ullptr)
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: "d" (rp_new)
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: "memory", "cc");
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return rp_old.pair;
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}
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#define cmpxchg64(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg64((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)); \
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__ret; \
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})
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#endif /* CONFIG_64BIT */
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#define __cmpxchg_double_op(p1, p2, o1, o2, n1, n2, insn) \
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({ \
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register __typeof__(*(p1)) __old1 asm("2") = (o1); \
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@ -265,40 +93,4 @@ extern void __cmpxchg_double_called_with_bad_pointer(void);
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#define system_has_cmpxchg_double() 1
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef CONFIG_64BIT
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case 8:
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#endif
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return __cmpxchg(ptr, old, new, size);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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#define cmpxchg64_local(ptr, o, n) cmpxchg64((ptr), (o), (n))
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#endif /* __ASM_CMPXCHG_H */
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@ -18,14 +18,7 @@ extern int spin_retry;
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static inline int
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_raw_compare_and_swap(unsigned int *lock, unsigned int old, unsigned int new)
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{
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unsigned int old_expected = old;
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asm volatile(
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" cs %0,%3,%1"
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: "=d" (old), "=Q" (*lock)
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: "0" (old), "d" (new), "Q" (*lock)
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: "cc", "memory" );
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return old == old_expected;
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return __sync_bool_compare_and_swap(lock, old, new);
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}
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/*
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@ -17,8 +17,8 @@
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* Make sure that the compiler is new enough. We want a compiler that
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* is known to work with the "Q" assembler constraint.
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*/
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#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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#error Your compiler is too old; please use version 3.3.3 or newer
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#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 3)
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#error Your compiler is too old; please use version 4.3 or newer
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#endif
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int main(void)
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