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Merge branch 'qcom-emac-misc' 

Timur Tabi says:

====================
net: qcom/emac:

Although not related, these patches affect the same files, so they should
be applied in order.

The first patch cleans up logging of when the the phy driver is attached.

The second patch always configures the SGMII to use autonegotiation mode.

The third patch removes a redundant call to emac_mac_start().

The fourth patch removes some extraneous non-functioning WOL code.

The fifth patch adds an error handler for the SGMII block.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2017-01-29 19:07:03 -05:00
parent 5b8784aaf2 fd0e97b806
commit f33f4ac3d3
7 changed files with 166 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/net/ethernet/qualcomm/emac/emac-mac.c
View File

@ -103,14 +103,6 @@
#define RXEN 0x00000002
#define TXEN 0x00000001
/* EMAC_WOL_CTRL0 */
#define LK_CHG_PME 0x20
#define LK_CHG_EN 0x10
#define MG_FRAME_PME 0x8
#define MG_FRAME_EN 0x4
#define WK_FRAME_EN 0x1
/* EMAC_DESC_CTRL_3 */
#define RFD_RING_SIZE_BMSK 0xfff
@ -556,7 +548,7 @@ void emac_mac_reset(struct emac_adapter *adpt)
emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, INT_RD_CLR_EN);
}
void emac_mac_start(struct emac_adapter *adpt)
static void emac_mac_start(struct emac_adapter *adpt)
{
struct phy_device *phydev = adpt->phydev;
u32 mac, csr1;
@ -619,8 +611,6 @@ void emac_mac_start(struct emac_adapter *adpt)
emac_reg_update32(adpt->base + EMAC_ATHR_HEADER_CTRL,
(HEADER_ENABLE | HEADER_CNT_EN), 0);
emac_reg_update32(adpt->csr + EMAC_EMAC_WRAPPER_CSR2, 0, WOL_EN);
}
void emac_mac_stop(struct emac_adapter *adpt)
@ -961,12 +951,16 @@ static void emac_mac_rx_descs_refill(struct emac_adapter *adpt,
static void emac_adjust_link(struct net_device *netdev)
{
struct emac_adapter *adpt = netdev_priv(netdev);
struct emac_sgmii *sgmii = &adpt->phy;
struct phy_device *phydev = netdev->phydev;
if (phydev->link)
if (phydev->link) {
emac_mac_start(adpt);
else
sgmii->link_up(adpt);
} else {
sgmii->link_down(adpt);
emac_mac_stop(adpt);
}
phy_print_status(phydev);
}
@ -981,6 +975,7 @@ int emac_mac_up(struct emac_adapter *adpt)
emac_mac_config(adpt);
emac_mac_rx_descs_refill(adpt, &adpt->rx_q);
adpt->phydev->irq = PHY_IGNORE_INTERRUPT;
ret = phy_connect_direct(netdev, adpt->phydev, emac_adjust_link,
PHY_INTERFACE_MODE_SGMII);
if (ret) {
@ -988,11 +983,12 @@ int emac_mac_up(struct emac_adapter *adpt)
return ret;
}
phy_attached_print(adpt->phydev, NULL);
/* enable mac irq */
writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS);
writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK);
adpt->phydev->irq = PHY_IGNORE_INTERRUPT;
phy_start(adpt->phydev);
napi_enable(&adpt->rx_q.napi);

1
drivers/net/ethernet/qualcomm/emac/emac-mac.h
View File

@ -230,7 +230,6 @@ struct emac_adapter;
int emac_mac_up(struct emac_adapter *adpt);
void emac_mac_down(struct emac_adapter *adpt);
void emac_mac_reset(struct emac_adapter *adpt);
void emac_mac_start(struct emac_adapter *adpt);
void emac_mac_stop(struct emac_adapter *adpt);
void emac_mac_mode_config(struct emac_adapter *adpt);
void emac_mac_rx_process(struct emac_adapter *adpt, struct emac_rx_queue *rx_q,

3
drivers/net/ethernet/qualcomm/emac/emac-phy.c
View File

@ -226,8 +226,5 @@ int emac_phy_config(struct platform_device *pdev, struct emac_adapter *adpt)
return -ENODEV;
}
if (adpt->phydev->drv)
phy_attached_print(adpt->phydev, NULL);
return 0;
}

175
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
View File

@ -25,7 +25,9 @@
#define EMAC_SGMII_PHY_SPEED_CFG1 0x0074
#define EMAC_SGMII_PHY_IRQ_CMD 0x00ac
#define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0
#define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4
#define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8
#define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4
#define FORCE_AN_TX_CFG BIT(5)
#define FORCE_AN_RX_CFG BIT(4)
@ -36,6 +38,8 @@
#define SPDMODE_100 BIT(0)
#define SPDMODE_10 0
#define CDR_ALIGN_DET BIT(6)
#define IRQ_GLOBAL_CLEAR BIT(0)
#define DECODE_CODE_ERR BIT(7)
@ -44,47 +48,23 @@
#define SGMII_PHY_IRQ_CLR_WAIT_TIME 10
#define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR)
#define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR)
#define SERDES_START_WAIT_TIMES 100
static int emac_sgmii_link_init(struct emac_adapter *adpt)
/* Initialize the SGMII link between the internal and external PHYs. */
static void emac_sgmii_link_init(struct emac_adapter *adpt)
{
struct phy_device *phydev = adpt->phydev;
struct emac_sgmii *phy = &adpt->phy;
u32 val;
/* Always use autonegotiation. It works no matter how the external
* PHY is configured.
*/
val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
if (phydev->autoneg == AUTONEG_ENABLE) {
val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
val |= AN_ENABLE;
writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
} else {
u32 speed_cfg;
switch (phydev->speed) {
case SPEED_10:
speed_cfg = SPDMODE_10;
break;
case SPEED_100:
speed_cfg = SPDMODE_100;
break;
case SPEED_1000:
speed_cfg = SPDMODE_1000;
break;
default:
return -EINVAL;
}
if (phydev->duplex == DUPLEX_FULL)
speed_cfg |= DUPLEX_MODE;
val &= ~AN_ENABLE;
writel(speed_cfg, phy->base + EMAC_SGMII_PHY_SPEED_CFG1);
writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
}
return 0;
val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
val |= AN_ENABLE;
writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
}
static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
@ -121,6 +101,51 @@ static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits)
return 0;
}
/* The number of decode errors that triggers a reset */
#define DECODE_ERROR_LIMIT 2
static irqreturn_t emac_sgmii_interrupt(int irq, void *data)
{
struct emac_adapter *adpt = data;
struct emac_sgmii *phy = &adpt->phy;
u32 status;
status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS);
status &= SGMII_ISR_MASK;
if (!status)
return IRQ_HANDLED;
/* If we get a decoding error and CDR is not locked, then try
* resetting the internal PHY. The internal PHY uses an embedded
* clock with Clock and Data Recovery (CDR) to recover the
* clock and data.
*/
if (status & SGMII_PHY_INTERRUPT_ERR) {
int count;
/* The SGMII is capable of recovering from some decode
* errors automatically. However, if we get multiple
* decode errors in a row, then assume that something
* is wrong and reset the interface.
*/
count = atomic_inc_return(&phy->decode_error_count);
if (count == DECODE_ERROR_LIMIT) {
schedule_work(&adpt->work_thread);
atomic_set(&phy->decode_error_count, 0);
}
} else {
/* We only care about consecutive decode errors. */
atomic_set(&phy->decode_error_count, 0);
}
if (emac_sgmii_irq_clear(adpt, status)) {
netdev_warn(adpt->netdev, "failed to clear SGMII interrupt\n");
schedule_work(&adpt->work_thread);
}
return IRQ_HANDLED;
}
static void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
{
struct emac_sgmii *phy = &adpt->phy;
@ -145,12 +170,7 @@ void emac_sgmii_reset(struct emac_adapter *adpt)
int ret;
emac_sgmii_reset_prepare(adpt);
ret = emac_sgmii_link_init(adpt);
if (ret) {
netdev_err(adpt->netdev, "unsupported link speed\n");
return;
}
emac_sgmii_link_init(adpt);
ret = adpt->phy.initialize(adpt);
if (ret)
@ -159,6 +179,68 @@ void emac_sgmii_reset(struct emac_adapter *adpt)
ret);
}
static int emac_sgmii_open(struct emac_adapter *adpt)
{
struct emac_sgmii *sgmii = &adpt->phy;
int ret;
if (sgmii->irq) {
/* Make sure interrupts are cleared and disabled first */
ret = emac_sgmii_irq_clear(adpt, 0xff);
if (ret)
return ret;
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0,
"emac-sgmii", adpt);
if (ret) {
netdev_err(adpt->netdev,
"could not register handler for internal PHY\n");
return ret;
}
}
return 0;
}
static int emac_sgmii_close(struct emac_adapter *adpt)
{
struct emac_sgmii *sgmii = &adpt->phy;
/* Make sure interrupts are disabled */
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
free_irq(sgmii->irq, adpt);
return 0;
}
/* The error interrupts are only valid after the link is up */
static int emac_sgmii_link_up(struct emac_adapter *adpt)
{
struct emac_sgmii *sgmii = &adpt->phy;
int ret;
/* Clear and enable interrupts */
ret = emac_sgmii_irq_clear(adpt, 0xff);
if (ret)
return ret;
writel(SGMII_ISR_MASK, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
return 0;
}
static int emac_sgmii_link_down(struct emac_adapter *adpt)
{
struct emac_sgmii *sgmii = &adpt->phy;
/* Disable interrupts */
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
synchronize_irq(sgmii->irq);
return 0;
}
static int emac_sgmii_acpi_match(struct device *dev, void *data)
{
#ifdef CONFIG_ACPI
@ -169,7 +251,7 @@ static int emac_sgmii_acpi_match(struct device *dev, void *data)
{}
};
const struct acpi_device_id *id = acpi_match_device(match_table, dev);
emac_sgmii_initialize *initialize = data;
emac_sgmii_function *initialize = data;
if (id) {
acpi_handle handle = ACPI_HANDLE(dev);
@ -256,9 +338,14 @@ int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
goto error_put_device;
}
phy->initialize = (emac_sgmii_initialize)match->data;
phy->initialize = (emac_sgmii_function)match->data;
}
phy->open = emac_sgmii_open;
phy->close = emac_sgmii_close;
phy->link_up = emac_sgmii_link_up;
phy->link_down = emac_sgmii_link_down;
/* Base address is the first address */
res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0);
if (!res) {
@ -286,7 +373,11 @@ int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
if (ret)
goto error;
emac_sgmii_irq_clear(adpt, SGMII_PHY_INTERRUPT_ERR);
emac_sgmii_link_init(adpt);
ret = platform_get_irq(sgmii_pdev, 0);
if (ret > 0)
phy->irq = ret;
/* We've remapped the addresses, so we don't need the device any
* more. of_find_device_by_node() says we should release it.

16
drivers/net/ethernet/qualcomm/emac/emac-sgmii.h
View File

@ -16,17 +16,29 @@
struct emac_adapter;
struct platform_device;
typedef int (*emac_sgmii_initialize)(struct emac_adapter *adpt);
typedef int (*emac_sgmii_function)(struct emac_adapter *adpt);
/** emac_sgmii - internal emac phy
* @base base address
* @digital per-lane digital block
* @irq the interrupt number
* @decode_error_count reference count of consecutive decode errors
* @initialize initialization function
* @open called when the driver is opened
* @close called when the driver is closed
* @link_up called when the link comes up
* @link_down called when the link comes down
*/
struct emac_sgmii {
void __iomem *base;
void __iomem *digital;
emac_sgmii_initialize initialize;
unsigned int irq;
atomic_t decode_error_count;
emac_sgmii_function initialize;
emac_sgmii_function open;
emac_sgmii_function close;
emac_sgmii_function link_up;
emac_sgmii_function link_down;
};
int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt);

10
drivers/net/ethernet/qualcomm/emac/emac.c
View File

@ -280,7 +280,13 @@ static int emac_open(struct net_device *netdev)
return ret;
}
emac_mac_start(adpt);
ret = adpt->phy.open(adpt);
if (ret) {
emac_mac_down(adpt);
emac_mac_rx_tx_rings_free_all(adpt);
free_irq(irq->irq, irq);
return ret;
}
return 0;
}
@ -292,6 +298,7 @@ static int emac_close(struct net_device *netdev)
mutex_lock(&adpt->reset_lock);
adpt->phy.close(adpt);
emac_mac_down(adpt);
emac_mac_rx_tx_rings_free_all(adpt);
@ -647,6 +654,7 @@ static int emac_probe(struct platform_device *pdev)
adpt->msg_enable = EMAC_MSG_DEFAULT;
phy = &adpt->phy;
atomic_set(&phy->decode_error_count, 0);
mutex_init(&adpt->reset_lock);
spin_lock_init(&adpt->stats.lock);

4
drivers/net/ethernet/qualcomm/emac/emac.h
View File

@ -167,10 +167,6 @@ enum emac_clk_id {
#define EMAC_MAX_SETUP_LNK_CYCLE 100
/* Wake On Lan */
#define EMAC_WOL_PHY 0x00000001 /* PHY Status Change */
#define EMAC_WOL_MAGIC 0x00000002 /* Magic Packet */
struct emac_stats {
/* rx */
u64 rx_ok; /* good packets */