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arm64: dts: msm8996: thermal: Initialise via DT and add second controller 

We also split up the regmap address space into two, for the TM and SROT
registers. This was required to deal with different address offsets for the
TM and SROT registers across different SoC families.

8996 has two TSENS IP blocks, initialise the second one too.

Since tsens-common.c/init_common() currently only registers one address
space, the order is important (TM before SROT). This is OK since the code
doesn't really use the SROT functionality yet.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Amit Kucheria 2018-07-18 12:13:10 +05:30 committed by Andy Gross
parent 7a0d5009db
commit f35c11b03b
1 changed files with 16 additions and 6 deletions
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22
arch/arm64/boot/dts/qcom/msm8996.dtsi
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@ -377,6 +377,22 @@ tcsr_mutex_regs: syscon@740000 {
reg = <0x740000 0x20000>;
};
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4a9000 0x1000>, /* TM */
<0x4a8000 0x1000>; /* SROT */
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4ad000 0x1000>, /* TM */
<0x4ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x7a0000 0x18000>;
@ -459,12 +475,6 @@ blsp2_i2c0: i2c@75b5000 {
status = "disabled";
};
tsens0: thermal-sensor@4a8000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4a8000 0x2000>;
#thermal-sensor-cells = <1>;
};
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;