mirror of https://gitee.com/openkylin/linux.git
[POWERPC] pasemi: Implement NMI support
Some PWRficient-based boards have a NMI button that's wired up to a GPIO as interrupt source. By configuring the openpic accordingly, these get delivered as a machine check with high priority, instead of as an external interrupt. The device tree contains a property "nmi-source" in the openpic node for these systems, and it's the (hwirq) source for the input. Also, for these interrupts, the IACK is read from another register than the regular (MCACK instead), but they are EOI'd as usual. So implement said function for the mpic driver. Finally, move a couple of external function defines to include/ instead of local under sysdev. Being able to mask/unmask and eoi directly saves us from setting up a dummy irq handler that will never be called. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
parent
c2a7dcad9f
commit
f365355e65
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@ -61,6 +61,7 @@ struct mce_regs {
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static struct mce_regs mce_regs[MAX_MCE_REGS];
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static int num_mce_regs;
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static int nmi_virq = NO_IRQ;
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static void pas_restart(char *cmd)
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@ -189,6 +190,8 @@ static __init void pas_init_IRQ(void)
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unsigned long openpic_addr;
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const unsigned int *opprop;
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int naddr, opplen;
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int mpic_flags;
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const unsigned int *nmiprop;
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struct mpic *mpic;
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mpic_node = NULL;
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@ -221,13 +224,26 @@ static __init void pas_init_IRQ(void)
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openpic_addr = of_read_number(opprop, naddr);
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printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
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mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS;
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nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
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if (nmiprop)
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mpic_flags |= MPIC_ENABLE_MCK;
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mpic = mpic_alloc(mpic_node, openpic_addr,
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MPIC_PRIMARY|MPIC_LARGE_VECTORS,
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0, 0, "PASEMI-OPIC");
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mpic_flags, 0, 0, "PASEMI-OPIC");
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BUG_ON(!mpic);
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mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
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mpic_init(mpic);
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/* The NMI/MCK source needs to be prio 15 */
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if (nmiprop) {
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nmi_virq = irq_create_mapping(NULL, *nmiprop);
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mpic_irq_set_priority(nmi_virq, 15);
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set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
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mpic_unmask_irq(nmi_virq);
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}
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of_node_put(mpic_node);
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of_node_put(root);
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}
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@ -247,6 +263,14 @@ static int pas_machine_check_handler(struct pt_regs *regs)
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srr0 = regs->nip;
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srr1 = regs->msr;
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if (mpic_get_mcirq() == nmi_virq) {
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printk(KERN_ERR "NMI delivered\n");
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debugger(regs);
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mpic_end_irq(nmi_virq);
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goto out;
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}
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dsisr = mfspr(SPRN_DSISR);
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printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
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printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
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@ -310,7 +334,7 @@ static int pas_machine_check_handler(struct pt_regs *regs)
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}
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}
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out:
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/* SRR1[62] is from MSR[62] if recoverable, so pass that back */
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return !!(srr1 & 0x2);
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}
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@ -83,6 +83,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
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MPIC_CPU_WHOAMI,
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MPIC_CPU_INTACK,
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MPIC_CPU_EOI,
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MPIC_CPU_MCACK,
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MPIC_IRQ_BASE,
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MPIC_IRQ_STRIDE,
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@ -121,6 +122,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
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TSI108_CPU_WHOAMI,
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TSI108_CPU_INTACK,
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TSI108_CPU_EOI,
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TSI108_CPU_MCACK,
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TSI108_IRQ_BASE,
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TSI108_IRQ_STRIDE,
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@ -1126,6 +1128,11 @@ struct mpic * __init mpic_alloc(struct device_node *node,
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mb();
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}
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if (flags & MPIC_ENABLE_MCK)
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mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
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mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
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| MPIC_GREG_GCONF_MCK);
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/* Read feature register, calculate num CPUs and, for non-ISU
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* MPICs, num sources as well. On ISU MPICs, sources are counted
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* as ISUs are added
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@ -1438,13 +1445,13 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
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mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
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}
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unsigned int mpic_get_one_irq(struct mpic *mpic)
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static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
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{
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u32 src;
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src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
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src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
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#ifdef DEBUG_LOW
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DBG("%s: get_one_irq(): %d\n", mpic->name, src);
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DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
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#endif
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if (unlikely(src == mpic->spurious_vec)) {
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if (mpic->flags & MPIC_SPV_EOI)
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@ -1462,6 +1469,11 @@ unsigned int mpic_get_one_irq(struct mpic *mpic)
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return irq_linear_revmap(mpic->irqhost, src);
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}
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unsigned int mpic_get_one_irq(struct mpic *mpic)
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{
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return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
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}
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unsigned int mpic_get_irq(void)
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{
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struct mpic *mpic = mpic_primary;
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@ -1471,6 +1483,14 @@ unsigned int mpic_get_irq(void)
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return mpic_get_one_irq(mpic);
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}
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unsigned int mpic_get_mcirq(void)
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{
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struct mpic *mpic = mpic_primary;
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BUG_ON(mpic == NULL);
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return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
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}
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#ifdef CONFIG_SMP
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void mpic_request_ipis(void)
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@ -38,9 +38,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
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extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
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extern void mpic_set_vector(unsigned int virq, unsigned int vector);
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extern void mpic_end_irq(unsigned int irq);
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extern void mpic_mask_irq(unsigned int irq);
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extern void mpic_unmask_irq(unsigned int irq);
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extern void mpic_set_affinity(unsigned int irq, cpumask_t cpumask);
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#endif /* _POWERPC_SYSDEV_MPIC_H */
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@ -23,6 +23,7 @@
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#define MPIC_GREG_GCONF_RESET 0x80000000
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#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
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#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
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#define MPIC_GREG_GCONF_MCK 0x08000000
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#define MPIC_GREG_GLOBAL_CONF_1 0x00030
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#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
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#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
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@ -78,6 +79,7 @@
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#define MPIC_CPU_WHOAMI_MASK 0x0000001f
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#define MPIC_CPU_INTACK 0x000a0
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#define MPIC_CPU_EOI 0x000b0
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#define MPIC_CPU_MCACK 0x000c0
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/*
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* Per-source registers
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@ -141,6 +143,7 @@
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#define TSI108_CPU_WHOAMI 0xffffffff
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#define TSI108_CPU_INTACK 0x00004
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#define TSI108_CPU_EOI 0x00008
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#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
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/*
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* Per-source registers
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@ -183,6 +186,7 @@ enum {
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MPIC_IDX_CPU_WHOAMI,
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MPIC_IDX_CPU_INTACK,
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MPIC_IDX_CPU_EOI,
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MPIC_IDX_CPU_MCACK,
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MPIC_IDX_IRQ_BASE,
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MPIC_IDX_IRQ_STRIDE,
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@ -344,6 +348,8 @@ struct mpic
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#define MPIC_USES_DCR 0x00000080
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/* MPIC has 11-bit vector fields (or larger) */
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#define MPIC_LARGE_VECTORS 0x00000100
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/* Enable delivery of prio 15 interrupts as MCK instead of EE */
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#define MPIC_ENABLE_MCK 0x00000200
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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@ -447,10 +453,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
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/* Send a message (IPI) to a given target (cpu number or MSG_*) */
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void smp_mpic_message_pass(int target, int msg);
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/* Unmask a specific virq */
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extern void mpic_unmask_irq(unsigned int irq);
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/* Mask a specific virq */
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extern void mpic_mask_irq(unsigned int irq);
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/* EOI a specific virq */
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extern void mpic_end_irq(unsigned int irq);
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/* Fetch interrupt from a given mpic */
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extern unsigned int mpic_get_one_irq(struct mpic *mpic);
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/* This one gets to the primary mpic */
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/* This one gets from the primary mpic */
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extern unsigned int mpic_get_irq(void);
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/* Fetch Machine Check interrupt from primary mpic */
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extern unsigned int mpic_get_mcirq(void);
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/* Set the EPIC clock ratio */
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void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
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