mirror of https://gitee.com/openkylin/linux.git
powerpc: Use correct sequence for putting CPU into nap mode
We weren't using the recommended sequence for putting the CPU into nap mode. When I changed the idle loop, for some reason 7447A cpus started hanging when we put them into nap mode. Changing to the recommended sequence fixes that. The complexity here is that the recommended sequence is a loop that keeps putting the cpu back into nap mode. Clearly we need some way to break out of the loop when an interrupt (external interrupt, decrementer, performance monitor) occurs. Here we use a bit in the thread_info struct to indicate that we need this, and the exception entry code notices this and arranges for the exception to return to the value in the link register, thus breaking out of the loop. We use a new `local_flags' field in the thread_info which we can alter without needing to use an atomic update sequence. The PPC970 has the same recommended sequence, so we do the same thing there too. This also fixes a bug in the kernel stack overflow handling code on 32-bit, since it was causing a value that we needed in a register to get trashed. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras
parent
183b73ae7c
commit
f39224a8c1
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@ -366,6 +366,7 @@ config PPC_PMAC64
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select U3_DART
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select MPIC_BROKEN_U3
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select GENERIC_TBSYNC
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select PPC_970_NAP
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default y
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config PPC_PREP
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@ -383,6 +384,7 @@ config PPC_MAPLE
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select MPIC_BROKEN_U3
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select GENERIC_TBSYNC
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select PPC_UDBG_16550
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select PPC_970_NAP
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default n
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help
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This option enables support for the Maple 970FX Evaluation Board.
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@ -457,6 +459,10 @@ config PPC_MPC106
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bool
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default n
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config PPC_970_NAP
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bool
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default n
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source "drivers/cpufreq/Kconfig"
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config CPU_FREQ_PMAC
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@ -20,7 +20,7 @@ obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
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firmware.o sysfs.o
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obj-$(CONFIG_PPC64) += vdso64/
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obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
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obj-$(CONFIG_POWER4) += idle_power4.o
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obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
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obj-$(CONFIG_PPC_OF) += of_device.o prom_parse.o
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procfs-$(CONFIG_PPC64) := proc_ppc64.o
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obj-$(CONFIG_PROC_FS) += $(procfs-y)
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@ -91,6 +91,7 @@ int main(void)
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#endif /* CONFIG_PPC64 */
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DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
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DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
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DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
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DEFINE(TI_TASK, offsetof(struct thread_info, task));
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#ifdef CONFIG_PPC32
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@ -128,37 +128,36 @@ transfer_to_handler:
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stw r12,4(r11)
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#endif
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b 3f
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2: /* if from kernel, check interrupted DOZE/NAP mode and
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* check for stack overflow
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*/
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lwz r9,THREAD_INFO-THREAD(r12)
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cmplw r1,r9 /* if r1 <= current->thread_info */
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ble- stack_ovf /* then the kernel stack overflowed */
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5:
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#ifdef CONFIG_6xx
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mfspr r11,SPRN_HID0
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mtcr r11
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BEGIN_FTR_SECTION
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bt- 8,4f /* Check DOZE */
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
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BEGIN_FTR_SECTION
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bt- 9,4f /* Check NAP */
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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tophys(r9,r9) /* check local flags */
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lwz r12,TI_LOCAL_FLAGS(r9)
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mtcrf 0x01,r12
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bt- 31-TLF_NAPPING,4f
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#endif /* CONFIG_6xx */
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.globl transfer_to_handler_cont
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transfer_to_handler_cont:
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lwz r11,THREAD_INFO-THREAD(r12)
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cmplw r1,r11 /* if r1 <= current->thread_info */
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ble- stack_ovf /* then the kernel stack overflowed */
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3:
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mflr r9
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lwz r11,0(r9) /* virtual address of handler */
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lwz r9,4(r9) /* where to go when done */
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FIX_SRR1(r10,r12)
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r10
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mtlr r9
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SYNC
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RFI /* jump to handler, enable MMU */
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#ifdef CONFIG_6xx
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4: b power_save_6xx_restore
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#ifdef CONFIG_6xx
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4: rlwinm r12,r12,0,~_TLF_NAPPING
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stw r12,TI_LOCAL_FLAGS(r9)
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b power_save_6xx_restore
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#endif
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/*
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@ -167,10 +166,10 @@ transfer_to_handler_cont:
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*/
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stack_ovf:
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/* sometimes we use a statically-allocated stack, which is OK. */
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lis r11,_end@h
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ori r11,r11,_end@l
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cmplw r1,r11
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ble 3b /* r1 <= &_end is OK */
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lis r12,_end@h
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ori r12,r12,_end@l
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cmplw r1,r12
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ble 5b /* r1 <= &_end is OK */
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SAVE_NVGPRS(r11)
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addi r3,r1,STACK_FRAME_OVERHEAD
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lis r1,init_thread_union@ha
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@ -376,17 +376,53 @@ label##_common: \
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bl hdlr; \
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b .ret_from_except
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/*
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* Like STD_EXCEPTION_COMMON, but for exceptions that can occur
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* in the idle task and therefore need the special idle handling.
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*/
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#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
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.align 7; \
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.globl label##_common; \
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label##_common: \
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EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
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FINISH_NAP; \
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DISABLE_INTS; \
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bl .save_nvgprs; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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bl hdlr; \
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b .ret_from_except
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#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
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.align 7; \
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.globl label##_common; \
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label##_common: \
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EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
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FINISH_NAP; \
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DISABLE_INTS; \
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bl .ppc64_runlatch_on; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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bl hdlr; \
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b .ret_from_except_lite
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/*
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* When the idle code in power4_idle puts the CPU into NAP mode,
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* it has to do so in a loop, and relies on the external interrupt
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* and decrementer interrupt entry code to get it out of the loop.
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* It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
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* to signal that it is in the loop and needs help to get out.
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*/
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#ifdef CONFIG_PPC_970_NAP
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#define FINISH_NAP \
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BEGIN_FTR_SECTION \
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clrrdi r11,r1,THREAD_SHIFT; \
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ld r9,TI_LOCAL_FLAGS(r11); \
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andi. r10,r9,_TLF_NAPPING; \
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bnel power4_fixup_nap; \
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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#else
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#define FINISH_NAP
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#endif
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/*
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* Start of pSeries system interrupt routines
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*/
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@ -772,6 +808,7 @@ hardware_interrupt_iSeries_masked:
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.globl machine_check_common
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machine_check_common:
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EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
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FINISH_NAP
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DISABLE_INTS
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bl .save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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@ -783,7 +820,7 @@ machine_check_common:
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STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
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STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
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STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
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STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
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STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
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STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
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#ifdef CONFIG_ALTIVEC
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STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
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@ -1034,6 +1071,7 @@ unrecov_slb:
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.globl hardware_interrupt_entry
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hardware_interrupt_common:
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EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
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FINISH_NAP
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hardware_interrupt_entry:
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DISABLE_INTS
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bl .ppc64_runlatch_on
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@ -1041,6 +1079,15 @@ hardware_interrupt_entry:
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bl .do_IRQ
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b .ret_from_except_lite
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#ifdef CONFIG_PPC_970_NAP
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power4_fixup_nap:
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andc r9,r9,r10
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std r9,TI_LOCAL_FLAGS(r11)
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ld r10,_LINK(r1) /* make idle task do the */
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std r10,_NIP(r1) /* equivalent of a blr */
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blr
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#endif
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.align 7
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.globl alignment_common
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alignment_common:
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@ -22,8 +22,6 @@
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#undef DEBUG
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.text
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/*
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@ -109,12 +107,6 @@ BEGIN_FTR_SECTION
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dcbf 0,r4
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dcbf 0,r4
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END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
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#ifdef DEBUG
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lis r6,nap_enter_count@ha
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lwz r4,nap_enter_count@l(r6)
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addi r4,r4,1
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stw r4,nap_enter_count@l(r6)
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#endif
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2:
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BEGIN_FTR_SECTION
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/* Go to low speed mode on some 750FX */
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@ -144,48 +136,42 @@ BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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rlwinm r9,r1,0,0,31-THREAD_SHIFT /* current thread_info */
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lwz r8,TI_LOCAL_FLAGS(r9) /* set napping bit */
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ori r8,r8,_TLF_NAPPING /* so when we take an exception */
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stw r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */
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mfmsr r7
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ori r7,r7,MSR_EE
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oris r7,r7,MSR_POW@h
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sync
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isync
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1: sync
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mtmsr r7
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isync
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sync
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blr
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b 1b
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/*
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* Return from NAP/DOZE mode, restore some CPU specific registers,
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* we are called with DR/IR still off and r2 containing physical
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* address of current.
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* address of current. R11 points to the exception frame (physical
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* address). We have to preserve r10.
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*/
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_GLOBAL(power_save_6xx_restore)
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mfspr r11,SPRN_HID0
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rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */
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cror 4*cr1+eq,4*cr0+eq,4*cr0+eq
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BEGIN_FTR_SECTION
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rlwinm r11,r11,0,9,7 /* Clear DOZE */
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
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mtspr SPRN_HID0, r11
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lwz r9,_LINK(r11) /* interrupted in ppc6xx_idle: */
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stw r9,_NIP(r11) /* make it do a blr */
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#ifdef DEBUG
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beq cr1,1f
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lis r11,(nap_return_count-KERNELBASE)@ha
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lwz r9,nap_return_count@l(r11)
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addi r9,r9,1
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stw r9,nap_return_count@l(r11)
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1:
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#endif
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rlwinm r9,r1,0,0,18
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tophys(r9,r9)
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lwz r11,TI_CPU(r9)
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#ifdef CONFIG_SMP
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mfspr r12,SPRN_SPRG3
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lwz r11,TI_CPU(r12) /* get cpu number * 4 */
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slwi r11,r11,2
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#else
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li r11,0
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#endif
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/* Todo make sure all these are in the same page
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* and load r22 (@ha part + CPU offset) only once
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* and load r11 (@ha part + CPU offset) only once
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*/
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BEGIN_FTR_SECTION
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beq cr1,1f
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mfspr r9,SPRN_HID0
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andis. r9,r9,HID0_NAP@h
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beq 1f
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addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha
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lwz r9,nap_save_msscr0@l(r9)
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mtspr SPRN_MSSCR0, r9
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@ -210,10 +196,3 @@ _GLOBAL(nap_save_hid1)
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_GLOBAL(powersave_lowspeed)
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.long 0
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#ifdef DEBUG
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_GLOBAL(nap_enter_count)
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.space 4
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_GLOBAL(nap_return_count)
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.space 4
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#endif
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@ -35,12 +35,16 @@ BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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clrrdi r9,r1,THREAD_SHIFT /* current thread_info */
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ld r8,TI_LOCAL_FLAGS(r9) /* set napping bit */
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ori r8,r8,_TLF_NAPPING /* so when we take an exception */
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std r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */
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mfmsr r7
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ori r7,r7,MSR_EE
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oris r7,r7,MSR_POW@h
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sync
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1: sync
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isync
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mtmsrd r7
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isync
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sync
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blr
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b 1b
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@ -37,6 +37,8 @@ struct thread_info {
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int preempt_count; /* 0 => preemptable,
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<0 => BUG */
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struct restart_block restart_block;
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unsigned long local_flags; /* private flags for thread */
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/* low level flags - has atomic operations done on it */
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unsigned long flags ____cacheline_aligned_in_smp;
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};
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@ -143,6 +145,12 @@ static inline struct thread_info *current_thread_info(void)
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_TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK)
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#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
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/* Bits in local_flags */
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/* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
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#define TLF_NAPPING 0 /* idle thread enabled NAP mode */
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#define _TLF_NAPPING (1 << TLF_NAPPING)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_THREAD_INFO_H */
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