mirror of https://gitee.com/openkylin/linux.git
ARM: lpc32xx: devicetree updates for v5.2
Here are the changes for ARM NXP LPC32xx devicetree files: * disabled I2S and MAC controllers by default, * set default #address-cells = <1> / #size-cells = <0> for SPI slaves, * fix notation of hexadecimal values, * switched lpc32xx.dtsi to SPDX license identifier. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAly7f1YACgkQqj3i2jwl OWUbOg//Smcs+TqEzP7baR2RehJu7ayuvNMDUZFAH24X7VcIk0gyCm4sHlufM2yM iDWH7bA9+VUTwDibr687huDXKKillL/3DlEHkTrBGWK5fIioyR5vWN/6MDWdNYV6 CRG3ymqylssakj84KT9vZgjj5hsJ+WSHIV2J4brnO67Gws6LYvKYOCEwN+ZyFIRf c+UpJJEcTK9QBEdHt1AWRI7qt1fWCBa+5H38defuJl+nvrQcD5YQX0FMVROtB3zq coUoS72hRWFHPG1t9L3O8YV7Qxivm90UYYt2WAoxbhv3e1OEI9xDycwx0JJdb5LB ecPChg1BiQ0Y1VoqKgtudF7qcuFrxvRXPxebfQpYWwNhqkAVMniVTPmmHUXCKCQx /TE4zhecy+XHi8gogkRvvi+49LZ3J6v3ITHh4mBYeo9+zibZT9TfgehsuGp4Sctf 1Jo0PEVcGGrNrOiOqM/66vZj8tpFT1g1ybophrEz4eSoZrzfo7PECnDDVPXreY0u QtBDDF3mtE77Qg+pLkhwOV556B6KwNhXsfQVdP+1uEQfYV5rGEkTJSmcyjM7zlAo QhQY2RPsGpvKI4etERf0FJjJRMei8dHvH17IW2OgWvAppd/dnSPJg9Q06wTYiIgL beIqm+U1HIM6WdEAsBWcLYIRcXHdnJ3Uq4pqOFKTMEiHmnFNII0= =03bL -----END PGP SIGNATURE----- Merge tag 'lpc32xx-dt-for-5.2' of https://github.com/vzapolskiy/linux-lpc32xx into arm/dt ARM: lpc32xx: devicetree updates for v5.2 Here are the changes for ARM NXP LPC32xx devicetree files: * disabled I2S and MAC controllers by default, * set default #address-cells = <1> / #size-cells = <0> for SPI slaves, * fix notation of hexadecimal values, * switched lpc32xx.dtsi to SPDX license identifier. * tag 'lpc32xx-dt-for-5.2' of https://github.com/vzapolskiy/linux-lpc32xx: ARM: dts: lpc32xx: use SPDX license identifier ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes ARM: dts: lpc32xx: disable MAC controller by default ARM: dts: lpc32xx: disable I2S controllers by default ARM: dts: lpc32xx: change hexadecimal values to lower case Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
f45f5182d7
|
|
@ -201,6 +201,7 @@ isp1301: usb-transceiver@2d {
|
|||
&mac {
|
||||
phy-mode = "rmii";
|
||||
use-iram;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Here, choose exactly one from: ohci, usbd */
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ &key {
|
|||
&mac {
|
||||
phy-mode = "rmii";
|
||||
use-iram;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Here, choose exactly one from: ohci, usbd */
|
||||
|
|
@ -201,8 +202,6 @@ mtd4@604000 {
|
|||
};
|
||||
|
||||
&ssp0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
num-cs = <1>;
|
||||
cs-gpios = <&gpio 3 5 0>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -1,14 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* NXP LPC32xx SoC
|
||||
*
|
||||
* Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
|
||||
* Copyright 2012 Roland Stigge <stigge@antcom.de>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/lpc32xx-clock.h>
|
||||
|
|
@ -152,6 +147,7 @@ mac: ethernet@31060000 {
|
|||
reg = <0x31060000 0x1000>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_MAC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emc: memory-controller@31080000 {
|
||||
|
|
@ -185,6 +181,8 @@ ssp0: spi@20084000 {
|
|||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_SSP0>;
|
||||
clock-names = "apb_pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -192,6 +190,8 @@ spi1: spi@20088000 {
|
|||
compatible = "nxp,lpc3220-spi";
|
||||
reg = <0x20088000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_SPI1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -205,6 +205,8 @@ ssp1: spi@2008c000 {
|
|||
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_SSP1>;
|
||||
clock-names = "apb_pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -212,12 +214,15 @@ spi2: spi@20090000 {
|
|||
compatible = "nxp,lpc3220-spi";
|
||||
reg = <0x20090000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_SPI2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s0: i2s@20094000 {
|
||||
compatible = "nxp,lpc3220-i2s";
|
||||
reg = <0x20094000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd: sd@20098000 {
|
||||
|
|
@ -232,7 +237,8 @@ sd: sd@20098000 {
|
|||
|
||||
i2s1: i2s@2009c000 {
|
||||
compatible = "nxp,lpc3220-i2s";
|
||||
reg = <0x2009C000 0x1000>;
|
||||
reg = <0x2009c000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* UART5 first since it is the default console, ttyS0 */
|
||||
|
|
@ -275,7 +281,7 @@ uart6: serial@40098000 {
|
|||
|
||||
i2c1: i2c@400a0000 {
|
||||
compatible = "nxp,pnx-i2c";
|
||||
reg = <0x400A0000 0x100>;
|
||||
reg = <0x400a0000 0x100>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -286,7 +292,7 @@ i2c1: i2c@400a0000 {
|
|||
|
||||
i2c2: i2c@400a8000 {
|
||||
compatible = "nxp,pnx-i2c";
|
||||
reg = <0x400A8000 0x100>;
|
||||
reg = <0x400a8000 0x100>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -297,7 +303,7 @@ i2c2: i2c@400a8000 {
|
|||
|
||||
mpwm: mpwm@400e8000 {
|
||||
compatible = "nxp,lpc3220-motor-pwm";
|
||||
reg = <0x400E8000 0x78>;
|
||||
reg = <0x400e8000 0x78>;
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
|
@ -396,7 +402,7 @@ gpio: gpio@40028000 {
|
|||
|
||||
timer4: timer@4002c000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x4002C000 0x1000>;
|
||||
reg = <0x4002c000 0x1000>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER4>;
|
||||
clock-names = "timerclk";
|
||||
|
|
@ -414,7 +420,7 @@ timer5: timer@40030000 {
|
|||
|
||||
watchdog: watchdog@4003c000 {
|
||||
compatible = "nxp,pnx4008-wdt";
|
||||
reg = <0x4003C000 0x1000>;
|
||||
reg = <0x4003c000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_WDOG>;
|
||||
};
|
||||
|
||||
|
|
@ -453,7 +459,7 @@ tsc: tsc@40048000 {
|
|||
|
||||
timer1: timer@4004c000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x4004C000 0x1000>;
|
||||
reg = <0x4004c000 0x1000>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER1>;
|
||||
clock-names = "timerclk";
|
||||
|
|
@ -479,7 +485,7 @@ timer2: timer@40058000 {
|
|||
|
||||
pwm1: pwm@4005c000 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005C000 0x4>;
|
||||
reg = <0x4005c000 0x4>;
|
||||
clocks = <&clk LPC32XX_CLK_PWM1>;
|
||||
assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
|
||||
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
||||
|
|
@ -488,7 +494,7 @@ pwm1: pwm@4005c000 {
|
|||
|
||||
pwm2: pwm@4005c004 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005C004 0x4>;
|
||||
reg = <0x4005c004 0x4>;
|
||||
clocks = <&clk LPC32XX_CLK_PWM2>;
|
||||
assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
|
||||
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue