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arm64: dts: uniphier: fix input delay value for legacy mode of eMMC 

The property of the legacy mode for the eMMC PHY turned out to
be wrong.  Some eMMC devices are unstable due to the set-up/hold
timing violation.  Correct the delay value.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2018-04-12 11:31:31 +09:00
parent 60cc43fc88
commit f4e5200fc0
3 changed files with 3 additions and 3 deletions
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2
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View File

@ -414,7 +414,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;

2
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View File

@ -519,7 +519,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;

2
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View File

@ -334,7 +334,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;