mirror of https://gitee.com/openkylin/linux.git
ath9k: Add SERDES initvals for AR9462 2.1
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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babaa80ac5
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f51ecd770c
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@ -223,6 +223,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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ar9462_2p1_modes_fast_clock);
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ar9462_2p1_modes_fast_clock);
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
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ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9462_2p1_pciephy_clkreq_disable_L1);
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9462_2p1_pciephy_clkreq_disable_L1);
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} else if (AR_SREV_9462_20(ah)) {
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} else if (AR_SREV_9462_20(ah)) {
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
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@ -1771,4 +1771,11 @@ static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
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{0x0000a3a0, 0xca9228ee},
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{0x0000a3a0, 0xca9228ee},
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};
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};
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static const u32 ar9462_2p1_pciephy_clkreq_disable_L1[][2] = {
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/* Addr allmodes */
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{0x00018c00, 0x18213ede},
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{0x00018c04, 0x000801d8},
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{0x00018c08, 0x0003780c},
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};
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#endif /* INITVALS_9462_2P1_H */
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#endif /* INITVALS_9462_2P1_H */
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