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clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clock 

The clock is registered later than these two re-parentings.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Abel Vesa 2019-05-29 12:26:40 +00:00 committed by Shawn Guo
parent fa7574740c
commit f5697226f9
1 changed files with 0 additions and 8 deletions
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8
drivers/clk/imx/clk-imx6q.c
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@ -280,12 +280,6 @@ static void mmdc_ch1_disable(void __iomem *ccm_base)
clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
clk[IMX6QDL_CLK_PLL3_USB_OTG]); clk[IMX6QDL_CLK_PLL3_USB_OTG]);
/*
* Handshake with mmdc_ch1 module must be masked when changing
* periph2_clk_sel.
*/
clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
/* Disable pll3_sw_clk by selecting the bypass clock source */ /* Disable pll3_sw_clk by selecting the bypass clock source */
reg = readl_relaxed(ccm_base + CCM_CCSR); reg = readl_relaxed(ccm_base + CCM_CCSR);
reg |= CCSR_PLL3_SW_CLK_SEL; reg |= CCSR_PLL3_SW_CLK_SEL;
@ -300,8 +294,6 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base)
reg = readl_relaxed(ccm_base + CCM_CCSR); reg = readl_relaxed(ccm_base + CCM_CCSR);
reg &= ~CCSR_PLL3_SW_CLK_SEL; reg &= ~CCSR_PLL3_SW_CLK_SEL;
writel_relaxed(reg, ccm_base + CCM_CCSR); writel_relaxed(reg, ccm_base + CCM_CCSR);
clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
} }
/* /*