mirror of https://gitee.com/openkylin/linux.git
wl18xx: define HW-rate translation elements/tables
Define HW-rate conversion tables for the 18xx chip. Initialize the appropriate wlcore elements with these tables and values to allow conversion of HW-rates. Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
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@ -37,6 +37,118 @@
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#define WL18XX_TX_HW_GEM_BLOCK_SPARE 2
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#define WL18XX_TX_HW_BLOCK_SIZE 268
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static const u8 wl18xx_rate_to_idx_2ghz[] = {
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/* MCS rates are used only with 11n */
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15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
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14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
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13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
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12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
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/* TI-specific rate */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
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0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
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};
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static const u8 wl18xx_rate_to_idx_5ghz[] = {
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/* MCS rates are used only with 11n */
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15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
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14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
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13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
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12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
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/* TI-specific rate */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
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};
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static const u8 *wl18xx_band_rate_to_idx[] = {
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[IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
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[IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
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};
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enum wl18xx_hw_rates {
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WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
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WL18XX_CONF_HW_RXTX_RATE_MCS14,
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WL18XX_CONF_HW_RXTX_RATE_MCS13,
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WL18XX_CONF_HW_RXTX_RATE_MCS12,
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WL18XX_CONF_HW_RXTX_RATE_MCS11,
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WL18XX_CONF_HW_RXTX_RATE_MCS10,
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WL18XX_CONF_HW_RXTX_RATE_MCS9,
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WL18XX_CONF_HW_RXTX_RATE_MCS8,
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WL18XX_CONF_HW_RXTX_RATE_MCS7,
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WL18XX_CONF_HW_RXTX_RATE_MCS6,
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WL18XX_CONF_HW_RXTX_RATE_MCS5,
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WL18XX_CONF_HW_RXTX_RATE_MCS4,
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WL18XX_CONF_HW_RXTX_RATE_MCS3,
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WL18XX_CONF_HW_RXTX_RATE_MCS2,
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WL18XX_CONF_HW_RXTX_RATE_MCS1,
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WL18XX_CONF_HW_RXTX_RATE_MCS0,
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WL18XX_CONF_HW_RXTX_RATE_54,
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WL18XX_CONF_HW_RXTX_RATE_48,
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WL18XX_CONF_HW_RXTX_RATE_36,
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WL18XX_CONF_HW_RXTX_RATE_24,
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WL18XX_CONF_HW_RXTX_RATE_22,
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WL18XX_CONF_HW_RXTX_RATE_18,
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WL18XX_CONF_HW_RXTX_RATE_12,
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WL18XX_CONF_HW_RXTX_RATE_11,
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WL18XX_CONF_HW_RXTX_RATE_9,
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WL18XX_CONF_HW_RXTX_RATE_6,
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WL18XX_CONF_HW_RXTX_RATE_5_5,
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WL18XX_CONF_HW_RXTX_RATE_2,
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WL18XX_CONF_HW_RXTX_RATE_1,
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WL18XX_CONF_HW_RXTX_RATE_MAX,
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};
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static struct wl18xx_conf wl18xx_default_conf = {
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.phy = {
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.phy_standalone = 0x00,
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@ -363,6 +475,9 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
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wl->num_tx_desc = 32;
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wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
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wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
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wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
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wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
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wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
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return wlcore_probe(wl, pdev);
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}
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@ -45,7 +45,15 @@ enum {
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CONF_HW_BIT_RATE_MCS_4 = BIT(17),
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CONF_HW_BIT_RATE_MCS_5 = BIT(18),
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CONF_HW_BIT_RATE_MCS_6 = BIT(19),
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CONF_HW_BIT_RATE_MCS_7 = BIT(20)
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CONF_HW_BIT_RATE_MCS_7 = BIT(20),
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CONF_HW_BIT_RATE_MCS_8 = BIT(21),
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CONF_HW_BIT_RATE_MCS_9 = BIT(22),
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CONF_HW_BIT_RATE_MCS_10 = BIT(23),
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CONF_HW_BIT_RATE_MCS_11 = BIT(24),
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CONF_HW_BIT_RATE_MCS_12 = BIT(25),
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CONF_HW_BIT_RATE_MCS_13 = BIT(26),
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CONF_HW_BIT_RATE_MCS_14 = BIT(27),
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CONF_HW_BIT_RATE_MCS_15 = BIT(28),
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};
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enum {
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