openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

amdgpu DC display code for Vega. 

-----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJaDlaqAAoJEAx081l5xIa+VB8P/3tl1kg6gONXBHA89t4aoyaM
 uKyLy2D8//9RCPupnI2nOablbcdXzmZYE5gsLGHcN5G/cf9qHksslqo6P/8cjfIC
 lOz+2AxzFGTP9s6M0jyE7l4Dlk53Chd+7yOTJfm322BUuAZW7nSjWGglkO6rW6RR
 JRyNwIoRLX62nAkD769R9QTh8sh2P7pWvXKUSRtMQVWRRI0fICvUFuqyBbEFjJZN
 4GGkqM5bA6GU+z1W91iqkXoPWz34Zejch7cLBM5pXiZsgXOuzl4V/RwxdKZlWVrf
 9oA9357yKvvvb1bkNRgjNqLLHdOxQUomv1k2RxCbvX2xUecOCTKXKb4/X+AurZEI
 ENfSejTbzj+mP18CI1IsvsQolkighP1xxqjH3zmSu+bS0ivWBywbpDUVN969qKrV
 9kHigMwxxX5YCWGoLswhZ+6OsPm5R2FRKg10QVQAlARjye4Q7ssP+l+KRRP8rvkc
 D4rZiLBMuIDersRhW3ylEym8gXqSO2BoBJZS3+ECSzweIhvwziNgY0q6lpFxfzJa
 fzjW/mfK/uucEshoZrxJVRAEiWwtULvi1KVnTpQ/lm254maj4mOy6atqs7rmdAKK
 Jetfg+Z0Fb+805fHeS2dk/E855qwmTCsBf+TA4hGrxoW3EHB3yNLH1j4MSUxK8es
 6SpuEv7hzeyCiK0QJcSH
 =0JS4
 -----END PGP SIGNATURE-----

Merge tag 'drm-for-v4.15-amd-dc' of git://people.freedesktop.org/~airlied/linux

Pull amdgpu DC display code for Vega from Dave Airlie:
 "This is the pull request for the AMD DC (display code) layer which is
  a requirement to program the display engines on the new Vega and Raven
  based GPUs. It also contains support for all amdgpu supported GPUs
  (CIK, VI, Polaris), which has to be enabled. It is also a kms atomic
  modesetting compatible driver (unlike the current in-tree display
  code).

  I've kept it separate from drm-next because it may have some things
  that cause you to reject it.

  Background story:

  AMD have an internal team creating a shared OS codebase for display at
  hw bring up time using information from their hardware teams. This
  process doesn't lead to the most Linux friendly/looking code but we
  have worked together on cleaning a lot of it up and dealing with
  sparse/smatch/checkpatch, and having their team internally adhere to
  Linux coding standards.

  This tree is a complete history rebased since they started opening it,
  we decided not to squash it down as the history may have some value.
  Some of the commits therefore might not reach kernel standards, and we
  are steadily training people in AMD to better write commit msgs.

  There is a major bunch of generated bandwidth calculation and
  verification code that comes from their hardware team. On Vega and
  before this is float calculations, on Raven (DCN10) this is double
  based. They do the required things to do FP in the kernel, and I could
  understand this might raise some issues. Rewriting the bandwidth would
  be a major undertaken in reverification, it's non-trivial to work out
  if a display can handle the complete set of mode information thrown at
  it.

  Future story:

  There is a TODO list with this, and it address most of the remaining
  things that would be nice to refine/remove. The DCN10 code is still
  under development internally and they push out a lot of patches quite
  regularly and are supporting this code base with their display team. I
  think we've reached the point where keeping it out of tree is going to
  motivate distributions to start carrying the code, so I'd prefer we
  get it in tree. I think this code is slightly better than STAGING
  quality but not massively so, I'd really like to see that float/double
  magic gone and fixed point used, but AMD don't seem to think the
  accuracy and revalidation of the code is worth the effort"

* tag 'drm-for-v4.15-amd-dc' of git://people.freedesktop.org/~airlied/linux: (1110 commits)
  drm/amd/display: fix MST link training fail division by 0
  drm/amd/display: Fix formatting for null pointer dereference fix
  drm/amd/display: Remove dangling planes on dc commit state
  drm/amd/display: add flip_immediate to commit update for stream
  drm/amd/display: Miss register MST encoder cbs
  drm/amd/display: Fix warnings on S3 resume
  drm/amd/display: use num_timing_generator instead of pipe_count
  drm/amd/display: use configurable FBC option in dm
  drm/amd/display: fix AZ clock not enabled before program AZ endpoint
  amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check
  amd/display: Fix potential null dereference in dce_calcs.c
  amdgpu/dm: Remove unused forward declaration
  drm/amdgpu: Remove unused dc_stream from amdgpu_crtc
  amdgpu/dc: Fix double unlock in amdgpu_dm_commit_planes
  amdgpu/dc: Fix missing null checks in amdgpu_dm.c
  amdgpu/dc: Fix potential null dereferences in amdgpu_dm.c
  amdgpu/dc: fix more indentation warnings
  amdgpu/dc: handle allocation failures in dc_commit_planes_to_stream.
  amdgpu/dc: fix indentation warning from smatch.
  amdgpu/dc: fix non-ansi function decls.
  ...
This commit is contained in:
Linus Torvalds 2017-11-17 14:34:42 -08:00
parent bec04432cb 49e37ba07a
commit f6705bf959
368 changed files with 132395 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/gpu/todo.rst
View File

@ -409,5 +409,15 @@ those drivers as simple as possible, so lots of room for refactoring:
Contact: Noralf Trønnes, Daniel Vetter
AMD DC Display Driver
---------------------
AMD DC is the display driver for AMD devices starting with Vega. There has been
a bunch of progress cleaning it up but there's still plenty of work to be done.
See drivers/gpu/drm/amd/display/TODO for tasks.
Contact: Harry Wentland, Alex Deucher
Outside DRM
===========

1
drivers/gpu/drm/amd/amdgpu/Kconfig
View File

@ -41,3 +41,4 @@ config DRM_AMDGPU_GART_DEBUGFS
pages. Uses more memory for housekeeping, enable only for debugging.
source "drivers/gpu/drm/amd/acp/Kconfig"
source "drivers/gpu/drm/amd/display/Kconfig"

17
drivers/gpu/drm/amd/amdgpu/Makefile
View File

@ -4,13 +4,19 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
FULL_AMD_PATH=$(src)/..
DISPLAY_FOLDER_NAME=display
FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)
ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_PATH)/include \
-I$(FULL_AMD_PATH)/amdgpu \
-I$(FULL_AMD_PATH)/scheduler \
-I$(FULL_AMD_PATH)/powerplay/inc \
-I$(FULL_AMD_PATH)/acp/include
-I$(FULL_AMD_PATH)/acp/include \
-I$(FULL_AMD_DISPLAY_PATH) \
-I$(FULL_AMD_DISPLAY_PATH)/include \
-I$(FULL_AMD_DISPLAY_PATH)/dc \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm
amdgpu-y := amdgpu_drv.o
@ -133,4 +139,13 @@ include $(FULL_AMD_PATH)/powerplay/Makefile
amdgpu-y += $(AMD_POWERPLAY_FILES)
ifneq ($(CONFIG_DRM_AMD_DC),)
RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME)
include $(FULL_AMD_DISPLAY_PATH)/Makefile
amdgpu-y += $(AMD_DISPLAY_FILES)
endif
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o

16
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -66,6 +66,7 @@
#include "amdgpu_vce.h"
#include "amdgpu_vcn.h"
#include "amdgpu_mn.h"
#include "amdgpu_dm.h"
#include "gpu_scheduler.h"
#include "amdgpu_virt.h"
@ -101,6 +102,8 @@ extern int amdgpu_vm_fragment_size;
extern int amdgpu_vm_fault_stop;
extern int amdgpu_vm_debug;
extern int amdgpu_vm_update_mode;
extern int amdgpu_dc;
extern int amdgpu_dc_log;
extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern int amdgpu_no_evict;
@ -1535,6 +1538,7 @@ struct amdgpu_device {
/* display */
bool enable_virtual_display;
struct amdgpu_mode_info mode_info;
/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
struct work_struct hotplug_work;
struct amdgpu_irq_src crtc_irq;
struct amdgpu_irq_src pageflip_irq;
@ -1590,6 +1594,9 @@ struct amdgpu_device {
/* GDS */
struct amdgpu_gds gds;
/* display related functionality */
struct amdgpu_display_manager dm;
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
int num_ip_blocks;
struct mutex mn_lock;
@ -1653,6 +1660,9 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
/*
* Registers read & write functions.
*/
@ -1911,5 +1921,11 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
uint64_t addr, struct amdgpu_bo **bo,
struct amdgpu_bo_va_mapping **mapping);
#if defined(CONFIG_DRM_AMD_DC)
int amdgpu_dm_display_resume(struct amdgpu_device *adev );
#else
static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
#endif
#include "amdgpu_object.h"
#endif

59
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
View File

@ -911,10 +911,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
struct cgs_display_info *info)
{
CGS_FUNC_ADEV;
struct amdgpu_crtc *amdgpu_crtc;
struct drm_device *ddev = adev->ddev;
struct drm_crtc *crtc;
uint32_t line_time_us, vblank_lines;
struct cgs_mode_info *mode_info;
if (info == NULL)
@ -928,30 +924,43 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
mode_info->ref_clock = adev->clock.spll.reference_freq;
}
if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
list_for_each_entry(crtc,
&ddev->mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
if (crtc->enabled) {
info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
info->display_count++;
}
if (mode_info != NULL &&
crtc->enabled && amdgpu_crtc->enabled &&
amdgpu_crtc->hw_mode.clock) {
line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
amdgpu_crtc->hw_mode.clock;
vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
amdgpu_crtc->hw_mode.crtc_vdisplay +
(amdgpu_crtc->v_border * 2);
mode_info->vblank_time_us = vblank_lines * line_time_us;
mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
mode_info->ref_clock = adev->clock.spll.reference_freq;
mode_info = NULL;
if (!amdgpu_device_has_dc_support(adev)) {
struct amdgpu_crtc *amdgpu_crtc;
struct drm_device *ddev = adev->ddev;
struct drm_crtc *crtc;
uint32_t line_time_us, vblank_lines;
if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
list_for_each_entry(crtc,
&ddev->mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
if (crtc->enabled) {
info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
info->display_count++;
}
if (mode_info != NULL &&
crtc->enabled && amdgpu_crtc->enabled &&
amdgpu_crtc->hw_mode.clock) {
line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
amdgpu_crtc->hw_mode.clock;
vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
amdgpu_crtc->hw_mode.crtc_vdisplay +
(amdgpu_crtc->v_border * 2);
mode_info->vblank_time_us = vblank_lines * line_time_us;
mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
mode_info->ref_clock = adev->clock.spll.reference_freq;
mode_info = NULL;
}
}
}
} else {
info->display_count = adev->pm.pm_display_cfg.num_display;
if (mode_info != NULL) {
mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
mode_info->ref_clock = adev->clock.spll.reference_freq;
}
}
return 0;
}

105
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -31,6 +31,7 @@
#include <linux/debugfs.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/amdgpu_drm.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>
@ -2046,6 +2047,52 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
}
}
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
{
switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
case CHIP_TONGA:
case CHIP_FIJI:
#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
return amdgpu_dc != 0;
#endif
case CHIP_KABINI:
case CHIP_MULLINS:
return amdgpu_dc > 0;
case CHIP_VEGA10:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
#endif
return amdgpu_dc != 0;
#endif
default:
return false;
}
}
/**
* amdgpu_device_has_dc_support - check if dc is supported
*
* @adev: amdgpu_device_pointer
*
* Returns true for supported, false for not supported
*/
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
{
if (amdgpu_sriov_vf(adev))
return false;
return amdgpu_device_asic_has_dc_support(adev->asic_type);
}
/**
* amdgpu_device_init - initialize the driver
*
@ -2100,7 +2147,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
@ -2242,7 +2288,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
goto failed;
}
/* init i2c buses */
amdgpu_atombios_i2c_init(adev);
if (!amdgpu_device_has_dc_support(adev))
amdgpu_atombios_i2c_init(adev);
}
/* Fence driver */
@ -2378,7 +2425,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
adev->accel_working = false;
cancel_delayed_work_sync(&adev->late_init_work);
/* free i2c buses */
amdgpu_i2c_fini(adev);
if (!amdgpu_device_has_dc_support(adev))
amdgpu_i2c_fini(adev);
amdgpu_atombios_fini(adev);
kfree(adev->bios);
adev->bios = NULL;
@ -2429,12 +2477,14 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
drm_kms_helper_poll_disable(dev);
/* turn off display hw */
drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
if (!amdgpu_device_has_dc_support(adev)) {
/* turn off display hw */
drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
}
drm_modeset_unlock_all(dev);
}
drm_modeset_unlock_all(dev);
amdgpu_amdkfd_suspend(adev);
@ -2577,13 +2627,25 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
/* blat the mode back in */
if (fbcon) {
drm_helper_resume_force_mode(dev);
/* turn on display hw */
drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
if (!amdgpu_device_has_dc_support(adev)) {
/* pre DCE11 */
drm_helper_resume_force_mode(dev);
/* turn on display hw */
drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
}
drm_modeset_unlock_all(dev);
} else {
/*
* There is no equivalent atomic helper to turn on
* display, so we defined our own function for this,
* once suspend resume is supported by the atomic
* framework this will be reworked
*/
amdgpu_dm_display_resume(adev);
}
drm_modeset_unlock_all(dev);
}
drm_kms_helper_poll_enable(dev);
@ -2600,7 +2662,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
#ifdef CONFIG_PM
dev->dev->power.disable_depth++;
#endif
drm_helper_hpd_irq_event(dev);
if (!amdgpu_device_has_dc_support(adev))
drm_helper_hpd_irq_event(dev);
else
drm_kms_helper_hotplug_event(dev);
#ifdef CONFIG_PM
dev->dev->power.disable_depth--;
#endif
@ -2900,6 +2965,7 @@ int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
*/
int amdgpu_gpu_reset(struct amdgpu_device *adev)
{
struct drm_atomic_state *state = NULL;
int i, r;
int resched;
bool need_full_reset, vram_lost = false;
@ -2913,6 +2979,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
/* block TTM */
resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
/* store modesetting */
if (amdgpu_device_has_dc_support(adev))
state = drm_atomic_helper_suspend(adev->ddev);
/* block scheduler */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
@ -3029,7 +3098,11 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
}
}
drm_helper_resume_force_mode(adev->ddev);
if (amdgpu_device_has_dc_support(adev)) {
r = drm_atomic_helper_resume(adev->ddev, state);
amdgpu_dm_display_resume(adev);
} else
drm_helper_resume_force_mode(adev->ddev);
ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
if (r) {

4
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
View File

@ -518,7 +518,7 @@ amdgpu_framebuffer_init(struct drm_device *dev,
return 0;
}
static struct drm_framebuffer *
struct drm_framebuffer *
amdgpu_user_framebuffer_create(struct drm_device *dev,
struct drm_file *file_priv,
const struct drm_mode_fb_cmd2 *mode_cmd)
@ -556,7 +556,7 @@ amdgpu_user_framebuffer_create(struct drm_device *dev,
return &amdgpu_fb->base;
}
static void amdgpu_output_poll_changed(struct drm_device *dev)
void amdgpu_output_poll_changed(struct drm_device *dev)
{
struct amdgpu_device *adev = dev->dev_private;
amdgpu_fb_output_poll_changed(adev);

33
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_DISPLAY_H__
#define __AMDGPU_DISPLAY_H__
struct drm_framebuffer *
amdgpu_user_framebuffer_create(struct drm_device *dev,
struct drm_file *file_priv,
const struct drm_mode_fb_cmd2 *mode_cmd);
void amdgpu_output_poll_changed(struct drm_device *dev);
#endif

2
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
View File

@ -433,7 +433,7 @@ struct amdgpu_pm {
uint32_t fw_version;
uint32_t pcie_gen_mask;
uint32_t pcie_mlw_mask;
struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
};
#define R600_SSTU_DFLT 0

26
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -106,6 +106,8 @@ int amdgpu_vm_debug = 0;
int amdgpu_vram_page_split = 512;
int amdgpu_vm_update_mode = -1;
int amdgpu_exp_hw_support = 0;
int amdgpu_dc = -1;
int amdgpu_dc_log = 0;
int amdgpu_sched_jobs = 32;
int amdgpu_sched_hw_submission = 2;
int amdgpu_no_evict = 0;
@ -211,6 +213,12 @@ module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
module_param_named(dc, amdgpu_dc, int, 0444);
MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty");
module_param_named(dc_log, amdgpu_dc_log, int, 0444);
MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
@ -518,15 +526,15 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
/* Vega 10 */
{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
/* Raven */
{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},

8
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
View File

@ -42,11 +42,6 @@
this contains a helper + a amdgpu fb
the helper contains a pointer to amdgpu framebuffer baseclass.
*/
struct amdgpu_fbdev {
struct drm_fb_helper helper;
struct amdgpu_framebuffer rfb;
struct amdgpu_device *adev;
};
static int
amdgpufb_open(struct fb_info *info, int user)
@ -353,7 +348,8 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
/* disable all the possible outputs/crtcs before entering KMS mode */
drm_helper_disable_unused_functions(adev->ddev);
if (!amdgpu_device_has_dc_support(adev))
drm_helper_disable_unused_functions(adev->ddev);
drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
return 0;

29
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
View File

@ -37,6 +37,10 @@
#include <linux/pm_runtime.h>
#ifdef CONFIG_DRM_AMD_DC
#include "amdgpu_dm_irq.h"
#endif
#define AMDGPU_WAIT_IDLE_TIMEOUT 200
/*
@ -221,15 +225,6 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
spin_lock_init(&adev->irq.lock);
if (!adev->enable_virtual_display)
/* Disable vblank irqs aggressively for power-saving */
adev->ddev->vblank_disable_immediate = true;
r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
if (r) {
return r;
}
/* enable msi */
adev->irq.msi_enabled = false;
@ -241,7 +236,21 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
}
}
INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
if (!amdgpu_device_has_dc_support(adev)) {
if (!adev->enable_virtual_display)
/* Disable vblank irqs aggressively for power-saving */
/* XXX: can this be enabled for DC? */
adev->ddev->vblank_disable_immediate = true;
r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
if (r)
return r;
/* pre DCE11 */
INIT_WORK(&adev->hotplug_work,
amdgpu_hotplug_work_func);
}
INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
adev->irq.installed = true;

2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -1030,7 +1030,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
};
const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);

97
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
View File

@ -38,11 +38,15 @@
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/hrtimer.h>
#include "amdgpu_irq.h"
#include <drm/drm_dp_mst_helper.h>
#include "modules/inc/mod_freesync.h"
struct amdgpu_bo;
struct amdgpu_device;
struct amdgpu_encoder;
@ -53,9 +57,13 @@ struct amdgpu_hpd;
#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
#define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base)
#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base);
#define AMDGPU_MAX_HPD_PINS 6
#define AMDGPU_MAX_CRTCS 6
#define AMDGPU_MAX_PLANES 6
#define AMDGPU_MAX_AFMT_BLOCKS 9
enum amdgpu_rmx_type {
@ -292,6 +300,30 @@ struct amdgpu_display_funcs {
uint16_t connector_object_id,
struct amdgpu_hpd *hpd,
struct amdgpu_router *router);
/* it is used to enter or exit into free sync mode */
int (*notify_freesync)(struct drm_device *dev, void *data,
struct drm_file *filp);
/* it is used to allow enablement of freesync mode */
int (*set_freesync_property)(struct drm_connector *connector,
struct drm_property *property,
uint64_t val);
};
struct amdgpu_framebuffer {
struct drm_framebuffer base;
struct drm_gem_object *obj;
/* caching for later use */
uint64_t address;
};
struct amdgpu_fbdev {
struct drm_fb_helper helper;
struct amdgpu_framebuffer rfb;
struct list_head fbdev_list;
struct amdgpu_device *adev;
};
struct amdgpu_mode_info {
@ -299,6 +331,7 @@ struct amdgpu_mode_info {
struct card_info *atom_card_info;
bool mode_config_initialized;
struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
/* DVI-I properties */
struct drm_property *coherent_mode_property;
@ -328,6 +361,7 @@ struct amdgpu_mode_info {
int num_dig; /* number of dig blocks */
int disp_priority;
const struct amdgpu_display_funcs *funcs;
const enum drm_plane_type *plane_type;
};
#define AMDGPU_MAX_BL_LEVEL 0xFF
@ -400,6 +434,14 @@ struct amdgpu_crtc {
/* for virtual dce */
struct hrtimer vblank_timer;
enum amdgpu_interrupt_state vsync_timer_enabled;
int otg_inst;
struct drm_pending_vblank_event *event;
};
struct amdgpu_plane {
struct drm_plane base;
enum drm_plane_type plane_type;
};
struct amdgpu_encoder_atom_dig {
@ -489,6 +531,19 @@ enum amdgpu_connector_dither {
AMDGPU_FMT_DITHER_ENABLE = 1,
};
struct amdgpu_dm_dp_aux {
struct drm_dp_aux aux;
struct ddc_service *ddc_service;
};
struct amdgpu_i2c_adapter {
struct i2c_adapter base;
struct ddc_service *ddc_service;
};
#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
struct amdgpu_connector {
struct drm_connector base;
uint32_t connector_id;
@ -500,6 +555,14 @@ struct amdgpu_connector {
/* we need to mind the EDID between detect
and get modes due to analog/digital/tvencoder */
struct edid *edid;
/* number of modes generated from EDID at 'dc_sink' */
int num_modes;
/* The 'old' sink - before an HPD.
* The 'current' sink is in dc_link->sink. */
struct dc_sink *dc_sink;
struct dc_link *dc_link;
struct dc_sink *dc_em_sink;
const struct dc_stream *stream;
void *con_priv;
bool dac_load_detect;
bool detected_by_load; /* if the connection status was determined by load */
@ -510,11 +573,39 @@ struct amdgpu_connector {
enum amdgpu_connector_audio audio;
enum amdgpu_connector_dither dither;
unsigned pixelclock_for_modeset;
struct drm_dp_mst_topology_mgr mst_mgr;
struct amdgpu_dm_dp_aux dm_dp_aux;
struct drm_dp_mst_port *port;
struct amdgpu_connector *mst_port;
struct amdgpu_encoder *mst_encoder;
struct semaphore mst_sem;
/* TODO see if we can merge with ddc_bus or make a dm_connector */
struct amdgpu_i2c_adapter *i2c;
/* Monitor range limits */
int min_vfreq ;
int max_vfreq ;
int pixel_clock_mhz;
/*freesync caps*/
struct mod_freesync_caps caps;
struct mutex hpd_lock;
};
struct amdgpu_framebuffer {
struct drm_framebuffer base;
struct drm_gem_object *obj;
/* TODO: start to use this struct and remove same field from base one */
struct amdgpu_mst_connector {
struct amdgpu_connector base;
struct drm_dp_mst_topology_mgr mst_mgr;
struct amdgpu_dm_dp_aux dm_dp_aux;
struct drm_dp_mst_port *port;
struct amdgpu_connector *mst_port;
bool is_mst_connector;
struct amdgpu_encoder *mst_encoder;
};
#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \

2
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View File

@ -1466,7 +1466,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
list_for_each_entry(crtc,
&ddev->mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
if (crtc->enabled) {
if (amdgpu_crtc->enabled) {
adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
adev->pm.dpm.new_active_crtc_count++;
}

17
drivers/gpu/drm/amd/amdgpu/cik.c
View File

@ -65,6 +65,7 @@
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
#include "amdgpu_dm.h"
#include "amdgpu_amdkfd.h"
#include "amdgpu_powerplay.h"
#include "dce_virtual.h"
@ -1900,6 +1901,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
@ -1914,6 +1919,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
@ -1928,6 +1937,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
@ -1943,6 +1956,10 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);

12
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -532,6 +532,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
@ -545,6 +551,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);

21
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -77,6 +77,7 @@
#endif
#include "dce_virtual.h"
#include "mxgpu_vi.h"
#include "amdgpu_dm.h"
/*
* Indirect registers accessor
@ -1502,6 +1503,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
@ -1518,6 +1523,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
@ -1536,6 +1545,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
@ -1550,6 +1563,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
@ -1567,6 +1584,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
#endif
else
amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);

45
drivers/gpu/drm/amd/display/Kconfig Normal file
View File

@ -0,0 +1,45 @@
menu "Display Engine Configuration"
depends on DRM && DRM_AMDGPU
config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
Raven ASICs.
config DRM_AMD_DC_PRE_VEGA
bool "DC support for Polaris and older ASICs"
default n
help
Choose this option to enable the new DC support for older asics
by default. This includes Polaris, Carrizo, Tonga, Bonaire,
and Hawaii.
config DRM_AMD_DC_FBC
bool "AMD FBC - Enable Frame Buffer Compression"
depends on DRM_AMD_DC
help
Choose this option if you want to use frame buffer compression
support.
This is a power optimisation feature, check its availability
on your hardware before enabling this option.
config DRM_AMD_DC_DCN1_0
bool "DCN 1.0 Raven family"
depends on DRM_AMD_DC && X86
help
Choose this option if you want to have
RV family for display engine
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
help
Choose this option
if you want to hit
kdgb_break in assert.
endmenu

22
drivers/gpu/drm/amd/display/Makefile Normal file
View File

@ -0,0 +1,22 @@
#
# Makefile for the DAL (Display Abstract Layer), which is a sub-component
# of the AMDGPU drm driver.
# It provides the HW control for display related functionalities.
AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/hw
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
#TODO: remove when Timing Sync feature is complete
subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
DAL_LIBS = amdgpu_dm dc modules/freesync
AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
include $(AMD_DAL)

107
drivers/gpu/drm/amd/display/TODO Normal file
View File

@ -0,0 +1,107 @@
===============================================================================
TODOs
===============================================================================
1. Base this on drm-next - WIP
2. Cleanup commit history
3. WIP - Drop page flip helper and use DRM's version
4. DONE - Flatten all DC objects
* dc_stream/core_stream/stream should just be dc_stream
* Same for other DC objects
"Is there any major reason to keep all those abstractions?
Could you collapse everything into struct dc_stream?
I haven't looked recently but I didn't get the impression there was a
lot of design around what was public/protected, more whatever needed
to be used by someone else was in public."
~ Dave Airlie
5. DONE - Rename DC objects to align more with DRM
* dc_surface -> dc_plane_state
* dc_stream -> dc_stream_state
6. DONE - Per-plane and per-stream validation
7. WIP - Per-plane and per-stream commit
8. WIP - Split pipe_ctx into plane and stream resource structs
9. Attach plane and stream reources to state object instead of validate_context
10. Remove dc_edid_caps and drm_helpers_parse_edid_caps
* Use drm_display_info instead
* Remove DC's edid quirks and rely on DRM's quirks (add quirks if needed)
"Making sure you use the sink-specific helper libraries and kernel
subsystems, since there's really no good reason to have 2nd
implementation of those in the kernel. Looks likes that's done for mst
and edid parsing. There's still a bit a midlayer feeling to the edid
parsing side (e.g. dc_edid_caps and dm_helpers_parse_edid_caps, I
think it'd be much better if you convert that over to reading stuff
from drm_display_info and if needed, push stuff into the core). Also,
I can't come up with a good reason why DC needs all this (except to
reimplement half of our edid quirk table, which really isn't a good
idea). Might be good if you put this onto the list of things to fix
long-term, but imo not a blocker. Definitely make sure new stuff
doesn't slip in (i.e. if you start adding edid quirks to DC instead of
the drm core, refactoring to use the core edid stuff was pointless)."
~ Daniel Vetter
11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically an
overy complicated HW programming function for sendind and receiving i2c/aux
commands. We can greatly simplify that and move it into dc/dceXYZ like other
HW blocks.
12. drm_modeset_lock in MST should no longer be needed in recent kernels
* Adopt appropriate locking scheme
13. get_modes and best_encoder callbacks look a bit funny. Can probably rip out
a few indirections, and consider removing entirely and using the
drm_atomic_helper_best_encoder default behaviour.
14. core/dc_debug.c, consider switching to the atomic state debug helpers and
moving all your driver state printing into the various atomic_print_state
callbacks. There's also plans to expose this stuff in a standard way across all
drivers, to make debugging userspace compositors easier across different hw.
15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c. See
dal_ddc_service_i2c_query_dp_dual_mode_adaptor.
16. Move to core SCDC helpers (I think those are new since initial DC review).
17. There's still a pretty massive layer cake around dp aux and DPCD handling,
with like 3 levels of abstraction and using your own structures instead of the
stuff in drm_dp_helper.h. drm_dp_helper.h isn't really great and already has 2
incompatible styles, just means more reasons not to add a third (or well third
one gets to do the cleanup refactor).
18. There's a pile of sink handling code, both for DP and HDMI where I didn't
immediately recognize the standard. I think long term it'd be best for the drm
subsystem if we try to move as much of that into helpers/core as possible, and
share it with drivers. But that's a very long term goal, and by far not just an
issue with DC - other drivers, especially around DP sink handling, are equally
guilty.
19. The DC logger is still a rather sore thing, but I know that the DRM_DEBUG
stuff just isn't up to the challenges either. We need to figure out something
that integrates better with DRM and linux debug printing, while not being
useless with filtering output. dynamic debug printing might be an option.
20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
retimer that we need to program to pass PHY compliance. Currently that's
bypassing the i2c device and goes directly to HW. This should be changed.

17
drivers/gpu/drm/amd/display/amdgpu_dm/Makefile Normal file
View File

@ -0,0 +1,17 @@
#
# Makefile for the 'dm' sub-component of DAL.
# It provides the control and status of dm blocks.
AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
ifneq ($(CONFIG_DRM_AMD_DC),)
AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
endif
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc
AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
AMD_DISPLAY_FILES += $(AMDGPU_DM)

4925
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c Normal file
View File

File diff suppressed because it is too large Load Diff

259
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h Normal file
View File

@ -0,0 +1,259 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __AMDGPU_DM_H__
#define __AMDGPU_DM_H__
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include "dc.h"
/*
* This file contains the definition for amdgpu_display_manager
* and its API for amdgpu driver's use.
* This component provides all the display related functionality
* and this is the only component that calls DAL API.
* The API contained here intended for amdgpu driver use.
* The API that is called directly from KMS framework is located
* in amdgpu_dm_kms.h file
*/
#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
/*
#include "include/amdgpu_dal_power_if.h"
#include "amdgpu_dm_irq.h"
*/
#include "irq_types.h"
#include "signal_types.h"
/* Forward declarations */
struct amdgpu_device;
struct drm_device;
struct amdgpu_dm_irq_handler_data;
struct amdgpu_dm_prev_state {
struct drm_framebuffer *fb;
int32_t x;
int32_t y;
struct drm_display_mode mode;
};
struct common_irq_params {
struct amdgpu_device *adev;
enum dc_irq_source irq_src;
};
struct irq_list_head {
struct list_head head;
/* In case this interrupt needs post-processing, 'work' will be queued*/
struct work_struct work;
};
#if defined(CONFIG_DRM_AMD_DC_FBC)
struct dm_comressor_info {
void *cpu_addr;
struct amdgpu_bo *bo_ptr;
uint64_t gpu_addr;
};
#endif
struct amdgpu_display_manager {
struct dal *dal;
struct dc *dc;
struct cgs_device *cgs_device;
/* lock to be used when DAL is called from SYNC IRQ context */
spinlock_t dal_lock;
struct amdgpu_device *adev; /*AMD base driver*/
struct drm_device *ddev; /*DRM base driver*/
u16 display_indexes_num;
struct amdgpu_dm_prev_state prev_state;
/*
* 'irq_source_handler_table' holds a list of handlers
* per (DAL) IRQ source.
*
* Each IRQ source may need to be handled at different contexts.
* By 'context' we mean, for example:
* - The ISR context, which is the direct interrupt handler.
* - The 'deferred' context - this is the post-processing of the
* interrupt, but at a lower priority.
*
* Note that handlers are called in the same order as they were
* registered (FIFO).
*/
struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
struct common_irq_params
pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
struct common_irq_params
vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
/* this spin lock synchronizes access to 'irq_handler_list_table' */
spinlock_t irq_handler_list_table_lock;
/* Timer-related data. */
struct list_head timer_handler_list;
struct workqueue_struct *timer_workqueue;
/* Use dal_mutex for any activity which is NOT syncronized by
* DRM mode setting locks.
* For example: amdgpu_dm_hpd_low_irq() calls into DAL *without*
* DRM mode setting locks being acquired. This is where dal_mutex
* is acquired before calling into DAL. */
struct mutex dal_mutex;
struct backlight_device *backlight_dev;
const struct dc_link *backlight_link;
struct work_struct mst_hotplug_work;
struct mod_freesync *freesync_module;
/**
* Caches device atomic state for suspend/resume
*/
struct drm_atomic_state *cached_state;
#if defined(CONFIG_DRM_AMD_DC_FBC)
struct dm_comressor_info compressor;
#endif
};
struct amdgpu_dm_connector {
struct drm_connector base;
uint32_t connector_id;
/* we need to mind the EDID between detect
and get modes due to analog/digital/tvencoder */
struct edid *edid;
/* shared with amdgpu */
struct amdgpu_hpd hpd;
/* number of modes generated from EDID at 'dc_sink' */
int num_modes;
/* The 'old' sink - before an HPD.
* The 'current' sink is in dc_link->sink. */
struct dc_sink *dc_sink;
struct dc_link *dc_link;
struct dc_sink *dc_em_sink;
/* DM only */
struct drm_dp_mst_topology_mgr mst_mgr;
struct amdgpu_dm_dp_aux dm_dp_aux;
struct drm_dp_mst_port *port;
struct amdgpu_dm_connector *mst_port;
struct amdgpu_encoder *mst_encoder;
/* TODO see if we can merge with ddc_bus or make a dm_connector */
struct amdgpu_i2c_adapter *i2c;
/* Monitor range limits */
int min_vfreq ;
int max_vfreq ;
int pixel_clock_mhz;
/*freesync caps*/
struct mod_freesync_caps caps;
struct mutex hpd_lock;
bool fake_enable;
};
#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
extern const struct amdgpu_ip_block_version dm_ip_block;
struct amdgpu_framebuffer;
struct amdgpu_display_manager;
struct dc_validation_set;
struct dc_plane_state;
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
};
struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream_state *stream;
};
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
struct dm_atomic_state {
struct drm_atomic_state base;
struct dc_state *context;
};
#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
struct drm_connector_state *
amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
uint64_t val);
int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
struct drm_property *property,
uint64_t *val);
int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector,
int connector_type,
struct dc_link *link,
int link_index);
int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode);
void dm_restore_drm_connector_state(struct drm_device *dev,
struct drm_connector *connector);
void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
struct edid *edid);
void
amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
#endif /* __AMDGPU_DM_H__ */

498
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c Normal file
View File

@ -0,0 +1,498 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/string.h>
#include <linux/acpi.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include <drm/drm_edid.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "dc.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
#include "dm_helpers.h"
/* dm_helpers_parse_edid_caps
*
* Parse edid caps
*
* @edid: [in] pointer to edid
* edid_caps: [in] pointer to edid caps
* @return
* void
* */
enum dc_edid_status dm_helpers_parse_edid_caps(
struct dc_context *ctx,
const struct dc_edid *edid,
struct dc_edid_caps *edid_caps)
{
struct edid *edid_buf = (struct edid *) edid->raw_edid;
struct cea_sad *sads;
int sad_count = -1;
int sadb_count = -1;
int i = 0;
int j = 0;
uint8_t *sadb = NULL;
enum dc_edid_status result = EDID_OK;
if (!edid_caps || !edid)
return EDID_BAD_INPUT;
if (!drm_edid_is_valid(edid_buf))
result = EDID_BAD_CHECKSUM;
edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
((uint16_t) edid_buf->mfg_id[1])<<8;
edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
((uint16_t) edid_buf->prod_code[1])<<8;
edid_caps->serial_number = edid_buf->serial;
edid_caps->manufacture_week = edid_buf->mfg_week;
edid_caps->manufacture_year = edid_buf->mfg_year;
/* One of the four detailed_timings stores the monitor name. It's
* stored in an array of length 13. */
for (i = 0; i < 4; i++) {
if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
break;
edid_caps->display_name[j] =
edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
j++;
}
}
}
edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
(struct edid *) edid->raw_edid);
sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
if (sad_count <= 0) {
DRM_INFO("SADs count is: %d, don't need to read it\n",
sad_count);
return result;
}
edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
for (i = 0; i < edid_caps->audio_mode_count; ++i) {
struct cea_sad *sad = &sads[i];
edid_caps->audio_modes[i].format_code = sad->format;
edid_caps->audio_modes[i].channel_count = sad->channels;
edid_caps->audio_modes[i].sample_rate = sad->freq;
edid_caps->audio_modes[i].sample_size = sad->byte2;
}
sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
if (sadb_count < 0) {
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
sadb_count = 0;
}
if (sadb_count)
edid_caps->speaker_flags = sadb[0];
else
edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
kfree(sads);
kfree(sadb);
return result;
}
static void get_payload_table(
struct amdgpu_dm_connector *aconnector,
struct dp_mst_stream_allocation_table *proposed_table)
{
int i;
struct drm_dp_mst_topology_mgr *mst_mgr =
&aconnector->mst_port->mst_mgr;
mutex_lock(&mst_mgr->payload_lock);
proposed_table->stream_count = 0;
/* number of active streams */
for (i = 0; i < mst_mgr->max_payloads; i++) {
if (mst_mgr->payloads[i].num_slots == 0)
break; /* end of vcp_id table */
ASSERT(mst_mgr->payloads[i].payload_state !=
DP_PAYLOAD_DELETE_LOCAL);
if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
mst_mgr->payloads[i].payload_state ==
DP_PAYLOAD_REMOTE) {
struct dp_mst_stream_allocation *sa =
&proposed_table->stream_allocations[
proposed_table->stream_count];
sa->slot_count = mst_mgr->payloads[i].num_slots;
sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
proposed_table->stream_count++;
}
}
mutex_unlock(&mst_mgr->payload_lock);
}
/*
* Writes payload allocation table in immediate downstream device.
*/
bool dm_helpers_dp_mst_write_payload_allocation_table(
struct dc_context *ctx,
const struct dc_stream_state *stream,
struct dp_mst_stream_allocation_table *proposed_table,
bool enable)
{
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
struct drm_dp_mst_port *mst_port;
int slots = 0;
bool ret;
int clock;
int bpp = 0;
int pbn = 0;
aconnector = stream->sink->priv;
if (!aconnector || !aconnector->mst_port)
return false;
mst_mgr = &aconnector->mst_port->mst_mgr;
if (!mst_mgr->mst_state)
return false;
mst_port = aconnector->port;
if (enable) {
clock = stream->timing.pix_clk_khz;
switch (stream->timing.display_color_depth) {
case COLOR_DEPTH_666:
bpp = 6;
break;
case COLOR_DEPTH_888:
bpp = 8;
break;
case COLOR_DEPTH_101010:
bpp = 10;
break;
case COLOR_DEPTH_121212:
bpp = 12;
break;
case COLOR_DEPTH_141414:
bpp = 14;
break;
case COLOR_DEPTH_161616:
bpp = 16;
break;
default:
ASSERT(bpp != 0);
break;
}
bpp = bpp * 3;
/* TODO need to know link rate */
pbn = drm_dp_calc_pbn_mode(clock, bpp);
slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
if (!ret)
return false;
} else {
drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
}
ret = drm_dp_update_payload_part1(mst_mgr);
/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
* AUX message. The sequence is slot 1-63 allocated sequence for each
* stream. AMD ASIC stream slot allocation should follow the same
* sequence. copy DRM MST allocation to dc */
get_payload_table(aconnector, proposed_table);
if (ret)
return false;
return true;
}
/*
* Polls for ACT (allocation change trigger) handled and sends
* ALLOCATE_PAYLOAD message.
*/
bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
struct dc_context *ctx,
const struct dc_stream_state *stream)
{
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
int ret;
aconnector = stream->sink->priv;
if (!aconnector || !aconnector->mst_port)
return false;
mst_mgr = &aconnector->mst_port->mst_mgr;
if (!mst_mgr->mst_state)
return false;
ret = drm_dp_check_act_status(mst_mgr);
if (ret)
return false;
return true;
}
bool dm_helpers_dp_mst_send_payload_allocation(
struct dc_context *ctx,
const struct dc_stream_state *stream,
bool enable)
{
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_mgr *mst_mgr;
struct drm_dp_mst_port *mst_port;
int ret;
aconnector = stream->sink->priv;
if (!aconnector || !aconnector->mst_port)
return false;
mst_port = aconnector->port;
mst_mgr = &aconnector->mst_port->mst_mgr;
if (!mst_mgr->mst_state)
return false;
ret = drm_dp_update_payload_part2(mst_mgr);
if (ret)
return false;
if (!enable)
drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
return true;
}
bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enum dc_log_type event)
{
return true;
}
void dm_dtn_log_begin(struct dc_context *ctx)
{}
void dm_dtn_log_append_v(struct dc_context *ctx,
const char *pMsg, ...)
{}
void dm_dtn_log_end(struct dc_context *ctx)
{}
bool dm_helpers_dp_mst_start_top_mgr(
struct dc_context *ctx,
const struct dc_link *link,
bool boot)
{
struct amdgpu_dm_connector *aconnector = link->priv;
if (!aconnector) {
DRM_ERROR("Failed to found connector for link!");
return false;
}
if (boot) {
DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
return true;
}
DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
}
void dm_helpers_dp_mst_stop_top_mgr(
struct dc_context *ctx,
const struct dc_link *link)
{
struct amdgpu_dm_connector *aconnector = link->priv;
if (!aconnector) {
DRM_ERROR("Failed to found connector for link!");
return;
}
DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
if (aconnector->mst_mgr.mst_state == true)
drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
}
bool dm_helpers_dp_read_dpcd(
struct dc_context *ctx,
const struct dc_link *link,
uint32_t address,
uint8_t *data,
uint32_t size)
{
struct amdgpu_dm_connector *aconnector = link->priv;
if (!aconnector) {
DRM_ERROR("Failed to found connector for link!");
return false;
}
return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
data, size) > 0;
}
bool dm_helpers_dp_write_dpcd(
struct dc_context *ctx,
const struct dc_link *link,
uint32_t address,
const uint8_t *data,
uint32_t size)
{
struct amdgpu_dm_connector *aconnector = link->priv;
if (!aconnector) {
DRM_ERROR("Failed to found connector for link!");
return false;
}
return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
address, (uint8_t *)data, size) > 0;
}
bool dm_helpers_submit_i2c(
struct dc_context *ctx,
const struct dc_link *link,
struct i2c_command *cmd)
{
struct amdgpu_dm_connector *aconnector = link->priv;
struct i2c_msg *msgs;
int i = 0;
int num = cmd->number_of_payloads;
bool result;
if (!aconnector) {
DRM_ERROR("Failed to found connector for link!");
return false;
}
msgs = kzalloc(num * sizeof(struct i2c_msg), GFP_KERNEL);
if (!msgs)
return false;
for (i = 0; i < num; i++) {
msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
msgs[i].addr = cmd->payloads[i].address;
msgs[i].len = cmd->payloads[i].length;
msgs[i].buf = cmd->payloads[i].data;
}
result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
kfree(msgs);
return result;
}
enum dc_edid_status dm_helpers_read_local_edid(
struct dc_context *ctx,
struct dc_link *link,
struct dc_sink *sink)
{
struct amdgpu_dm_connector *aconnector = link->priv;
struct i2c_adapter *ddc;
int retry = 3;
enum dc_edid_status edid_status;
struct edid *edid;
if (link->aux_mode)
ddc = &aconnector->dm_dp_aux.aux.ddc;
else
ddc = &aconnector->i2c->base;
/* some dongles read edid incorrectly the first time,
* do check sum and retry to make sure read correct edid.
*/
do {
edid = drm_get_edid(&aconnector->base, ddc);
if (!edid)
return EDID_NO_RESPONSE;
sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
/* We don't need the original edid anymore */
kfree(edid);
edid_status = dm_helpers_parse_edid_caps(
ctx,
&sink->dc_edid,
&sink->edid_caps);
} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
if (edid_status != EDID_OK)
DRM_ERROR("EDID err: %d, on connector: %s",
edid_status,
aconnector->base.name);
return edid_status;
}

755
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c Normal file
View File

@ -0,0 +1,755 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <drm/drmP.h>
#include "dm_services_types.h"
#include "dc.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
/******************************************************************************
* Private declarations.
*****************************************************************************/
struct handler_common_data {
struct list_head list;
interrupt_handler handler;
void *handler_arg;
/* DM which this handler belongs to */
struct amdgpu_display_manager *dm;
};
struct amdgpu_dm_irq_handler_data {
struct handler_common_data hcd;
/* DAL irq source which registered for this interrupt. */
enum dc_irq_source irq_source;
};
struct amdgpu_dm_timer_handler_data {
struct handler_common_data hcd;
struct delayed_work d_work;
};
#define DM_IRQ_TABLE_LOCK(adev, flags) \
spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
#define DM_IRQ_TABLE_UNLOCK(adev, flags) \
spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
/******************************************************************************
* Private functions.
*****************************************************************************/
static void init_handler_common_data(struct handler_common_data *hcd,
void (*ih)(void *),
void *args,
struct amdgpu_display_manager *dm)
{
hcd->handler = ih;
hcd->handler_arg = args;
hcd->dm = dm;
}
/**
* dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
*
* @work: work struct
*/
static void dm_irq_work_func(struct work_struct *work)
{
struct list_head *entry;
struct irq_list_head *irq_list_head =
container_of(work, struct irq_list_head, work);
struct list_head *handler_list = &irq_list_head->head;
struct amdgpu_dm_irq_handler_data *handler_data;
list_for_each(entry, handler_list) {
handler_data =
list_entry(
entry,
struct amdgpu_dm_irq_handler_data,
hcd.list);
DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
handler_data->irq_source);
DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
handler_data->irq_source);
handler_data->hcd.handler(handler_data->hcd.handler_arg);
}
/* Call a DAL subcomponent which registered for interrupt notification
* at INTERRUPT_LOW_IRQ_CONTEXT.
* (The most common use is HPD interrupt) */
}
/**
* Remove a handler and return a pointer to hander list from which the
* handler was removed.
*/
static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
void *ih,
const struct dc_interrupt_params *int_params)
{
struct list_head *hnd_list;
struct list_head *entry, *tmp;
struct amdgpu_dm_irq_handler_data *handler;
unsigned long irq_table_flags;
bool handler_removed = false;
enum dc_irq_source irq_source;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
irq_source = int_params->irq_source;
switch (int_params->int_context) {
case INTERRUPT_HIGH_IRQ_CONTEXT:
hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
break;
case INTERRUPT_LOW_IRQ_CONTEXT:
default:
hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
break;
}
list_for_each_safe(entry, tmp, hnd_list) {
handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
hcd.list);
if (ih == handler) {
/* Found our handler. Remove it from the list. */
list_del(&handler->hcd.list);
handler_removed = true;
break;
}
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
if (handler_removed == false) {
/* Not necessarily an error - caller may not
* know the context. */
return NULL;
}
kfree(handler);
DRM_DEBUG_KMS(
"DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
ih, int_params->irq_source, int_params->int_context);
return hnd_list;
}
/* If 'handler_in == NULL' then remove ALL handlers. */
static void remove_timer_handler(struct amdgpu_device *adev,
struct amdgpu_dm_timer_handler_data *handler_in)
{
struct amdgpu_dm_timer_handler_data *handler_temp;
struct list_head *handler_list;
struct list_head *entry, *tmp;
unsigned long irq_table_flags;
bool handler_removed = false;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
handler_list = &adev->dm.timer_handler_list;
list_for_each_safe(entry, tmp, handler_list) {
/* Note that list_for_each_safe() guarantees that
* handler_temp is NOT null. */
handler_temp = list_entry(entry,
struct amdgpu_dm_timer_handler_data, hcd.list);
if (handler_in == NULL || handler_in == handler_temp) {
list_del(&handler_temp->hcd.list);
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
DRM_DEBUG_KMS("DM_IRQ: removing timer handler: %p\n",
handler_temp);
if (handler_in == NULL) {
/* Since it is still in the queue, it must
* be cancelled. */
cancel_delayed_work_sync(&handler_temp->d_work);
}
kfree(handler_temp);
handler_removed = true;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
}
/* Remove ALL handlers. */
if (handler_in == NULL)
continue;
/* Remove a SPECIFIC handler.
* Found our handler - we can stop here. */
if (handler_in == handler_temp)
break;
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
if (handler_in != NULL && handler_removed == false)
DRM_ERROR("DM_IRQ: handler: %p is not in the list!\n",
handler_in);
}
static bool
validate_irq_registration_params(struct dc_interrupt_params *int_params,
void (*ih)(void *))
{
if (NULL == int_params || NULL == ih) {
DRM_ERROR("DM_IRQ: invalid input!\n");
return false;
}
if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
DRM_ERROR("DM_IRQ: invalid context: %d!\n",
int_params->int_context);
return false;
}
if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
int_params->irq_source);
return false;
}
return true;
}
static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
irq_handler_idx handler_idx)
{
if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
return false;
}
if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
return false;
}
return true;
}
/******************************************************************************
* Public functions.
*
* Note: caller is responsible for input validation.
*****************************************************************************/
void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
struct dc_interrupt_params *int_params,
void (*ih)(void *),
void *handler_args)
{
struct list_head *hnd_list;
struct amdgpu_dm_irq_handler_data *handler_data;
unsigned long irq_table_flags;
enum dc_irq_source irq_source;
if (false == validate_irq_registration_params(int_params, ih))
return DAL_INVALID_IRQ_HANDLER_IDX;
handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
if (!handler_data) {
DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
return DAL_INVALID_IRQ_HANDLER_IDX;
}
memset(handler_data, 0, sizeof(*handler_data));
init_handler_common_data(&handler_data->hcd, ih, handler_args,
&adev->dm);
irq_source = int_params->irq_source;
handler_data->irq_source = irq_source;
/* Lock the list, add the handler. */
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
switch (int_params->int_context) {
case INTERRUPT_HIGH_IRQ_CONTEXT:
hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
break;
case INTERRUPT_LOW_IRQ_CONTEXT:
default:
hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
break;
}
list_add_tail(&handler_data->hcd.list, hnd_list);
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
/* This pointer will be stored by code which requested interrupt
* registration.
* The same pointer will be needed in order to unregister the
* interrupt. */
DRM_DEBUG_KMS(
"DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
handler_data,
irq_source,
int_params->int_context);
return handler_data;
}
void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
enum dc_irq_source irq_source,
void *ih)
{
struct list_head *handler_list;
struct dc_interrupt_params int_params;
int i;
if (false == validate_irq_unregistration_params(irq_source, ih))
return;
memset(&int_params, 0, sizeof(int_params));
int_params.irq_source = irq_source;
for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
int_params.int_context = i;
handler_list = remove_irq_handler(adev, ih, &int_params);
if (handler_list != NULL)
break;
}
if (handler_list == NULL) {
/* If we got here, it means we searched all irq contexts
* for this irq source, but the handler was not found. */
DRM_ERROR(
"DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
ih, irq_source);
}
}
int amdgpu_dm_irq_init(struct amdgpu_device *adev)
{
int src;
struct irq_list_head *lh;
DRM_DEBUG_KMS("DM_IRQ\n");
spin_lock_init(&adev->dm.irq_handler_list_table_lock);
for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
/* low context handler list init */
lh = &adev->dm.irq_handler_list_low_tab[src];
INIT_LIST_HEAD(&lh->head);
INIT_WORK(&lh->work, dm_irq_work_func);
/* high context handler init */
INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
}
INIT_LIST_HEAD(&adev->dm.timer_handler_list);
/* allocate and initialize the workqueue for DM timer */
adev->dm.timer_workqueue = create_singlethread_workqueue(
"dm_timer_queue");
if (adev->dm.timer_workqueue == NULL) {
DRM_ERROR("DM_IRQ: unable to create timer queue!\n");
return -1;
}
return 0;
}
/* DM IRQ and timer resource release */
void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
{
int src;
struct irq_list_head *lh;
DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
/* The handler was removed from the table,
* it means it is safe to flush all the 'work'
* (because no code can schedule a new one). */
lh = &adev->dm.irq_handler_list_low_tab[src];
flush_work(&lh->work);
}
/* Cancel ALL timers and release handlers (if any). */
remove_timer_handler(adev, NULL);
/* Release the queue itself. */
destroy_workqueue(adev->dm.timer_workqueue);
}
int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
{
int src;
struct list_head *hnd_list_h;
struct list_head *hnd_list_l;
unsigned long irq_table_flags;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
DRM_DEBUG_KMS("DM_IRQ: suspend\n");
/**
* Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK
* will be disabled from manage_dm_interrupts on disable CRTC.
*/
for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
dc_interrupt_set(adev->dm.dc, src, false);
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
return 0;
}
int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
{
int src;
struct list_head *hnd_list_h, *hnd_list_l;
unsigned long irq_table_flags;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
DRM_DEBUG_KMS("DM_IRQ: early resume\n");
/* re-enable short pulse interrupts HW interrupt */
for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
dc_interrupt_set(adev->dm.dc, src, true);
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
return 0;
}
int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
{
int src;
struct list_head *hnd_list_h, *hnd_list_l;
unsigned long irq_table_flags;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
DRM_DEBUG_KMS("DM_IRQ: resume\n");
/**
* Renable HW interrupt for HPD and only since FLIP and VBLANK
* will be enabled from manage_dm_interrupts on enable CRTC.
*/
for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
dc_interrupt_set(adev->dm.dc, src, true);
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
return 0;
}
/**
* amdgpu_dm_irq_schedule_work - schedule all work items registered for the
* "irq_source".
*/
static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
enum dc_irq_source irq_source)
{
unsigned long irq_table_flags;
struct work_struct *work = NULL;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
if (work) {
if (!schedule_work(work))
DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
irq_source);
}
}
/** amdgpu_dm_irq_immediate_work
* Callback high irq work immediately, don't send to work queue
*/
static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
enum dc_irq_source irq_source)
{
struct amdgpu_dm_irq_handler_data *handler_data;
struct list_head *entry;
unsigned long irq_table_flags;
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
list_for_each(
entry,
&adev->dm.irq_handler_list_high_tab[irq_source]) {
handler_data =
list_entry(
entry,
struct amdgpu_dm_irq_handler_data,
hcd.list);
/* Call a subcomponent which registered for immediate
* interrupt notification */
handler_data->hcd.handler(handler_data->hcd.handler_arg);
}
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
}
/*
* amdgpu_dm_irq_handler
*
* Generic IRQ handler, calls all registered high irq work immediately, and
* schedules work for low irq
*/
static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
enum dc_irq_source src =
dc_interrupt_to_irq_source(
adev->dm.dc,
entry->src_id,
entry->src_data[0]);
dc_interrupt_ack(adev->dm.dc, src);
/* Call high irq work immediately */
amdgpu_dm_irq_immediate_work(adev, src);
/*Schedule low_irq work */
amdgpu_dm_irq_schedule_work(adev, src);
return 0;
}
static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
{
switch (type) {
case AMDGPU_HPD_1:
return DC_IRQ_SOURCE_HPD1;
case AMDGPU_HPD_2:
return DC_IRQ_SOURCE_HPD2;
case AMDGPU_HPD_3:
return DC_IRQ_SOURCE_HPD3;
case AMDGPU_HPD_4:
return DC_IRQ_SOURCE_HPD4;
case AMDGPU_HPD_5:
return DC_IRQ_SOURCE_HPD5;
case AMDGPU_HPD_6:
return DC_IRQ_SOURCE_HPD6;
default:
return DC_IRQ_SOURCE_INVALID;
}
}
static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
enum amdgpu_interrupt_state state)
{
enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
dc_interrupt_set(adev->dm.dc, src, st);
return 0;
}
static inline int dm_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned crtc_id,
enum amdgpu_interrupt_state state,
const enum irq_type dal_irq_type,
const char *func)
{
bool st;
enum dc_irq_source irq_source;
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
if (!acrtc) {
DRM_ERROR(
"%s: crtc is NULL at id :%d\n",
func,
crtc_id);
return 0;
}
irq_source = dal_irq_type + acrtc->otg_inst;
st = (state == AMDGPU_IRQ_STATE_ENABLE);
dc_interrupt_set(adev->dm.dc, irq_source, st);
return 0;
}
static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned crtc_id,
enum amdgpu_interrupt_state state)
{
return dm_irq_state(
adev,
source,
crtc_id,
state,
IRQ_TYPE_PFLIP,
__func__);
}
static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned crtc_id,
enum amdgpu_interrupt_state state)
{
return dm_irq_state(
adev,
source,
crtc_id,
state,
IRQ_TYPE_VBLANK,
__func__);
}
static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
.set = amdgpu_dm_set_crtc_irq_state,
.process = amdgpu_dm_irq_handler,
};
static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
.set = amdgpu_dm_set_pflip_irq_state,
.process = amdgpu_dm_irq_handler,
};
static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
.set = amdgpu_dm_set_hpd_irq_state,
.process = amdgpu_dm_irq_handler,
};
void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
{
adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
}
/*
* amdgpu_dm_hpd_init - hpd setup callback.
*
* @adev: amdgpu_device pointer
*
* Setup the hpd pins used by the card (evergreen+).
* Enable the pin, set the polarity, and enable the hpd interrupts.
*/
void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
{
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
dc_interrupt_set(adev->dm.dc,
dc_link->irq_source_hpd,
true);
}
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
dc_interrupt_set(adev->dm.dc,
dc_link->irq_source_hpd_rx,
true);
}
}
}
/**
* amdgpu_dm_hpd_fini - hpd tear down callback.
*
* @adev: amdgpu_device pointer
*
* Tear down the hpd pins used by the card (evergreen+).
* Disable the hpd interrupts.
*/
void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
{
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
dc_interrupt_set(adev->dm.dc,
dc_link->irq_source_hpd_rx,
false);
}
}
}

102
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_DM_IRQ_H__
#define __AMDGPU_DM_IRQ_H__
#include "irq_types.h" /* DAL irq definitions */
/*
* Display Manager IRQ-related interfaces (for use by DAL).
*/
/**
* amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
*
* This function should be called exactly once - during DM initialization.
*
* Returns:
* 0 - success
* non-zero - error
*/
int amdgpu_dm_irq_init(struct amdgpu_device *adev);
/**
* amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
*
* This function should be called exactly once - during DM destruction.
*
*/
void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
/**
* amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
*
* @adev: AMD DRM device
* @int_params: parameters for the irq
* @ih: pointer to the irq hander function
* @handler_args: arguments which will be passed to ih
*
* Returns:
* IRQ Handler Index on success.
* NULL on failure.
*
* Cannot be called from an interrupt handler.
*/
void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
struct dc_interrupt_params *int_params,
void (*ih)(void *),
void *handler_args);
/**
* amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
* by amdgpu_dm_irq_register_interrupt().
*
* @adev: AMD DRM device.
* @ih_index: irq handler index which was returned by
* amdgpu_dm_irq_register_interrupt
*/
void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
enum dc_irq_source irq_source,
void *ih_index);
void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
/**
* amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
*
*/
int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
/**
* amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
* amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
*
*/
int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
#endif /* __AMDGPU_DM_IRQ_H__ */

446
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c Normal file
View File

@ -0,0 +1,446 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/version.h>
#include <drm/drm_atomic_helper.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_mst_types.h"
#include "dc.h"
#include "dm_helpers.h"
#include "dc_link_ddc.h"
/* #define TRACE_DPCD */
#ifdef TRACE_DPCD
#define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
static inline char *side_band_msg_type_to_str(uint32_t address)
{
static char str[10] = {0};
if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
strcpy(str, "DOWN_REQ");
else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
strcpy(str, "UP_REP");
else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
strcpy(str, "DOWN_REP");
else
strcpy(str, "UP_REQ");
return str;
}
static void log_dpcd(uint8_t type,
uint32_t address,
uint8_t *data,
uint32_t size,
bool res)
{
DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
(type == DP_AUX_NATIVE_READ) ||
(type == DP_AUX_I2C_READ) ?
"Read" : "Write",
address,
SIDE_BAND_MSG(address) ?
side_band_msg_type_to_str(address) : "Nop",
res ? "OK" : "Fail");
if (res) {
print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
}
}
#endif
static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
{
enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
I2C_MOT_TRUE : I2C_MOT_FALSE;
enum ddc_result res;
switch (msg->request & ~DP_AUX_I2C_MOT) {
case DP_AUX_NATIVE_READ:
res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
false,
I2C_MOT_UNDEF,
msg->address,
msg->buffer,
msg->size);
break;
case DP_AUX_NATIVE_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
false,
I2C_MOT_UNDEF,
msg->address,
msg->buffer,
msg->size);
break;
case DP_AUX_I2C_READ:
res = dal_ddc_service_read_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
true,
mot,
msg->address,
msg->buffer,
msg->size);
break;
case DP_AUX_I2C_WRITE:
res = dal_ddc_service_write_dpcd_data(
TO_DM_AUX(aux)->ddc_service,
true,
mot,
msg->address,
msg->buffer,
msg->size);
break;
default:
return 0;
}
#ifdef TRACE_DPCD
log_dpcd(msg->request,
msg->address,
msg->buffer,
msg->size,
r == DDC_RESULT_SUCESSFULL);
#endif
return msg->size;
}
static enum drm_connector_status
dm_dp_mst_detect(struct drm_connector *connector, bool force)
{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
struct amdgpu_dm_connector *master = aconnector->mst_port;
enum drm_connector_status status =
drm_dp_mst_detect_port(
connector,
&master->mst_mgr,
aconnector->port);
return status;
}
static void
dm_dp_mst_connector_destroy(struct drm_connector *connector)
{
struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
drm_encoder_cleanup(&amdgpu_encoder->base);
kfree(amdgpu_encoder);
drm_connector_cleanup(connector);
kfree(amdgpu_dm_connector);
}
static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
.detect = dm_dp_mst_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = dm_dp_mst_connector_destroy,
.reset = amdgpu_dm_connector_funcs_reset,
.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
.atomic_get_property = amdgpu_dm_connector_atomic_get_property
};
static int dm_connector_update_modes(struct drm_connector *connector,
struct edid *edid)
{
int ret;
ret = drm_add_edid_modes(connector, edid);
drm_edid_to_eld(connector, edid);
return ret;
}
static int dm_dp_mst_get_modes(struct drm_connector *connector)
{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
int ret = 0;
if (!aconnector)
return dm_connector_update_modes(connector, NULL);
if (!aconnector->edid) {
struct edid *edid;
struct dc_sink *dc_sink;
struct dc_sink_init_data init_params = {
.link = aconnector->dc_link,
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
if (!edid) {
drm_mode_connector_update_edid_property(
&aconnector->base,
NULL);
return ret;
}
aconnector->edid = edid;
dc_sink = dc_link_add_remote_sink(
aconnector->dc_link,
(uint8_t *)edid,
(edid->extensions + 1) * EDID_LENGTH,
&init_params);
dc_sink->priv = aconnector;
aconnector->dc_sink = dc_sink;
if (aconnector->dc_sink)
amdgpu_dm_add_sink_to_freesync_module(
connector, edid);
drm_mode_connector_update_edid_property(
&aconnector->base, edid);
}
ret = dm_connector_update_modes(connector, aconnector->edid);
return ret;
}
static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
{
struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
return &amdgpu_dm_connector->mst_encoder->base;
}
static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
.get_modes = dm_dp_mst_get_modes,
.mode_valid = amdgpu_dm_connector_mode_valid,
.best_encoder = dm_mst_best_encoder,
};
static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
{
drm_encoder_cleanup(encoder);
kfree(encoder);
}
static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
.destroy = amdgpu_dm_encoder_destroy,
};
static struct amdgpu_encoder *
dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
{
struct drm_device *dev = connector->base.dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder;
struct drm_encoder *encoder;
const struct drm_connector_helper_funcs *connector_funcs =
connector->base.helper_private;
struct drm_encoder *enc_master =
connector_funcs->best_encoder(&connector->base);
DRM_DEBUG_KMS("enc master is %p\n", enc_master);
amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
if (!amdgpu_encoder)
return NULL;
encoder = &amdgpu_encoder->base;
encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
drm_encoder_init(
dev,
&amdgpu_encoder->base,
&amdgpu_dm_encoder_funcs,
DRM_MODE_ENCODER_DPMST,
NULL);
drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
return amdgpu_encoder;
}
static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
const char *pathprop)
{
struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
struct drm_device *dev = master->base.dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
aconnector = to_amdgpu_dm_connector(connector);
if (aconnector->mst_port == master
&& !aconnector->port) {
DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n",
aconnector, connector->base.id, aconnector->mst_port);
aconnector->port = port;
drm_mode_connector_set_path_property(connector, pathprop);
drm_connector_list_iter_end(&conn_iter);
return &aconnector->base;
}
}
drm_connector_list_iter_end(&conn_iter);
aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
if (!aconnector)
return NULL;
connector = &aconnector->base;
aconnector->port = port;
aconnector->mst_port = master;
if (drm_connector_init(
dev,
connector,
&dm_dp_mst_connector_funcs,
DRM_MODE_CONNECTOR_DisplayPort)) {
kfree(aconnector);
return NULL;
}
drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
amdgpu_dm_connector_init_helper(
&adev->dm,
aconnector,
DRM_MODE_CONNECTOR_DisplayPort,
master->dc_link,
master->connector_id);
aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
/*
* TODO: understand why this one is needed
*/
drm_object_attach_property(
&connector->base,
dev->mode_config.path_property,
0);
drm_object_attach_property(
&connector->base,
dev->mode_config.tile_property,
0);
drm_mode_connector_set_path_property(connector, pathprop);
/*
* Initialize connector state before adding the connectror to drm and
* framebuffer lists
*/
amdgpu_dm_connector_funcs_reset(connector);
DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
aconnector, connector->base.id, aconnector->mst_port);
DRM_DEBUG_KMS(":%d\n", connector->base.id);
return connector;
}
static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_connector *connector)
{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
aconnector, connector->base.id, aconnector->mst_port);
aconnector->port = NULL;
if (aconnector->dc_sink) {
amdgpu_dm_remove_sink_from_freesync_module(connector);
dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL;
}
if (aconnector->edid) {
kfree(aconnector->edid);
aconnector->edid = NULL;
}
drm_mode_connector_update_edid_property(
&aconnector->base,
NULL);
}
static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
{
struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
struct drm_device *dev = master->base.dev;
drm_kms_helper_hotplug_event(dev);
}
static void dm_dp_mst_register_connector(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = dev->dev_private;
if (adev->mode_info.rfbdev)
drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
else
DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
drm_connector_register(connector);
}
static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
.add_connector = dm_dp_add_mst_connector,
.destroy_connector = dm_dp_destroy_mst_connector,
.hotplug = dm_dp_mst_hotplug,
.register_connector = dm_dp_mst_register_connector
};
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector)
{
aconnector->dm_dp_aux.aux.name = "dmdc";
aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
aconnector->mst_mgr.cbs = &dm_mst_cbs;
drm_dp_mst_topology_mgr_init(
&aconnector->mst_mgr,
dm->adev->ddev,
&aconnector->dm_dp_aux.aux,
16,
4,
aconnector->connector_id);
}

35
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h Normal file
View File

@ -0,0 +1,35 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_AMDGPU_DM_MST_TYPES_H__
#define __DAL_AMDGPU_DM_MST_TYPES_H__
struct amdgpu_display_manager;
struct amdgpu_dm_connector;
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector);
#endif

379
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c Normal file
View File

@ -0,0 +1,379 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/string.h>
#include <linux/acpi.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
#include "amdgpu_pm.h"
unsigned long long dm_get_timestamp(struct dc_context *ctx)
{
/* TODO: return actual timestamp */
return 0;
}
bool dm_write_persistent_data(struct dc_context *ctx,
const struct dc_sink *sink,
const char *module_name,
const char *key_name,
void *params,
unsigned int size,
struct persistent_data_flag *flag)
{
/*TODO implement*/
return false;
}
bool dm_read_persistent_data(struct dc_context *ctx,
const struct dc_sink *sink,
const char *module_name,
const char *key_name,
void *params,
unsigned int size,
struct persistent_data_flag *flag)
{
/*TODO implement*/
return false;
}
/**** power component interfaces ****/
bool dm_pp_pre_dce_clock_change(
struct dc_context *ctx,
struct dm_pp_gpu_clock_range *requested_state,
struct dm_pp_gpu_clock_range *actual_state)
{
/*TODO*/
return false;
}
bool dm_pp_apply_display_requirements(
const struct dc_context *ctx,
const struct dm_pp_display_configuration *pp_display_cfg)
{
struct amdgpu_device *adev = ctx->driver_context;
if (adev->pm.dpm_enabled) {
memset(&adev->pm.pm_display_cfg, 0,
sizeof(adev->pm.pm_display_cfg));
adev->pm.pm_display_cfg.cpu_cc6_disable =
pp_display_cfg->cpu_cc6_disable;
adev->pm.pm_display_cfg.cpu_pstate_disable =
pp_display_cfg->cpu_pstate_disable;
adev->pm.pm_display_cfg.cpu_pstate_separation_time =
pp_display_cfg->cpu_pstate_separation_time;
adev->pm.pm_display_cfg.nb_pstate_switch_disable =
pp_display_cfg->nb_pstate_switch_disable;
adev->pm.pm_display_cfg.num_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.num_path_including_non_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.min_core_set_clock =
pp_display_cfg->min_engine_clock_khz/10;
adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
adev->pm.pm_display_cfg.min_mem_set_clock =
pp_display_cfg->min_memory_clock_khz/10;
adev->pm.pm_display_cfg.multi_monitor_in_sync =
pp_display_cfg->all_displays_in_sync;
adev->pm.pm_display_cfg.min_vblank_time =
pp_display_cfg->avail_mclk_switch_time_us;
adev->pm.pm_display_cfg.display_clk =
pp_display_cfg->disp_clk_khz/10;
adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
adev->pm.pm_display_cfg.line_time_in_us =
pp_display_cfg->line_time_in_us;
adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
adev->pm.pm_display_cfg.crossfire_display_index = -1;
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
/* TODO: complete implementation of
* amd_powerplay_display_configuration_change().
* Follow example of:
* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
amd_powerplay_display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
/* TODO: replace by a separate call to 'apply display cfg'? */
amdgpu_pm_compute_clocks(adev);
}
return true;
}
bool dc_service_get_system_clocks_range(
const struct dc_context *ctx,
struct dm_pp_gpu_clock_range *sys_clks)
{
struct amdgpu_device *adev = ctx->driver_context;
/* Default values, in case PPLib is not compiled-in. */
sys_clks->mclk.max_khz = 800000;
sys_clks->mclk.min_khz = 800000;
sys_clks->sclk.max_khz = 600000;
sys_clks->sclk.min_khz = 300000;
if (adev->pm.dpm_enabled) {
sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false);
sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true);
sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false);
sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true);
}
return true;
}
static void get_default_clock_levels(
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *clks)
{
uint32_t disp_clks_in_khz[6] = {
300000, 400000, 496560, 626090, 685720, 757900 };
uint32_t sclks_in_khz[6] = {
300000, 360000, 423530, 514290, 626090, 720000 };
uint32_t mclks_in_khz[2] = { 333000, 800000 };
switch (clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, disp_clks_in_khz,
sizeof(disp_clks_in_khz));
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, sclks_in_khz,
sizeof(sclks_in_khz));
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
clks->num_levels = 2;
memmove(clks->clocks_in_khz, mclks_in_khz,
sizeof(mclks_in_khz));
break;
default:
clks->num_levels = 0;
break;
}
}
static enum amd_pp_clock_type dc_to_pp_clock_type(
enum dm_pp_clock_type dm_pp_clk_type)
{
enum amd_pp_clock_type amd_pp_clk_type = 0;
switch (dm_pp_clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
amd_pp_clk_type = amd_pp_disp_clock;
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
amd_pp_clk_type = amd_pp_sys_clock;
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
amd_pp_clk_type = amd_pp_mem_clock;
break;
default:
DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
dm_pp_clk_type);
break;
}
return amd_pp_clk_type;
}
static void pp_to_dc_clock_levels(
const struct amd_pp_clocks *pp_clks,
struct dm_pp_clock_levels *dc_clks,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->count,
DM_PP_MAX_CLOCK_LEVELS);
dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
dc_clks->num_levels = pp_clks->count;
DRM_INFO("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < dc_clks->num_levels; i++) {
DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
/* translate 10kHz to kHz */
dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
}
}
bool dm_pp_get_clock_levels_by_type(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *dc_clks)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct amd_pp_clocks pp_clks = { 0 };
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
if (amd_powerplay_get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
get_default_clock_levels(clk_type, dc_clks);
return true;
}
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
&validation_clks)) {
/* Error in pplib. Provide default values. */
DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
validation_clks.engine_max_clock = 72000;
validation_clks.memory_max_clock = 80000;
validation_clks.level = 0;
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
validation_clks.engine_max_clock);
DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
validation_clks.memory_max_clock);
DRM_INFO("DM_PPLIB: level : %d\n",
validation_clks.level);
/* Translate 10 kHz to kHz. */
validation_clks.engine_max_clock *= 10;
validation_clks.memory_max_clock *= 10;
/* Determine the highest non-boosted level from the Validation Clocks */
if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
/* This clock is higher the validation clock.
* Than means the previous one is the highest
* non-boosted one. */
DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
}
return true;
}
bool dm_pp_get_clock_levels_by_type_with_latency(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_latency *clk_level_info)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_get_clock_levels_by_type_with_voltage(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_voltage *clk_level_info)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_notify_wm_clock_changes(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_power_level_change_request(
const struct dc_context *ctx,
struct dm_pp_power_level_change_request *level_change_req)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_clock_for_voltage_request(
const struct dc_context *ctx,
struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_get_static_clocks(
const struct dc_context *ctx,
struct dm_pp_static_clock_info *static_clk_info)
{
/* TODO: to be implemented */
return false;
}
void dm_pp_get_funcs_rv(
struct dc_context *ctx,
struct pp_smu_funcs_rv *funcs)
{}
/**** end of power component interfaces ****/

33
drivers/gpu/drm/amd/display/dc/Makefile Normal file
View File

@ -0,0 +1,33 @@
#
# Makefile for Display Core (dc) component.
#
DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
ifdef CONFIG_DRM_AMD_DC_DCN1_0
DC_LIBS += dcn10 dml
endif
DC_LIBS += dce120
DC_LIBS += dce112
DC_LIBS += dce110
DC_LIBS += dce100
DC_LIBS += dce80
AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
include $(AMD_DC)
DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)

11
drivers/gpu/drm/amd/display/dc/basics/Makefile Normal file
View File

@ -0,0 +1,11 @@
#
# Makefile for the 'utils' sub-component of DAL.
# It provides the general basic services required by other DAL
# subcomponents.
BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
logger.o log_helpers.o vector.o
AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
AMD_DISPLAY_FILES += $(AMD_DAL_BASICS)

104
drivers/gpu/drm/amd/display/dc/basics/conversion.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#define DIVIDER 10000
/* S2D13 value in [-3.00...0.9999] */
#define S2D13_MIN (-3 * DIVIDER)
#define S2D13_MAX (3 * DIVIDER)
uint16_t fixed_point_to_int_frac(
struct fixed31_32 arg,
uint8_t integer_bits,
uint8_t fractional_bits)
{
int32_t numerator;
int32_t divisor = 1 << fractional_bits;
uint16_t result;
uint16_t d = (uint16_t)dal_fixed31_32_floor(
dal_fixed31_32_abs(
arg));
if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
numerator = (uint16_t)dal_fixed31_32_floor(
dal_fixed31_32_mul_int(
arg,
divisor));
else {
numerator = dal_fixed31_32_floor(
dal_fixed31_32_sub(
dal_fixed31_32_from_int(
1LL << integer_bits),
dal_fixed31_32_recip(
dal_fixed31_32_from_int(
divisor))));
}
if (numerator >= 0)
result = (uint16_t)numerator;
else
result = (uint16_t)(
(1 << (integer_bits + fractional_bits + 1)) + numerator);
if ((result != 0) && dal_fixed31_32_lt(
arg, dal_fixed31_32_zero))
result |= 1 << (integer_bits + fractional_bits);
return result;
}
/**
* convert_float_matrix
* This converts a double into HW register spec defined format S2D13.
* @param :
* @return None
*/
void convert_float_matrix(
uint16_t *matrix,
struct fixed31_32 *flt,
uint32_t buffer_size)
{
const struct fixed31_32 min_2_13 =
dal_fixed31_32_from_fraction(S2D13_MIN, DIVIDER);
const struct fixed31_32 max_2_13 =
dal_fixed31_32_from_fraction(S2D13_MAX, DIVIDER);
uint32_t i;
for (i = 0; i < buffer_size; ++i) {
uint32_t reg_value =
fixed_point_to_int_frac(
dal_fixed31_32_clamp(
flt[i],
min_2_13,
max_2_13),
2,
13);
matrix[i] = (uint16_t)reg_value;
}
}

46
drivers/gpu/drm/amd/display/dc/basics/conversion.h Normal file
View File

@ -0,0 +1,46 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_CONVERSION_H__
#define __DAL_CONVERSION_H__
#include "include/fixed31_32.h"
uint16_t fixed_point_to_int_frac(
struct fixed31_32 arg,
uint8_t integer_bits,
uint8_t fractional_bits);
void convert_float_matrix(
uint16_t *matrix,
struct fixed31_32 *flt,
uint32_t buffer_size);
static inline unsigned int log_2(unsigned int num)
{
return ilog2(num);
}
#endif

567
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c Normal file
View File

@ -0,0 +1,567 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/fixed31_32.h"
static inline uint64_t abs_i64(
int64_t arg)
{
if (arg > 0)
return (uint64_t)arg;
else
return (uint64_t)(-arg);
}
/*
* @brief
* result = dividend / divisor
* *remainder = dividend % divisor
*/
static inline uint64_t complete_integer_division_u64(
uint64_t dividend,
uint64_t divisor,
uint64_t *remainder)
{
uint64_t result;
ASSERT(divisor);
result = div64_u64_rem(dividend, divisor, remainder);
return result;
}
#define FRACTIONAL_PART_MASK \
((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
#define GET_INTEGER_PART(x) \
((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART)
#define GET_FRACTIONAL_PART(x) \
(FRACTIONAL_PART_MASK & (x))
struct fixed31_32 dal_fixed31_32_from_fraction(
int64_t numerator,
int64_t denominator)
{
struct fixed31_32 res;
bool arg1_negative = numerator < 0;
bool arg2_negative = denominator < 0;
uint64_t arg1_value = arg1_negative ? -numerator : numerator;
uint64_t arg2_value = arg2_negative ? -denominator : denominator;
uint64_t remainder;
/* determine integer part */
uint64_t res_value = complete_integer_division_u64(
arg1_value, arg2_value, &remainder);
ASSERT(res_value <= LONG_MAX);
/* determine fractional part */
{
uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
do {
remainder <<= 1;
res_value <<= 1;
if (remainder >= arg2_value) {
res_value |= 1;
remainder -= arg2_value;
}
} while (--i != 0);
}
/* round up LSB */
{
uint64_t summand = (remainder << 1) >= arg2_value;
ASSERT(res_value <= LLONG_MAX - summand);
res_value += summand;
}
res.value = (int64_t)res_value;
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
return res;
}
struct fixed31_32 dal_fixed31_32_from_int_nonconst(
int64_t arg)
{
struct fixed31_32 res;
ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
return res;
}
struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
uint8_t shift)
{
struct fixed31_32 res;
ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
res.value = arg.value << shift;
return res;
}
struct fixed31_32 dal_fixed31_32_add(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
{
struct fixed31_32 res;
ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
res.value = arg1.value + arg2.value;
return res;
}
struct fixed31_32 dal_fixed31_32_sub(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
{
struct fixed31_32 res;
ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
res.value = arg1.value - arg2.value;
return res;
}
struct fixed31_32 dal_fixed31_32_mul(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
{
struct fixed31_32 res;
bool arg1_negative = arg1.value < 0;
bool arg2_negative = arg2.value < 0;
uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
uint64_t tmp;
res.value = arg1_int * arg2_int;
ASSERT(res.value <= LONG_MAX);
res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
tmp = arg1_int * arg2_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg2_int * arg1_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg1_fra * arg2_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
return res;
}
struct fixed31_32 dal_fixed31_32_sqr(
struct fixed31_32 arg)
{
struct fixed31_32 res;
uint64_t arg_value = abs_i64(arg.value);
uint64_t arg_int = GET_INTEGER_PART(arg_value);
uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
uint64_t tmp;
res.value = arg_int * arg_int;
ASSERT(res.value <= LONG_MAX);
res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
tmp = arg_int * arg_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg_fra * arg_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
res.value += tmp;
return res;
}
struct fixed31_32 dal_fixed31_32_recip(
struct fixed31_32 arg)
{
/*
* @note
* Good idea to use Newton's method
*/
ASSERT(arg.value);
return dal_fixed31_32_from_fraction(
dal_fixed31_32_one.value,
arg.value);
}
struct fixed31_32 dal_fixed31_32_sinc(
struct fixed31_32 arg)
{
struct fixed31_32 square;
struct fixed31_32 res = dal_fixed31_32_one;
int32_t n = 27;
struct fixed31_32 arg_norm = arg;
if (dal_fixed31_32_le(
dal_fixed31_32_two_pi,
dal_fixed31_32_abs(arg))) {
arg_norm = dal_fixed31_32_sub(
arg_norm,
dal_fixed31_32_mul_int(
dal_fixed31_32_two_pi,
(int32_t)div64_s64(
arg_norm.value,
dal_fixed31_32_two_pi.value)));
}
square = dal_fixed31_32_sqr(arg_norm);
do {
res = dal_fixed31_32_sub(
dal_fixed31_32_one,
dal_fixed31_32_div_int(
dal_fixed31_32_mul(
square,
res),
n * (n - 1)));
n -= 2;
} while (n > 2);
if (arg.value != arg_norm.value)
res = dal_fixed31_32_div(
dal_fixed31_32_mul(res, arg_norm),
arg);
return res;
}
struct fixed31_32 dal_fixed31_32_sin(
struct fixed31_32 arg)
{
return dal_fixed31_32_mul(
arg,
dal_fixed31_32_sinc(arg));
}
struct fixed31_32 dal_fixed31_32_cos(
struct fixed31_32 arg)
{
/* TODO implement argument normalization */
const struct fixed31_32 square = dal_fixed31_32_sqr(arg);
struct fixed31_32 res = dal_fixed31_32_one;
int32_t n = 26;
do {
res = dal_fixed31_32_sub(
dal_fixed31_32_one,
dal_fixed31_32_div_int(
dal_fixed31_32_mul(
square,
res),
n * (n - 1)));
n -= 2;
} while (n != 0);
return res;
}
/*
* @brief
* result = exp(arg),
* where abs(arg) < 1
*
* Calculated as Taylor series.
*/
static struct fixed31_32 fixed31_32_exp_from_taylor_series(
struct fixed31_32 arg)
{
uint32_t n = 9;
struct fixed31_32 res = dal_fixed31_32_from_fraction(
n + 2,
n + 1);
/* TODO find correct res */
ASSERT(dal_fixed31_32_lt(arg, dal_fixed31_32_one));
do
res = dal_fixed31_32_add(
dal_fixed31_32_one,
dal_fixed31_32_div_int(
dal_fixed31_32_mul(
arg,
res),
n));
while (--n != 1);
return dal_fixed31_32_add(
dal_fixed31_32_one,
dal_fixed31_32_mul(
arg,
res));
}
struct fixed31_32 dal_fixed31_32_exp(
struct fixed31_32 arg)
{
/*
* @brief
* Main equation is:
* exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r),
* where m = round(x / ln(2)), r = x - m * ln(2)
*/
if (dal_fixed31_32_le(
dal_fixed31_32_ln2_div_2,
dal_fixed31_32_abs(arg))) {
int32_t m = dal_fixed31_32_round(
dal_fixed31_32_div(
arg,
dal_fixed31_32_ln2));
struct fixed31_32 r = dal_fixed31_32_sub(
arg,
dal_fixed31_32_mul_int(
dal_fixed31_32_ln2,
m));
ASSERT(m != 0);
ASSERT(dal_fixed31_32_lt(
dal_fixed31_32_abs(r),
dal_fixed31_32_one));
if (m > 0)
return dal_fixed31_32_shl(
fixed31_32_exp_from_taylor_series(r),
(uint8_t)m);
else
return dal_fixed31_32_div_int(
fixed31_32_exp_from_taylor_series(r),
1LL << -m);
} else if (arg.value != 0)
return fixed31_32_exp_from_taylor_series(arg);
else
return dal_fixed31_32_one;
}
struct fixed31_32 dal_fixed31_32_log(
struct fixed31_32 arg)
{
struct fixed31_32 res = dal_fixed31_32_neg(dal_fixed31_32_one);
/* TODO improve 1st estimation */
struct fixed31_32 error;
ASSERT(arg.value > 0);
/* TODO if arg is negative, return NaN */
/* TODO if arg is zero, return -INF */
do {
struct fixed31_32 res1 = dal_fixed31_32_add(
dal_fixed31_32_sub(
res,
dal_fixed31_32_one),
dal_fixed31_32_div(
arg,
dal_fixed31_32_exp(res)));
error = dal_fixed31_32_sub(
res,
res1);
res = res1;
/* TODO determine max_allowed_error based on quality of exp() */
} while (abs_i64(error.value) > 100ULL);
return res;
}
struct fixed31_32 dal_fixed31_32_pow(
struct fixed31_32 arg1,
struct fixed31_32 arg2)
{
return dal_fixed31_32_exp(
dal_fixed31_32_mul(
dal_fixed31_32_log(arg1),
arg2));
}
int32_t dal_fixed31_32_floor(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
}
int32_t dal_fixed31_32_round(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
const int64_t summand = dal_fixed31_32_half.value;
ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
}
int32_t dal_fixed31_32_ceil(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
const int64_t summand = dal_fixed31_32_one.value -
dal_fixed31_32_epsilon.value;
ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
}
/* this function is a generic helper to translate fixed point value to
* specified integer format that will consist of integer_bits integer part and
* fractional_bits fractional part. For example it is used in
* dal_fixed31_32_u2d19 to receive 2 bits integer part and 19 bits fractional
* part in 32 bits. It is used in hw programming (scaler)
*/
static inline uint32_t ux_dy(
int64_t value,
uint32_t integer_bits,
uint32_t fractional_bits)
{
/* 1. create mask of integer part */
uint32_t result = (1 << integer_bits) - 1;
/* 2. mask out fractional part */
uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
/* 3. shrink fixed point integer part to be of integer_bits width*/
result &= GET_INTEGER_PART(value);
/* 4. make space for fractional part to be filled in after integer */
result <<= fractional_bits;
/* 5. shrink fixed point fractional part to of fractional_bits width*/
fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits;
/* 6. merge the result */
return result | fractional_part;
}
uint32_t dal_fixed31_32_u2d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 2, 19);
}
uint32_t dal_fixed31_32_u0d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 0, 19);
}

161
drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c Normal file
View File

@ -0,0 +1,161 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/fixed32_32.h"
static uint64_t u64_div(uint64_t n, uint64_t d)
{
uint32_t i = 0;
uint64_t r;
uint64_t q = div64_u64_rem(n, d, &r);
for (i = 0; i < 32; ++i) {
uint64_t sbit = q & (1ULL<<63);
r <<= 1;
r |= sbit ? 1 : 0;
q <<= 1;
if (r >= d) {
r -= d;
q |= 1;
}
}
if (2*r >= d)
q += 1;
return q;
}
struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d)
{
struct fixed32_32 fx;
fx.value = u64_div((uint64_t)n << 32, (uint64_t)d << 32);
return fx;
}
struct fixed32_32 dal_fixed32_32_add(
struct fixed32_32 lhs,
struct fixed32_32 rhs)
{
struct fixed32_32 fx = {lhs.value + rhs.value};
ASSERT(fx.value >= rhs.value);
return fx;
}
struct fixed32_32 dal_fixed32_32_add_int(struct fixed32_32 lhs, uint32_t rhs)
{
struct fixed32_32 fx = {lhs.value + ((uint64_t)rhs << 32)};
ASSERT(fx.value >= (uint64_t)rhs << 32);
return fx;
}
struct fixed32_32 dal_fixed32_32_sub(
struct fixed32_32 lhs,
struct fixed32_32 rhs)
{
struct fixed32_32 fx;
ASSERT(lhs.value >= rhs.value);
fx.value = lhs.value - rhs.value;
return fx;
}
struct fixed32_32 dal_fixed32_32_sub_int(struct fixed32_32 lhs, uint32_t rhs)
{
struct fixed32_32 fx;
ASSERT(lhs.value >= ((uint64_t)rhs<<32));
fx.value = lhs.value - ((uint64_t)rhs<<32);
return fx;
}
struct fixed32_32 dal_fixed32_32_mul(
struct fixed32_32 lhs,
struct fixed32_32 rhs)
{
struct fixed32_32 fx;
uint64_t lhs_int = lhs.value>>32;
uint64_t lhs_frac = (uint32_t)lhs.value;
uint64_t rhs_int = rhs.value>>32;
uint64_t rhs_frac = (uint32_t)rhs.value;
uint64_t ahbh = lhs_int * rhs_int;
uint64_t ahbl = lhs_int * rhs_frac;
uint64_t albh = lhs_frac * rhs_int;
uint64_t albl = lhs_frac * rhs_frac;
ASSERT((ahbh>>32) == 0);
fx.value = (ahbh<<32) + ahbl + albh + (albl>>32);
return fx;
}
struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
{
struct fixed32_32 fx;
uint64_t lhsi = (lhs.value>>32) * (uint64_t)rhs;
uint64_t lhsf;
ASSERT((lhsi>>32) == 0);
lhsf = ((uint32_t)lhs.value) * (uint64_t)rhs;
ASSERT((lhsi<<32) + lhsf >= lhsf);
fx.value = (lhsi<<32) + lhsf;
return fx;
}
struct fixed32_32 dal_fixed32_32_div(
struct fixed32_32 lhs,
struct fixed32_32 rhs)
{
struct fixed32_32 fx;
fx.value = u64_div(lhs.value, rhs.value);
return fx;
}
struct fixed32_32 dal_fixed32_32_div_int(struct fixed32_32 lhs, uint32_t rhs)
{
struct fixed32_32 fx;
fx.value = u64_div(lhs.value, (uint64_t)rhs << 32);
return fx;
}
uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
{
ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
}
uint32_t dal_fixed32_32_round(struct fixed32_32 v)
{
ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
return (v.value + (1ULL<<31))>>32;
}

75
drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c Normal file
View File

@ -0,0 +1,75 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/grph_object_id.h"
static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
{
bool rc = true;
switch (id.type) {
case OBJECT_TYPE_UNKNOWN:
rc = false;
break;
case OBJECT_TYPE_GPU:
case OBJECT_TYPE_ENGINE:
/* do NOT check for id.id == 0 */
if (id.enum_id == ENUM_ID_UNKNOWN)
rc = false;
break;
default:
if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
rc = false;
break;
}
return rc;
}
bool dal_graphics_object_id_is_equal(
struct graphics_object_id id1,
struct graphics_object_id id2)
{
if (false == dal_graphics_object_id_is_valid(id1)) {
dm_output_to_console(
"%s: Warning: comparing invalid object 'id1'!\n", __func__);
return false;
}
if (false == dal_graphics_object_id_is_valid(id2)) {
dm_output_to_console(
"%s: Warning: comparing invalid object 'id2'!\n", __func__);
return false;
}
if (id1.id == id2.id && id1.enum_id == id2.enum_id
&& id1.type == id2.type)
return true;
return false;
}

102
drivers/gpu/drm/amd/display/dc/basics/log_helpers.c Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "core_types.h"
#include "logger.h"
#include "include/logger_interface.h"
#include "dm_helpers.h"
#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
struct dc_signal_type_info {
enum signal_type type;
char name[MAX_NAME_LEN];
};
static const struct dc_signal_type_info signal_type_info_tbl[] = {
{SIGNAL_TYPE_NONE, "NC"},
{SIGNAL_TYPE_DVI_SINGLE_LINK, "DVI"},
{SIGNAL_TYPE_DVI_DUAL_LINK, "DDVI"},
{SIGNAL_TYPE_HDMI_TYPE_A, "HDMIA"},
{SIGNAL_TYPE_LVDS, "LVDS"},
{SIGNAL_TYPE_RGB, "VGA"},
{SIGNAL_TYPE_DISPLAY_PORT, "DP"},
{SIGNAL_TYPE_DISPLAY_PORT_MST, "MST"},
{SIGNAL_TYPE_EDP, "eDP"},
{SIGNAL_TYPE_VIRTUAL, "Virtual"}
};
void dc_conn_log(struct dc_context *ctx,
const struct dc_link *link,
uint8_t *hex_data,
int hex_data_count,
enum dc_log_type event,
const char *msg,
...)
{
int i;
va_list args;
struct log_entry entry = { 0 };
enum signal_type signal;
if (link->local_sink)
signal = link->local_sink->sink_signal;
else
signal = link->connector_signal;
if (link->type == dc_connection_mst_branch)
signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
dm_logger_open(ctx->logger, &entry, event);
for (i = 0; i < NUM_ELEMENTS(signal_type_info_tbl); i++)
if (signal == signal_type_info_tbl[i].type)
break;
dm_logger_append(&entry, "[%s][ConnIdx:%d] ",
signal_type_info_tbl[i].name,
link->link_index);
va_start(args, msg);
entry.buf_offset += dm_log_to_buffer(
&entry.buf[entry.buf_offset],
LOG_MAX_LINE_SIZE - entry.buf_offset,
msg, args);
if (entry.buf[strlen(entry.buf) - 1] == '\n') {
entry.buf[strlen(entry.buf) - 1] = '\0';
entry.buf_offset--;
}
if (hex_data)
for (i = 0; i < hex_data_count; i++)
dm_logger_append(&entry, "%2.2X ", hex_data[i]);
dm_logger_append(&entry, "^\n");
dm_helpers_dc_conn_log(ctx, &entry, event);
dm_logger_close(&entry);
va_end(args);
}

397
drivers/gpu/drm/amd/display/dc/basics/logger.c Normal file
View File

@ -0,0 +1,397 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/logger_interface.h"
#include "logger.h"
#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_ERROR, "Error"},
{LOG_WARNING, "Warning"},
{LOG_DEBUG, "Debug"},
{LOG_DC, "DC_Interface"},
{LOG_SURFACE, "Surface"},
{LOG_HW_HOTPLUG, "HW_Hotplug"},
{LOG_HW_LINK_TRAINING, "HW_LKTN"},
{LOG_HW_SET_MODE, "HW_Mode"},
{LOG_HW_RESUME_S3, "HW_Resume"},
{LOG_HW_AUDIO, "HW_Audio"},
{LOG_HW_HPD_IRQ, "HW_HPDIRQ"},
{LOG_MST, "MST"},
{LOG_SCALER, "Scaler"},
{LOG_BIOS, "BIOS"},
{LOG_BANDWIDTH_CALCS, "BWCalcs"},
{LOG_BANDWIDTH_VALIDATION, "BWValidation"},
{LOG_I2C_AUX, "I2C_AUX"},
{LOG_SYNC, "Sync"},
{LOG_BACKLIGHT, "Backlight"},
{LOG_FEATURE_OVERRIDE, "Override"},
{LOG_DETECTION_EDID_PARSER, "Edid"},
{LOG_DETECTION_DP_CAPS, "DP_Caps"},
{LOG_RESOURCE, "Resource"},
{LOG_DML, "DML"},
{LOG_EVENT_MODE_SET, "Mode"},
{LOG_EVENT_DETECTION, "Detect"},
{LOG_EVENT_LINK_TRAINING, "LKTN"},
{LOG_EVENT_LINK_LOSS, "LinkLoss"},
{LOG_EVENT_UNDERFLOW, "Underflow"},
{LOG_IF_TRACE, "InterfaceTrace"},
{LOG_DTN, "DTN"}
};
/* ----------- Object init and destruction ----------- */
static bool construct(struct dc_context *ctx, struct dal_logger *logger,
uint32_t log_mask)
{
/* malloc buffer and init offsets */
logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char),
GFP_KERNEL);
if (!logger->log_buffer)
return false;
/* Initialize both offsets to start of buffer (empty) */
logger->buffer_read_offset = 0;
logger->buffer_write_offset = 0;
logger->open_count = 0;
logger->flags.bits.ENABLE_CONSOLE = 1;
logger->flags.bits.ENABLE_BUFFER = 0;
logger->ctx = ctx;
logger->mask = log_mask;
return true;
}
static void destruct(struct dal_logger *logger)
{
if (logger->log_buffer) {
kfree(logger->log_buffer);
logger->log_buffer = NULL;
}
}
struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask)
{
/* malloc struct */
struct dal_logger *logger = kzalloc(sizeof(struct dal_logger),
GFP_KERNEL);
if (!logger)
return NULL;
if (!construct(ctx, logger, log_mask)) {
kfree(logger);
return NULL;
}
return logger;
}
uint32_t dal_logger_destroy(struct dal_logger **logger)
{
if (logger == NULL || *logger == NULL)
return 1;
destruct(*logger);
kfree(*logger);
*logger = NULL;
return 0;
}
/* ------------------------------------------------------------------------ */
static bool dal_logger_should_log(
struct dal_logger *logger,
enum dc_log_type log_type)
{
if (logger->mask & (1 << log_type))
return true;
return false;
}
static void log_to_debug_console(struct log_entry *entry)
{
struct dal_logger *logger = entry->logger;
if (logger->flags.bits.ENABLE_CONSOLE == 0)
return;
if (entry->buf_offset) {
switch (entry->type) {
case LOG_ERROR:
dm_error("%s", entry->buf);
break;
default:
dm_output_to_console("%s", entry->buf);
break;
}
}
}
/* Print everything unread existing in log_buffer to debug console*/
void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn)
{
char *string_start = &logger->log_buffer[logger->buffer_read_offset];
if (should_warn)
dm_output_to_console(
"---------------- FLUSHING LOG BUFFER ----------------\n");
while (logger->buffer_read_offset < logger->buffer_write_offset) {
if (logger->log_buffer[logger->buffer_read_offset] == '\0') {
dm_output_to_console("%s", string_start);
string_start = logger->log_buffer + logger->buffer_read_offset + 1;
}
logger->buffer_read_offset++;
}
if (should_warn)
dm_output_to_console(
"-------------- END FLUSHING LOG BUFFER --------------\n\n");
}
static void log_to_internal_buffer(struct log_entry *entry)
{
uint32_t size = entry->buf_offset;
struct dal_logger *logger = entry->logger;
if (logger->flags.bits.ENABLE_BUFFER == 0)
return;
if (logger->log_buffer == NULL)
return;
if (size > 0 && size < logger->log_buffer_size) {
int buffer_space = logger->log_buffer_size -
logger->buffer_write_offset;
if (logger->buffer_write_offset == logger->buffer_read_offset) {
/* Buffer is empty, start writing at beginning */
buffer_space = logger->log_buffer_size;
logger->buffer_write_offset = 0;
logger->buffer_read_offset = 0;
}
if (buffer_space > size) {
/* No wrap around, copy 'size' bytes
* from 'entry->buf' to 'log_buffer'
*/
memmove(logger->log_buffer +
logger->buffer_write_offset,
entry->buf, size);
logger->buffer_write_offset += size;
} else {
/* Not enough room remaining, we should flush
* existing logs */
/* Flush existing unread logs to console */
dm_logger_flush_buffer(logger, true);
/* Start writing to beginning of buffer */
memmove(logger->log_buffer, entry->buf, size);
logger->buffer_write_offset = size;
logger->buffer_read_offset = 0;
}
}
}
static void log_heading(struct log_entry *entry)
{
int j;
for (j = 0; j < NUM_ELEMENTS(log_type_info_tbl); j++) {
const struct dc_log_type_info *info = &log_type_info_tbl[j];
if (info->type == entry->type)
dm_logger_append(entry, "[%s]\t", info->name);
}
}
static void append_entry(
struct log_entry *entry,
char *buffer,
uint32_t buf_size)
{
if (!entry->buf ||
entry->buf_offset + buf_size > entry->max_buf_bytes
) {
BREAK_TO_DEBUGGER();
return;
}
/* Todo: check if off by 1 byte due to \0 anywhere */
memmove(entry->buf + entry->buf_offset, buffer, buf_size);
entry->buf_offset += buf_size;
}
/* ------------------------------------------------------------------------ */
/* Warning: Be careful that 'msg' is null terminated and the total size is
* less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
*/
void dm_logger_write(
struct dal_logger *logger,
enum dc_log_type log_type,
const char *msg,
...)
{
if (logger && dal_logger_should_log(logger, log_type)) {
uint32_t size;
va_list args;
char buffer[LOG_MAX_LINE_SIZE];
struct log_entry entry;
va_start(args, msg);
entry.logger = logger;
entry.buf = buffer;
entry.buf_offset = 0;
entry.max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
entry.type = log_type;
log_heading(&entry);
size = dm_log_to_buffer(
buffer, LOG_MAX_LINE_SIZE - 1, msg, args);
buffer[entry.buf_offset + size] = '\0';
entry.buf_offset += size + 1;
/* --Flush log_entry buffer-- */
/* print to kernel console */
log_to_debug_console(&entry);
/* log internally for dsat */
log_to_internal_buffer(&entry);
va_end(args);
}
}
/* Same as dm_logger_write, except without open() and close(), which must
* be done separately.
*/
void dm_logger_append(
struct log_entry *entry,
const char *msg,
...)
{
struct dal_logger *logger;
if (!entry) {
BREAK_TO_DEBUGGER();
return;
}
logger = entry->logger;
if (logger && logger->open_count > 0 &&
dal_logger_should_log(logger, entry->type)) {
uint32_t size;
va_list args;
char buffer[LOG_MAX_LINE_SIZE];
va_start(args, msg);
size = dm_log_to_buffer(
buffer, LOG_MAX_LINE_SIZE, msg, args);
if (size < LOG_MAX_LINE_SIZE - 1) {
append_entry(entry, buffer, size);
} else {
append_entry(entry, "LOG_ERROR, line too long\n", 27);
}
va_end(args);
}
}
void dm_logger_open(
struct dal_logger *logger,
struct log_entry *entry, /* out */
enum dc_log_type log_type)
{
if (!entry) {
BREAK_TO_DEBUGGER();
return;
}
entry->type = log_type;
entry->logger = logger;
entry->buf = kzalloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char),
GFP_KERNEL);
entry->buf_offset = 0;
entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
logger->open_count++;
log_heading(entry);
}
void dm_logger_close(struct log_entry *entry)
{
struct dal_logger *logger = entry->logger;
if (logger && logger->open_count > 0) {
logger->open_count--;
} else {
BREAK_TO_DEBUGGER();
goto cleanup;
}
/* --Flush log_entry buffer-- */
/* print to kernel console */
log_to_debug_console(entry);
/* log internally for dsat */
log_to_internal_buffer(entry);
/* TODO: Write end heading */
cleanup:
if (entry->buf) {
kfree(entry->buf);
entry->buf = NULL;
entry->buf_offset = 0;
entry->max_buf_bytes = 0;
}
}

30
drivers/gpu/drm/amd/display/dc/basics/logger.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_LOGGER_H__
#define __DAL_LOGGER_H__
#endif /* __DAL_LOGGER_H__ */

307
drivers/gpu/drm/amd/display/dc/basics/vector.c Normal file
View File

@ -0,0 +1,307 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/vector.h"
bool dal_vector_construct(
struct vector *vector,
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size)
{
vector->container = NULL;
if (!struct_size || !capacity) {
/* Container must be non-zero size*/
BREAK_TO_DEBUGGER();
return false;
}
vector->container = kzalloc(struct_size * capacity, GFP_KERNEL);
if (vector->container == NULL)
return false;
vector->capacity = capacity;
vector->struct_size = struct_size;
vector->count = 0;
vector->ctx = ctx;
return true;
}
bool dal_vector_presized_costruct(
struct vector *vector,
struct dc_context *ctx,
uint32_t count,
void *initial_value,
uint32_t struct_size)
{
uint32_t i;
vector->container = NULL;
if (!struct_size || !count) {
/* Container must be non-zero size*/
BREAK_TO_DEBUGGER();
return false;
}
vector->container = kzalloc(struct_size * count, GFP_KERNEL);
if (vector->container == NULL)
return false;
/* If caller didn't supply initial value then the default
* of all zeros is expected, which is exactly what dal_alloc()
* initialises the memory to. */
if (NULL != initial_value) {
for (i = 0; i < count; ++i)
memmove(
vector->container + i * struct_size,
initial_value,
struct_size);
}
vector->capacity = count;
vector->struct_size = struct_size;
vector->count = count;
return true;
}
struct vector *dal_vector_presized_create(
struct dc_context *ctx,
uint32_t size,
void *initial_value,
uint32_t struct_size)
{
struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL);
if (vector == NULL)
return NULL;
if (dal_vector_presized_costruct(
vector, ctx, size, initial_value, struct_size))
return vector;
BREAK_TO_DEBUGGER();
kfree(vector);
return NULL;
}
struct vector *dal_vector_create(
struct dc_context *ctx,
uint32_t capacity,
uint32_t struct_size)
{
struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL);
if (vector == NULL)
return NULL;
if (dal_vector_construct(vector, ctx, capacity, struct_size))
return vector;
BREAK_TO_DEBUGGER();
kfree(vector);
return NULL;
}
void dal_vector_destruct(
struct vector *vector)
{
kfree(vector->container);
vector->count = 0;
vector->capacity = 0;
}
void dal_vector_destroy(
struct vector **vector)
{
if (vector == NULL || *vector == NULL)
return;
dal_vector_destruct(*vector);
kfree(*vector);
*vector = NULL;
}
uint32_t dal_vector_get_count(
const struct vector *vector)
{
return vector->count;
}
void *dal_vector_at_index(
const struct vector *vector,
uint32_t index)
{
if (vector->container == NULL || index >= vector->count)
return NULL;
return vector->container + (index * vector->struct_size);
}
bool dal_vector_remove_at_index(
struct vector *vector,
uint32_t index)
{
if (index >= vector->count)
return false;
if (index != vector->count - 1)
memmove(
vector->container + (index * vector->struct_size),
vector->container + ((index + 1) * vector->struct_size),
(vector->count - index - 1) * vector->struct_size);
vector->count -= 1;
return true;
}
void dal_vector_set_at_index(
const struct vector *vector,
const void *what,
uint32_t index)
{
void *where = dal_vector_at_index(vector, index);
if (!where) {
BREAK_TO_DEBUGGER();
return;
}
memmove(
where,
what,
vector->struct_size);
}
static inline uint32_t calc_increased_capacity(
uint32_t old_capacity)
{
return old_capacity * 2;
}
bool dal_vector_insert_at(
struct vector *vector,
const void *what,
uint32_t position)
{
uint8_t *insert_address;
if (vector->count == vector->capacity) {
if (!dal_vector_reserve(
vector,
calc_increased_capacity(vector->capacity)))
return false;
}
insert_address = vector->container + (vector->struct_size * position);
if (vector->count && position < vector->count)
memmove(
insert_address + vector->struct_size,
insert_address,
vector->struct_size * (vector->count - position));
memmove(
insert_address,
what,
vector->struct_size);
vector->count++;
return true;
}
bool dal_vector_append(
struct vector *vector,
const void *item)
{
return dal_vector_insert_at(vector, item, vector->count);
}
struct vector *dal_vector_clone(
const struct vector *vector)
{
struct vector *vec_cloned;
uint32_t count;
/* create new vector */
count = dal_vector_get_count(vector);
if (count == 0)
/* when count is 0 we still want to create clone of the vector
*/
vec_cloned = dal_vector_create(
vector->ctx,
vector->capacity,
vector->struct_size);
else
/* Call "presized create" version, independently of how the
* original vector was created.
* The owner of original vector must know how to treat the new
* vector - as "presized" or as "regular".
* But from vector point of view it doesn't matter. */
vec_cloned = dal_vector_presized_create(vector->ctx, count,
NULL,/* no initial value */
vector->struct_size);
if (NULL == vec_cloned) {
BREAK_TO_DEBUGGER();
return NULL;
}
/* copy vector's data */
memmove(vec_cloned->container, vector->container,
vec_cloned->struct_size * vec_cloned->capacity);
return vec_cloned;
}
uint32_t dal_vector_capacity(const struct vector *vector)
{
return vector->capacity;
}
bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
{
void *new_container;
if (capacity <= vector->capacity)
return true;
new_container = krealloc(vector->container,
capacity * vector->struct_size, GFP_KERNEL);
if (new_container) {
vector->container = new_container;
vector->capacity = capacity;
return true;
}
return false;
}
void dal_vector_clear(struct vector *vector)
{
vector->count = 0;
}

27
drivers/gpu/drm/amd/display/dc/bios/Makefile Normal file
View File

@ -0,0 +1,27 @@
#
# Makefile for the 'bios' sub-component of DAL.
# It provides the parsing and executing controls for atom bios image.
BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o bios_parser_common.o
BIOS += command_table2.o command_table_helper2.o bios_parser2.o
AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
###############################################################################
# DCE 8x
###############################################################################
# All DCE8.x are derived from DCE8.0, so 8.0 MUST be defined if ANY of
# DCE8.x is compiled.
AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o
###############################################################################
# DCE 11x
###############################################################################
AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o

3871
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c Normal file
View File

File diff suppressed because it is too large Load Diff

33
drivers/gpu/drm/amd/display/dc/bios/bios_parser.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_H__
#define __DAL_BIOS_PARSER_H__
struct dc_bios *bios_parser_create(
struct bp_init_data *init,
enum dce_version dce_version);
#endif

1934
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c Normal file
View File

File diff suppressed because it is too large Load Diff

33
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER2_H__
#define __DAL_BIOS_PARSER2_H__
struct dc_bios *firmware_parser_create(
struct bp_init_data *init,
enum dce_version dce_version);
#endif

288
drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c Normal file
View File

@ -0,0 +1,288 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "bios_parser_common.h"
#include "include/grph_object_ctrl_defs.h"
static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
{
uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
>> OBJECT_TYPE_SHIFT;
enum object_type object_type;
switch (bios_object_type) {
case GRAPH_OBJECT_TYPE_GPU:
object_type = OBJECT_TYPE_GPU;
break;
case GRAPH_OBJECT_TYPE_ENCODER:
object_type = OBJECT_TYPE_ENCODER;
break;
case GRAPH_OBJECT_TYPE_CONNECTOR:
object_type = OBJECT_TYPE_CONNECTOR;
break;
case GRAPH_OBJECT_TYPE_ROUTER:
object_type = OBJECT_TYPE_ROUTER;
break;
case GRAPH_OBJECT_TYPE_GENERIC:
object_type = OBJECT_TYPE_GENERIC;
break;
default:
object_type = OBJECT_TYPE_UNKNOWN;
break;
}
return object_type;
}
static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
{
uint32_t bios_enum_id =
(bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
enum object_enum_id id;
switch (bios_enum_id) {
case GRAPH_OBJECT_ENUM_ID1:
id = ENUM_ID_1;
break;
case GRAPH_OBJECT_ENUM_ID2:
id = ENUM_ID_2;
break;
case GRAPH_OBJECT_ENUM_ID3:
id = ENUM_ID_3;
break;
case GRAPH_OBJECT_ENUM_ID4:
id = ENUM_ID_4;
break;
case GRAPH_OBJECT_ENUM_ID5:
id = ENUM_ID_5;
break;
case GRAPH_OBJECT_ENUM_ID6:
id = ENUM_ID_6;
break;
case GRAPH_OBJECT_ENUM_ID7:
id = ENUM_ID_7;
break;
default:
id = ENUM_ID_UNKNOWN;
break;
}
return id;
}
static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)
{
return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
}
static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
{
uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
enum encoder_id id;
switch (bios_encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
id = ENCODER_ID_INTERNAL_LVDS;
break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
id = ENCODER_ID_INTERNAL_TMDS1;
break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
id = ENCODER_ID_INTERNAL_TMDS2;
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
id = ENCODER_ID_INTERNAL_DAC1;
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
id = ENCODER_ID_INTERNAL_DAC2;
break;
case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
id = ENCODER_ID_INTERNAL_LVTM1;
break;
case ENCODER_OBJECT_ID_HDMI_INTERNAL:
id = ENCODER_ID_INTERNAL_HDMI;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
break;
case ENCODER_OBJECT_ID_MVPU_FPGA:
id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
break;
case ENCODER_OBJECT_ID_INTERNAL_DDI:
id = ENCODER_ID_INTERNAL_DDI;
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
id = ENCODER_ID_INTERNAL_UNIPHY;
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA;
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
id = ENCODER_ID_INTERNAL_UNIPHY1;
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
id = ENCODER_ID_INTERNAL_UNIPHY2;
break;
case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
id = ENCODER_ID_EXTERNAL_NUTMEG;
break;
case ENCODER_OBJECT_ID_TRAVIS:
id = ENCODER_ID_EXTERNAL_TRAVIS;
break;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
id = ENCODER_ID_INTERNAL_UNIPHY3;
break;
default:
id = ENCODER_ID_UNKNOWN;
ASSERT(0);
break;
}
return id;
}
static enum connector_id connector_id_from_bios_object_id(
uint32_t bios_object_id)
{
uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);
enum connector_id id;
switch (bios_connector_id) {
case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:
id = CONNECTOR_ID_SINGLE_LINK_DVII;
break;
case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:
id = CONNECTOR_ID_DUAL_LINK_DVII;
break;
case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:
id = CONNECTOR_ID_SINGLE_LINK_DVID;
break;
case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:
id = CONNECTOR_ID_DUAL_LINK_DVID;
break;
case CONNECTOR_OBJECT_ID_VGA:
id = CONNECTOR_ID_VGA;
break;
case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:
id = CONNECTOR_ID_HDMI_TYPE_A;
break;
case CONNECTOR_OBJECT_ID_LVDS:
id = CONNECTOR_ID_LVDS;
break;
case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR:
id = CONNECTOR_ID_PCIE;
break;
case CONNECTOR_OBJECT_ID_HARDCODE_DVI:
id = CONNECTOR_ID_HARDCODE_DVI;
break;
case CONNECTOR_OBJECT_ID_DISPLAYPORT:
id = CONNECTOR_ID_DISPLAY_PORT;
break;
case CONNECTOR_OBJECT_ID_eDP:
id = CONNECTOR_ID_EDP;
break;
case CONNECTOR_OBJECT_ID_MXM:
id = CONNECTOR_ID_MXM;
break;
default:
id = CONNECTOR_ID_UNKNOWN;
break;
}
return id;
}
static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)
{
uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id);
enum generic_id id;
switch (bios_generic_id) {
case GENERIC_OBJECT_ID_MXM_OPM:
id = GENERIC_ID_MXM_OPM;
break;
case GENERIC_OBJECT_ID_GLSYNC:
id = GENERIC_ID_GLSYNC;
break;
case GENERIC_OBJECT_ID_STEREO_PIN:
id = GENERIC_ID_STEREO;
break;
default:
id = GENERIC_ID_UNKNOWN;
break;
}
return id;
}
static uint32_t id_from_bios_object_id(enum object_type type,
uint32_t bios_object_id)
{
switch (type) {
case OBJECT_TYPE_GPU:
return gpu_id_from_bios_object_id(bios_object_id);
case OBJECT_TYPE_ENCODER:
return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
case OBJECT_TYPE_CONNECTOR:
return (uint32_t)connector_id_from_bios_object_id(
bios_object_id);
case OBJECT_TYPE_GENERIC:
return generic_id_from_bios_object_id(bios_object_id);
default:
return 0;
}
}
struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id)
{
enum object_type type;
enum object_enum_id enum_id;
struct graphics_object_id go_id = { 0 };
type = object_type_from_bios_object_id(bios_object_id);
if (OBJECT_TYPE_UNKNOWN == type)
return go_id;
enum_id = enum_id_from_bios_object_id(bios_object_id);
if (ENUM_ID_UNKNOWN == enum_id)
return go_id;
go_id = dal_graphics_object_id_init(
id_from_bios_object_id(type, bios_object_id), enum_id, type);
return go_id;
}

33
drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __BIOS_PARSER_COMMON_H__
#define __BIOS_PARSER_COMMON_H__
#include "dm_services.h"
#include "ObjectID.h"
struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id);
#endif

82
drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c Normal file
View File

@ -0,0 +1,82 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/bios_parser_types.h"
#include "bios_parser_helper.h"
#include "command_table_helper.h"
#include "command_table.h"
#include "bios_parser_types_internal.h"
uint8_t *bios_get_image(struct dc_bios *bp,
uint32_t offset,
uint32_t size)
{
if (bp->bios && offset + size < bp->bios_size)
return bp->bios + offset;
else
return NULL;
}
#include "reg_helper.h"
#define CTX \
bios->ctx
#define REG(reg)\
(bios->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
ATOM_ ## field_name ## _SHIFT, ATOM_ ## field_name
bool bios_is_accelerated_mode(
struct dc_bios *bios)
{
uint32_t acc_mode;
REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);
return (acc_mode == 1);
}
void bios_set_scratch_acc_mode_change(
struct dc_bios *bios)
{
REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
}
void bios_set_scratch_critical_state(
struct dc_bios *bios,
bool state)
{
uint32_t critial_state = state ? 1 : 0;
REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
}

40
drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_HELPER_H__
#define __DAL_BIOS_PARSER_HELPER_H__
struct bios_parser;
uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,
uint32_t size);
bool bios_is_accelerated_mode(struct dc_bios *bios);
void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
#define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type)))
#endif

56
drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c Normal file
View File

@ -0,0 +1,56 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/logger_interface.h"
#include "bios_parser_interface.h"
#include "bios_parser.h"
#include "bios_parser2.h"
struct dc_bios *dal_bios_parser_create(
struct bp_init_data *init,
enum dce_version dce_version)
{
struct dc_bios *bios = NULL;
bios = firmware_parser_create(init, dce_version);
/* Fall back to old bios parser for older asics */
if (bios == NULL)
bios = bios_parser_create(init, dce_version);
return bios;
}
void dal_bios_parser_destroy(struct dc_bios **dcb)
{
struct dc_bios *bios = *dcb;
bios->funcs->bios_parser_destroy(dcb);
}

72
drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_TYPES_BIOS_H__
#define __DAL_BIOS_PARSER_TYPES_BIOS_H__
#include "dc_bios_types.h"
#include "bios_parser_helper.h"
struct atom_data_revision {
uint32_t major;
uint32_t minor;
};
struct object_info_table {
struct atom_data_revision revision;
union {
ATOM_OBJECT_HEADER *v1_1;
ATOM_OBJECT_HEADER_V3 *v1_3;
};
};
enum spread_spectrum_id {
SS_ID_UNKNOWN = 0,
SS_ID_DP1 = 0xf1,
SS_ID_DP2 = 0xf2,
SS_ID_LVLINK_2700MHZ = 0xf3,
SS_ID_LVLINK_1620MHZ = 0xf4
};
struct bios_parser {
struct dc_bios base;
struct object_info_table object_info_tbl;
uint32_t object_info_tbl_offset;
ATOM_MASTER_DATA_TABLE *master_data_tbl;
const struct bios_parser_helper *bios_helper;
const struct command_table_helper *cmd_helper;
struct cmd_tbl cmd_tbl;
bool remap_device_tags;
};
/* Bios Parser from DC Bios */
#define BP_FROM_DCB(dc_bios) \
container_of(dc_bios, struct bios_parser, base)
#endif

74
drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_BIOS_PARSER_TYPES_BIOS2_H__
#define __DAL_BIOS_PARSER_TYPES_BIOS2_H__
#include "dc_bios_types.h"
#include "bios_parser_helper.h"
/* use atomfirmware_bringup.h only. Not atombios.h anymore */
struct atom_data_revision {
uint32_t major;
uint32_t minor;
};
struct object_info_table {
struct atom_data_revision revision;
union {
struct display_object_info_table_v1_4 *v1_4;
};
};
enum spread_spectrum_id {
SS_ID_UNKNOWN = 0,
SS_ID_DP1 = 0xf1,
SS_ID_DP2 = 0xf2,
SS_ID_LVLINK_2700MHZ = 0xf3,
SS_ID_LVLINK_1620MHZ = 0xf4
};
struct bios_parser {
struct dc_bios base;
struct object_info_table object_info_tbl;
uint32_t object_info_tbl_offset;
struct atom_master_data_table_v2_1 *master_data_tbl;
const struct bios_parser_helper *bios_helper;
const struct command_table_helper *cmd_helper;
struct cmd_tbl cmd_tbl;
bool remap_device_tags;
};
/* Bios Parser from DC Bios */
#define BP_FROM_DCB(dc_bios) \
container_of(dc_bios, struct bios_parser, base)
#endif

2424
drivers/gpu/drm/amd/display/dc/bios/command_table.c Normal file
View File

File diff suppressed because it is too large Load Diff

102
drivers/gpu/drm/amd/display/dc/bios/command_table.h Normal file
View File

@ -0,0 +1,102 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_H__
#define __DAL_COMMAND_TABLE_H__
struct bios_parser;
struct bp_encoder_control;
struct cmd_tbl {
enum bp_result (*dig_encoder_control)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*encoder_control_dig1)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*encoder_control_dig2)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*transmitter_control)(
struct bios_parser *bp,
struct bp_transmitter_control *control);
enum bp_result (*set_pixel_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*enable_spread_spectrum_on_ppll)(
struct bios_parser *bp,
struct bp_spread_spectrum_parameters *bp_params,
bool enable);
enum bp_result (*adjust_display_pll)(
struct bios_parser *bp,
struct bp_adjust_pixel_clock_parameters *bp_params);
enum bp_result (*dac1_encoder_control)(
struct bios_parser *bp,
bool enable,
uint32_t pixel_clock,
uint8_t dac_standard);
enum bp_result (*dac2_encoder_control)(
struct bios_parser *bp,
bool enable,
uint32_t pixel_clock,
uint8_t dac_standard);
enum bp_result (*dac1_output_control)(
struct bios_parser *bp,
bool enable);
enum bp_result (*dac2_output_control)(
struct bios_parser *bp,
bool enable);
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
enum bp_result (*enable_crtc)(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable);
enum bp_result (*enable_crtc_mem_req)(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable);
enum bp_result (*program_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*external_encoder_control)(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl);
enum bp_result (*enable_disp_power_gating)(
struct bios_parser *bp,
enum controller_id crtc_id,
enum bp_pipe_control_action action);
enum bp_result (*set_dce_clock)(
struct bios_parser *bp,
struct bp_set_dce_clock_parameters *bp_params);
};
void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp);
#endif

812
drivers/gpu/drm/amd/display/dc/bios/command_table2.c Normal file
View File

@ -0,0 +1,812 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "ObjectID.h"
#include "atomfirmware.h"
#include "include/bios_parser_interface.h"
#include "command_table2.h"
#include "command_table_helper2.h"
#include "bios_parser_helper.h"
#include "bios_parser_types_internal2.h"
#define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
(((char *)(&((\
struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
->FieldName)-(char *)0)/sizeof(uint16_t))
#define EXEC_BIOS_CMD_TABLE(fname, params)\
(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
GET_INDEX_INTO_MASTER_TABLE(command, fname), \
&params) == 0)
#define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
#define BIOS_CMD_TABLE_PARA_REVISION(fname)\
bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
GET_INDEX_INTO_MASTER_TABLE(command, fname))
static void init_dig_encoder_control(struct bios_parser *bp);
static void init_transmitter_control(struct bios_parser *bp);
static void init_set_pixel_clock(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
static void init_enable_disp_power_gating(struct bios_parser *bp);
static void init_set_dce_clock(struct bios_parser *bp);
static void init_get_smu_clock_info(struct bios_parser *bp);
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
{
init_dig_encoder_control(bp);
init_transmitter_control(bp);
init_set_pixel_clock(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
init_get_smu_clock_info(bp);
}
static uint32_t bios_cmd_table_para_revision(void *cgs_device,
uint32_t index)
{
uint8_t frev, crev;
if (cgs_atom_get_cmd_table_revs(cgs_device,
index,
&frev, &crev) != 0)
return 0;
return crev;
}
/******************************************************************************
******************************************************************************
**
** D I G E N C O D E R C O N T R O L
**
******************************************************************************
*****************************************************************************/
static enum bp_result encoder_control_digx_v1_5(
struct bios_parser *bp,
struct bp_encoder_control *cntl);
static void init_dig_encoder_control(struct bios_parser *bp)
{
uint32_t version =
BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);
switch (version) {
case 5:
bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
break;
default:
bp->cmd_tbl.dig_encoder_control = NULL;
break;
}
}
static enum bp_result encoder_control_digx_v1_5(
struct bios_parser *bp,
struct bp_encoder_control *cntl)
{
enum bp_result result = BP_RESULT_FAILURE;
struct dig_encoder_stream_setup_parameters_v1_5 params = {0};
params.digid = (uint8_t)(cntl->engine_id);
params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
params.pclk_10khz = cntl->pixel_clock / 10;
params.digmode =
(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
cntl->signal,
cntl->enable_dp_audio));
params.lanenum = (uint8_t)(cntl->lanes_number);
switch (cntl->color_depth) {
case COLOR_DEPTH_888:
params.bitpercolor = PANEL_8BIT_PER_COLOR;
break;
case COLOR_DEPTH_101010:
params.bitpercolor = PANEL_10BIT_PER_COLOR;
break;
case COLOR_DEPTH_121212:
params.bitpercolor = PANEL_12BIT_PER_COLOR;
break;
case COLOR_DEPTH_161616:
params.bitpercolor = PANEL_16BIT_PER_COLOR;
break;
default:
break;
}
if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
switch (cntl->color_depth) {
case COLOR_DEPTH_101010:
params.pclk_10khz =
(params.pclk_10khz * 30) / 24;
break;
case COLOR_DEPTH_121212:
params.pclk_10khz =
(params.pclk_10khz * 36) / 24;
break;
case COLOR_DEPTH_161616:
params.pclk_10khz =
(params.pclk_10khz * 48) / 24;
break;
default:
break;
}
if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
result = BP_RESULT_OK;
return result;
}
/*****************************************************************************
******************************************************************************
**
** TRANSMITTER CONTROL
**
******************************************************************************
*****************************************************************************/
static enum bp_result transmitter_control_v1_6(
struct bios_parser *bp,
struct bp_transmitter_control *cntl);
static void init_transmitter_control(struct bios_parser *bp)
{
uint8_t frev;
uint8_t crev;
if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0)
BREAK_TO_DEBUGGER();
switch (crev) {
case 6:
bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
break;
default:
bp->cmd_tbl.transmitter_control = NULL;
break;
}
}
static enum bp_result transmitter_control_v1_6(
struct bios_parser *bp,
struct bp_transmitter_control *cntl)
{
enum bp_result result = BP_RESULT_FAILURE;
const struct command_table_helper *cmd = bp->cmd_helper;
struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } };
ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
ps.param.action = (uint8_t)cntl->action;
if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
else
ps.param.mode_laneset.digmode =
cmd->signal_type_to_atom_dig_mode(cntl->signal);
ps.param.lanenum = (uint8_t)cntl->lanes_number;
ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
ps.param.symclk_10khz = cntl->pixel_clock/10;
if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
"%s:ps.param.symclk_10khz = %d\n",\
__func__, ps.param.symclk_10khz);
}
/*color_depth not used any more, driver has deep color factor in the Phyclk*/
if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************
******************************************************************************
**
** SET PIXEL CLOCK
**
******************************************************************************
*****************************************************************************/
static enum bp_result set_pixel_clock_v7(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
static void init_set_pixel_clock(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
case 7:
bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
break;
default:
bp->cmd_tbl.set_pixel_clock = NULL;
break;
}
}
static enum bp_result set_pixel_clock_v7(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params)
{
enum bp_result result = BP_RESULT_FAILURE;
struct set_pixel_clock_parameter_v1_7 clk;
uint8_t controller_id;
uint32_t pll_id;
memset(&clk, 0, sizeof(clk));
if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
&& bp->cmd_helper->controller_id_to_atom(bp_params->
controller_id, &controller_id)) {
/* Note: VBIOS still wants to use ucCRTC name which is now
* 1 byte in ULONG
*typedef struct _CRTC_PIXEL_CLOCK_FREQ
*{
* target the pixel clock to drive the CRTC timing.
* ULONG ulPixelClock:24;
* 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
* previous version.
* ATOM_CRTC1~6, indicate the CRTC controller to
* ULONG ucCRTC:8;
* drive the pixel clock. not used for DCPLL case.
*}CRTC_PIXEL_CLOCK_FREQ;
*union
*{
* pixel clock and CRTC id frequency
* CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
* ULONG ulDispEngClkFreq; dispclk frequency
*};
*/
clk.crtc_id = controller_id;
clk.pll_id = (uint8_t) pll_id;
clk.encoderobjid =
bp->cmd_helper->encoder_id_to_atom(
dal_graphics_object_id_get_encoder_id(
bp_params->encoder_object_id));
clk.encoder_mode = (uint8_t) bp->
cmd_helper->encoder_mode_bp_to_atom(
bp_params->signal_type, false);
/* We need to convert from KHz units into 10KHz units */
clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock *
10);
clk.deep_color_ratio =
(uint8_t) bp->cmd_helper->
transmitter_color_depth_to_atom(
bp_params->color_depth);
dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
"%s:program display clock = %d"\
"colorDepth = %d\n", __func__,\
bp_params->target_pixel_clock, bp_params->color_depth);
if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
if (bp_params->flags.SUPPORT_YUV_420)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
if (bp_params->flags.SET_XTALIN_REF_SRC)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
result = BP_RESULT_OK;
}
return result;
}
/******************************************************************************
******************************************************************************
**
** SET CRTC TIMING
**
******************************************************************************
*****************************************************************************/
static enum bp_result set_crtc_using_dtd_timing_v3(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
static void init_set_crtc_timing(struct bios_parser *bp)
{
uint32_t dtd_version =
BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
switch (dtd_version) {
case 3:
bp->cmd_tbl.set_crtc_timing =
set_crtc_using_dtd_timing_v3;
break;
default:
bp->cmd_tbl.set_crtc_timing = NULL;
break;
}
}
static enum bp_result set_crtc_using_dtd_timing_v3(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params)
{
enum bp_result result = BP_RESULT_FAILURE;
struct set_crtc_using_dtd_timing_parameters params = {0};
uint8_t atom_controller_id;
if (bp->cmd_helper->controller_id_to_atom(
bp_params->controller_id, &atom_controller_id))
params.crtc_id = atom_controller_id;
/* bios usH_Size wants h addressable size */
params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
/* bios usH_Blanking_Time wants borders included in blanking */
params.h_blanking_time =
cpu_to_le16((uint16_t)(bp_params->h_total -
bp_params->h_addressable));
/* bios usV_Size wants v addressable size */
params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
/* bios usV_Blanking_Time wants borders included in blanking */
params.v_blanking_time =
cpu_to_le16((uint16_t)(bp_params->v_total -
bp_params->v_addressable));
/* bios usHSyncOffset is the offset from the end of h addressable,
* our horizontalSyncStart is the offset from the beginning
* of h addressable
*/
params.h_syncoffset =
cpu_to_le16((uint16_t)(bp_params->h_sync_start -
bp_params->h_addressable));
params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
/* bios usHSyncOffset is the offset from the end of v addressable,
* our verticalSyncStart is the offset from the beginning of
* v addressable
*/
params.v_syncoffset =
cpu_to_le16((uint16_t)(bp_params->v_sync_start -
bp_params->v_addressable));
params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
/* we assume that overscan from original timing does not get bigger
* than 255
* we will program all the borders in the Set CRTC Overscan call below
*/
if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0)
params.modemiscinfo =
cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
ATOM_HSYNC_POLARITY);
if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0)
params.modemiscinfo =
cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
ATOM_VSYNC_POLARITY);
if (bp_params->flags.INTERLACE) {
params.modemiscinfo =
cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
ATOM_INTERLACE);
/* original DAL code has this condition to apply this
* for non-TV/CV only
* due to complex MV testing for possible impact
* if ( pACParameters->signal != SignalType_YPbPr &&
* pACParameters->signal != SignalType_Composite &&
* pACParameters->signal != SignalType_SVideo)
*/
{
/* HW will deduct 0.5 line from 2nd feild.
* i.e. for 1080i, it is 2 lines for 1st field,
* 2.5 lines for the 2nd feild. we need input as 5
* instead of 4.
* but it is 4 either from Edid data (spec CEA 861)
* or CEA timing table.
*/
params.v_syncoffset =
cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
1);
}
}
if (bp_params->flags.HORZ_COUNT_BY_TWO)
params.modemiscinfo =
cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
0x100); /* ATOM_DOUBLE_CLOCK_MODE */
if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************
******************************************************************************
**
** SELECT CRTC SOURCE
**
******************************************************************************
*****************************************************************************/
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
static void init_select_crtc_source(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {
case 3:
bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
break;
default:
bp->cmd_tbl.select_crtc_source = NULL;
break;
}
}
static enum bp_result select_crtc_source_v3(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params)
{
bool result = BP_RESULT_FAILURE;
struct select_crtc_source_parameters_v2_3 params;
uint8_t atom_controller_id;
uint32_t atom_engine_id;
enum signal_type s = bp_params->signal;
memset(&params, 0, sizeof(params));
if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
&atom_controller_id))
params.crtc_id = atom_controller_id;
else
return result;
if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
&atom_engine_id))
params.encoder_id = (uint8_t)atom_engine_id;
else
return result;
if (s == SIGNAL_TYPE_EDP ||
(s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal ==
SIGNAL_TYPE_LVDS))
s = SIGNAL_TYPE_LVDS;
params.encode_mode =
bp->cmd_helper->encoder_mode_bp_to_atom(
s, bp_params->enable_dp_audio);
/* Needed for VBIOS Random Spatial Dithering feature */
params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth);
if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************
******************************************************************************
**
** ENABLE CRTC
**
******************************************************************************
*****************************************************************************/
static enum bp_result enable_crtc_v1(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable);
static void init_enable_crtc(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {
case 1:
bp->cmd_tbl.enable_crtc = enable_crtc_v1;
break;
default:
bp->cmd_tbl.enable_crtc = NULL;
break;
}
}
static enum bp_result enable_crtc_v1(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable)
{
bool result = BP_RESULT_FAILURE;
struct enable_crtc_parameters params = {0};
uint8_t id;
if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
params.crtc_id = id;
else
return BP_RESULT_BADINPUT;
if (enable)
params.enable = ATOM_ENABLE;
else
params.enable = ATOM_DISABLE;
if (EXEC_BIOS_CMD_TABLE(enablecrtc, params))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************
******************************************************************************
**
** DISPLAY PLL
**
******************************************************************************
*****************************************************************************/
/******************************************************************************
******************************************************************************
**
** EXTERNAL ENCODER CONTROL
**
******************************************************************************
*****************************************************************************/
static enum bp_result external_encoder_control_v3(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl);
static void init_external_encoder_control(
struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {
case 3:
bp->cmd_tbl.external_encoder_control =
external_encoder_control_v3;
break;
default:
bp->cmd_tbl.external_encoder_control = NULL;
break;
}
}
static enum bp_result external_encoder_control_v3(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl)
{
/* TODO */
return BP_RESULT_OK;
}
/******************************************************************************
******************************************************************************
**
** ENABLE DISPLAY POWER GATING
**
******************************************************************************
*****************************************************************************/
static enum bp_result enable_disp_power_gating_v2_1(
struct bios_parser *bp,
enum controller_id crtc_id,
enum bp_pipe_control_action action);
static void init_enable_disp_power_gating(
struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {
case 1:
bp->cmd_tbl.enable_disp_power_gating =
enable_disp_power_gating_v2_1;
break;
default:
bp->cmd_tbl.enable_disp_power_gating = NULL;
break;
}
}
static enum bp_result enable_disp_power_gating_v2_1(
struct bios_parser *bp,
enum controller_id crtc_id,
enum bp_pipe_control_action action)
{
enum bp_result result = BP_RESULT_FAILURE;
struct enable_disp_power_gating_ps_allocation ps = { { 0 } };
uint8_t atom_crtc_id;
if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
ps.param.disp_pipe_id = atom_crtc_id;
else
return BP_RESULT_BADINPUT;
ps.param.enable =
bp->cmd_helper->disp_power_gating_action_to_atom(action);
if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
result = BP_RESULT_OK;
return result;
}
/******************************************************************************
*******************************************************************************
**
** SET DCE CLOCK
**
*******************************************************************************
*******************************************************************************/
static enum bp_result set_dce_clock_v2_1(
struct bios_parser *bp,
struct bp_set_dce_clock_parameters *bp_params);
static void init_set_dce_clock(struct bios_parser *bp)
{
switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {
case 1:
bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
break;
default:
bp->cmd_tbl.set_dce_clock = NULL;
break;
}
}
static enum bp_result set_dce_clock_v2_1(
struct bios_parser *bp,
struct bp_set_dce_clock_parameters *bp_params)
{
enum bp_result result = BP_RESULT_FAILURE;
struct set_dce_clock_ps_allocation_v2_1 params;
uint32_t atom_pll_id;
uint32_t atom_clock_type;
const struct command_table_helper *cmd = bp->cmd_helper;
memset(&params, 0, sizeof(params));
if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
!cmd->dc_clock_type_to_atom(bp_params->clock_type,
&atom_clock_type))
return BP_RESULT_BADINPUT;
params.param.dceclksrc = atom_pll_id;
params.param.dceclktype = atom_clock_type;
if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
params.param.dceclkflag |=
DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
params.param.dceclkflag |=
DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
params.param.dceclkflag |=
DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
params.param.dceclkflag |=
DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
} else
/* only program clock frequency if display clock is used;
* VBIOS will program DPREFCLK
* We need to convert from KHz units into 10KHz units
*/
params.param.dceclk_10khz = cpu_to_le32(
bp_params->target_clock_frequency / 10);
dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
"%s:target_clock_frequency = %d"\
"clock_type = %d \n", __func__,\
bp_params->target_clock_frequency,\
bp_params->clock_type);
if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) {
/* Convert from 10KHz units back to KHz */
bp_params->target_clock_frequency = le32_to_cpu(
params.param.dceclk_10khz) * 10;
result = BP_RESULT_OK;
}
return result;
}
/******************************************************************************
******************************************************************************
**
** GET SMU CLOCK INFO
**
******************************************************************************
*****************************************************************************/
static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp);
static void init_get_smu_clock_info(struct bios_parser *bp)
{
/* TODO add switch for table vrsion */
bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
}
static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp)
{
struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
/* Get Specific Clock */
if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
memmove(&smu_output, &smu_input, sizeof(
struct atom_get_smu_clock_info_parameters_v3_1));
return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz;
}
return 0;
}

105
drivers/gpu/drm/amd/display/dc/bios/command_table2.h Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE2_H__
#define __DAL_COMMAND_TABLE2_H__
struct bios_parser;
struct bp_encoder_control;
struct cmd_tbl {
enum bp_result (*dig_encoder_control)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*encoder_control_dig1)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*encoder_control_dig2)(
struct bios_parser *bp,
struct bp_encoder_control *control);
enum bp_result (*transmitter_control)(
struct bios_parser *bp,
struct bp_transmitter_control *control);
enum bp_result (*set_pixel_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*enable_spread_spectrum_on_ppll)(
struct bios_parser *bp,
struct bp_spread_spectrum_parameters *bp_params,
bool enable);
enum bp_result (*adjust_display_pll)(
struct bios_parser *bp,
struct bp_adjust_pixel_clock_parameters *bp_params);
enum bp_result (*dac1_encoder_control)(
struct bios_parser *bp,
bool enable,
uint32_t pixel_clock,
uint8_t dac_standard);
enum bp_result (*dac2_encoder_control)(
struct bios_parser *bp,
bool enable,
uint32_t pixel_clock,
uint8_t dac_standard);
enum bp_result (*dac1_output_control)(
struct bios_parser *bp,
bool enable);
enum bp_result (*dac2_output_control)(
struct bios_parser *bp,
bool enable);
enum bp_result (*set_crtc_timing)(
struct bios_parser *bp,
struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*select_crtc_source)(
struct bios_parser *bp,
struct bp_crtc_source_select *bp_params);
enum bp_result (*enable_crtc)(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable);
enum bp_result (*enable_crtc_mem_req)(
struct bios_parser *bp,
enum controller_id controller_id,
bool enable);
enum bp_result (*program_clock)(
struct bios_parser *bp,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*external_encoder_control)(
struct bios_parser *bp,
struct bp_external_encoder_control *cntl);
enum bp_result (*enable_disp_power_gating)(
struct bios_parser *bp,
enum controller_id crtc_id,
enum bp_pipe_control_action action);
enum bp_result (*set_dce_clock)(
struct bios_parser *bp,
struct bp_set_dce_clock_parameters *bp_params);
unsigned int (*get_smu_clock_info)(
struct bios_parser *bp);
};
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);
#endif

290
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c Normal file
View File

@ -0,0 +1,290 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/bios_parser_types.h"
#include "command_table_helper.h"
bool dal_bios_parser_init_cmd_tbl_helper(
const struct command_table_helper **h,
enum dce_version dce)
{
switch (dce) {
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
*h = dal_cmd_tbl_helper_dce80_get_table();
return true;
case DCE_VERSION_10_0:
*h = dal_cmd_tbl_helper_dce110_get_table();
return true;
case DCE_VERSION_11_0:
*h = dal_cmd_tbl_helper_dce110_get_table();
return true;
case DCE_VERSION_11_2:
*h = dal_cmd_tbl_helper_dce112_get_table();
return true;
default:
/* Unsupported DCE */
BREAK_TO_DEBUGGER();
return false;
}
}
/* real implementations */
bool dal_cmd_table_helper_controller_id_to_atom(
enum controller_id id,
uint8_t *atom_id)
{
if (atom_id == NULL) {
BREAK_TO_DEBUGGER();
return false;
}
switch (id) {
case CONTROLLER_ID_D0:
*atom_id = ATOM_CRTC1;
return true;
case CONTROLLER_ID_D1:
*atom_id = ATOM_CRTC2;
return true;
case CONTROLLER_ID_D2:
*atom_id = ATOM_CRTC3;
return true;
case CONTROLLER_ID_D3:
*atom_id = ATOM_CRTC4;
return true;
case CONTROLLER_ID_D4:
*atom_id = ATOM_CRTC5;
return true;
case CONTROLLER_ID_D5:
*atom_id = ATOM_CRTC6;
return true;
case CONTROLLER_ID_UNDERLAY0:
*atom_id = ATOM_UNDERLAY_PIPE0;
return true;
case CONTROLLER_ID_UNDEFINED:
*atom_id = ATOM_CRTC_INVALID;
return true;
default:
/* Wrong controller id */
BREAK_TO_DEBUGGER();
return false;
}
}
/**
* translate_transmitter_bp_to_atom
*
* @brief
* Translate the Transmitter to the corresponding ATOM BIOS value
*
* @param
* input transmitter
* output digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
enum transmitter t)
{
switch (t) {
case TRANSMITTER_UNIPHY_A:
case TRANSMITTER_UNIPHY_B:
case TRANSMITTER_TRAVIS_LCD:
return 0;
case TRANSMITTER_UNIPHY_C:
case TRANSMITTER_UNIPHY_D:
return 1;
case TRANSMITTER_UNIPHY_E:
case TRANSMITTER_UNIPHY_F:
return 2;
default:
/* Invalid Transmitter Type! */
BREAK_TO_DEBUGGER();
return 0;
}
}
uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
enum signal_type s,
bool enable_dp_audio)
{
switch (s) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
return ATOM_ENCODER_MODE_DVI;
case SIGNAL_TYPE_HDMI_TYPE_A:
return ATOM_ENCODER_MODE_HDMI;
case SIGNAL_TYPE_LVDS:
return ATOM_ENCODER_MODE_LVDS;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_VIRTUAL:
if (enable_dp_audio)
return ATOM_ENCODER_MODE_DP_AUDIO;
else
return ATOM_ENCODER_MODE_DP;
case SIGNAL_TYPE_RGB:
return ATOM_ENCODER_MODE_CRT;
default:
return ATOM_ENCODER_MODE_CRT;
}
}
void dal_cmd_table_helper_assign_control_parameter(
const struct command_table_helper *h,
struct bp_encoder_control *control,
DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
{
/* there are three transmitter blocks, each one has two links 4-lanes
* each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
* each transmitter block B, D and F as link 1, third transmitter block
* has non splitable links (UniphyE and UniphyF can not be configured
* separately to drive two different streams)
*/
if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
(control->transmitter == TRANSMITTER_UNIPHY_D) ||
(control->transmitter == TRANSMITTER_UNIPHY_F)) {
/* Bit2: Link Select
* =0: PHY linkA/C/E
* =1: PHY linkB/D/F
*/
ctrl_param->acConfig.ucLinkSel = 1;
}
/* Bit[4:3]: Transmitter Selection
* =00: Digital Transmitter1 ( UNIPHY linkAB )
* =01: Digital Transmitter2 ( UNIPHY linkCD )
* =02: Digital Transmitter3 ( UNIPHY linkEF )
* =03: Reserved
*/
ctrl_param->acConfig.ucTransmitterSel =
(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
/* We need to convert from KHz units into 10KHz units */
ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
ctrl_param->ucEncoderMode =
(uint8_t)(h->encoder_mode_bp_to_atom(
control->signal, control->enable_dp_audio));
ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
}
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
enum clock_source_id id,
uint32_t *ref_clk_src_id)
{
if (ref_clk_src_id == NULL) {
BREAK_TO_DEBUGGER();
return false;
}
switch (id) {
case CLOCK_SOURCE_ID_PLL1:
*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
return true;
case CLOCK_SOURCE_ID_PLL2:
*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
return true;
case CLOCK_SOURCE_ID_DCPLL:
*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
return true;
case CLOCK_SOURCE_ID_EXTERNAL:
*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
return true;
case CLOCK_SOURCE_ID_UNDEFINED:
*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
return true;
default:
/* Unsupported clock source id */
BREAK_TO_DEBUGGER();
return false;
}
}
uint8_t dal_cmd_table_helper_encoder_id_to_atom(
enum encoder_id id)
{
switch (id) {
case ENCODER_ID_INTERNAL_LVDS:
return ENCODER_OBJECT_ID_INTERNAL_LVDS;
case ENCODER_ID_INTERNAL_TMDS1:
return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
case ENCODER_ID_INTERNAL_TMDS2:
return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
case ENCODER_ID_INTERNAL_DAC1:
return ENCODER_OBJECT_ID_INTERNAL_DAC1;
case ENCODER_ID_INTERNAL_DAC2:
return ENCODER_OBJECT_ID_INTERNAL_DAC2;
case ENCODER_ID_INTERNAL_LVTM1:
return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
case ENCODER_ID_INTERNAL_HDMI:
return ENCODER_OBJECT_ID_HDMI_INTERNAL;
case ENCODER_ID_EXTERNAL_TRAVIS:
return ENCODER_OBJECT_ID_TRAVIS;
case ENCODER_ID_EXTERNAL_NUTMEG:
return ENCODER_OBJECT_ID_NUTMEG;
case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
case ENCODER_ID_EXTERNAL_MVPU_FPGA:
return ENCODER_OBJECT_ID_MVPU_FPGA;
case ENCODER_ID_INTERNAL_DDI:
return ENCODER_OBJECT_ID_INTERNAL_DDI;
case ENCODER_ID_INTERNAL_UNIPHY:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
case ENCODER_ID_INTERNAL_UNIPHY1:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
case ENCODER_ID_INTERNAL_UNIPHY2:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
case ENCODER_ID_INTERNAL_UNIPHY3:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
case ENCODER_ID_INTERNAL_WIRELESS:
return ENCODER_OBJECT_ID_INTERNAL_VCE;
case ENCODER_ID_UNKNOWN:
return ENCODER_OBJECT_ID_NONE;
default:
/* Invalid encoder id */
BREAK_TO_DEBUGGER();
return ENCODER_OBJECT_ID_NONE;
}
}

90
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h Normal file
View File

@ -0,0 +1,90 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER_H__
#define __DAL_COMMAND_TABLE_HELPER_H__
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper_dce112.h"
struct command_table_helper {
bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
uint8_t (*encoder_action_to_atom)(
enum bp_encoder_control_action action);
uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s,
bool enable_dp_audio);
bool (*engine_bp_to_atom)(enum engine_id engine_id,
uint32_t *atom_engine_id);
void (*assign_control_parameter)(
const struct command_table_helper *h,
struct bp_encoder_control *control,
DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
bool (*clock_source_id_to_atom)(enum clock_source_id id,
uint32_t *atom_pll_id);
bool (*clock_source_id_to_ref_clk_src)(
enum clock_source_id id,
uint32_t *ref_clk_src_id);
uint8_t (*transmitter_bp_to_atom)(enum transmitter t);
uint8_t (*encoder_id_to_atom)(enum encoder_id id);
uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(
enum clock_source_id id);
uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);
uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);
uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
uint8_t (*phy_id_to_atom)(enum transmitter t);
uint8_t (*disp_power_gating_action_to_atom)(
enum bp_pipe_control_action action);
bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
uint32_t *atom_clock_type);
uint8_t (*transmitter_color_depth_to_atom)(enum transmitter_color_depth id);
};
bool dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper **h,
enum dce_version dce);
bool dal_cmd_table_helper_controller_id_to_atom(
enum controller_id id,
uint8_t *atom_id);
uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
enum signal_type s,
bool enable_dp_audio);
void dal_cmd_table_helper_assign_control_parameter(
const struct command_table_helper *h,
struct bp_encoder_control *control,
DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
enum clock_source_id id,
uint32_t *ref_clk_src_id);
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
enum transmitter t);
uint8_t dal_cmd_table_helper_encoder_id_to_atom(
enum encoder_id id);
#endif

265
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c Normal file
View File

@ -0,0 +1,265 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "ObjectID.h"
#include "atomfirmware.h"
#include "include/bios_parser_types.h"
#include "command_table_helper2.h"
bool dal_bios_parser_init_cmd_tbl_helper2(
const struct command_table_helper **h,
enum dce_version dce)
{
switch (dce) {
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
*h = dal_cmd_tbl_helper_dce80_get_table();
return true;
case DCE_VERSION_10_0:
*h = dal_cmd_tbl_helper_dce110_get_table();
return true;
case DCE_VERSION_11_0:
*h = dal_cmd_tbl_helper_dce110_get_table();
return true;
case DCE_VERSION_11_2:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
default:
/* Unsupported DCE */
BREAK_TO_DEBUGGER();
return false;
}
}
/* real implementations */
bool dal_cmd_table_helper_controller_id_to_atom2(
enum controller_id id,
uint8_t *atom_id)
{
if (atom_id == NULL) {
BREAK_TO_DEBUGGER();
return false;
}
switch (id) {
case CONTROLLER_ID_D0:
*atom_id = ATOM_CRTC1;
return true;
case CONTROLLER_ID_D1:
*atom_id = ATOM_CRTC2;
return true;
case CONTROLLER_ID_D2:
*atom_id = ATOM_CRTC3;
return true;
case CONTROLLER_ID_D3:
*atom_id = ATOM_CRTC4;
return true;
case CONTROLLER_ID_D4:
*atom_id = ATOM_CRTC5;
return true;
case CONTROLLER_ID_D5:
*atom_id = ATOM_CRTC6;
return true;
/* TODO :case CONTROLLER_ID_UNDERLAY0:
*atom_id = ATOM_UNDERLAY_PIPE0;
return true;
*/
case CONTROLLER_ID_UNDEFINED:
*atom_id = ATOM_CRTC_INVALID;
return true;
default:
/* Wrong controller id */
BREAK_TO_DEBUGGER();
return false;
}
}
/**
* translate_transmitter_bp_to_atom
*
* @brief
* Translate the Transmitter to the corresponding ATOM BIOS value
*
* @param
* input transmitter
* output digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
enum transmitter t)
{
switch (t) {
case TRANSMITTER_UNIPHY_A:
case TRANSMITTER_UNIPHY_B:
case TRANSMITTER_TRAVIS_LCD:
return 0;
case TRANSMITTER_UNIPHY_C:
case TRANSMITTER_UNIPHY_D:
return 1;
case TRANSMITTER_UNIPHY_E:
case TRANSMITTER_UNIPHY_F:
return 2;
default:
/* Invalid Transmitter Type! */
BREAK_TO_DEBUGGER();
return 0;
}
}
uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
enum signal_type s,
bool enable_dp_audio)
{
switch (s) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
return ATOM_ENCODER_MODE_DVI;
case SIGNAL_TYPE_HDMI_TYPE_A:
return ATOM_ENCODER_MODE_HDMI;
case SIGNAL_TYPE_LVDS:
return ATOM_ENCODER_MODE_LVDS;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_VIRTUAL:
if (enable_dp_audio)
return ATOM_ENCODER_MODE_DP_AUDIO;
else
return ATOM_ENCODER_MODE_DP;
case SIGNAL_TYPE_RGB:
return ATOM_ENCODER_MODE_CRT;
default:
return ATOM_ENCODER_MODE_CRT;
}
}
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
enum clock_source_id id,
uint32_t *ref_clk_src_id)
{
if (ref_clk_src_id == NULL) {
BREAK_TO_DEBUGGER();
return false;
}
switch (id) {
case CLOCK_SOURCE_ID_PLL1:
*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
return true;
case CLOCK_SOURCE_ID_PLL2:
*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
return true;
/*TODO:case CLOCK_SOURCE_ID_DCPLL:
*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
return true;
*/
case CLOCK_SOURCE_ID_EXTERNAL:
*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
return true;
case CLOCK_SOURCE_ID_UNDEFINED:
*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
return true;
default:
/* Unsupported clock source id */
BREAK_TO_DEBUGGER();
return false;
}
}
uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
enum encoder_id id)
{
switch (id) {
case ENCODER_ID_INTERNAL_LVDS:
return ENCODER_OBJECT_ID_INTERNAL_LVDS;
case ENCODER_ID_INTERNAL_TMDS1:
return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
case ENCODER_ID_INTERNAL_TMDS2:
return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
case ENCODER_ID_INTERNAL_DAC1:
return ENCODER_OBJECT_ID_INTERNAL_DAC1;
case ENCODER_ID_INTERNAL_DAC2:
return ENCODER_OBJECT_ID_INTERNAL_DAC2;
case ENCODER_ID_INTERNAL_LVTM1:
return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
case ENCODER_ID_INTERNAL_HDMI:
return ENCODER_OBJECT_ID_HDMI_INTERNAL;
case ENCODER_ID_EXTERNAL_TRAVIS:
return ENCODER_OBJECT_ID_TRAVIS;
case ENCODER_ID_EXTERNAL_NUTMEG:
return ENCODER_OBJECT_ID_NUTMEG;
case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
case ENCODER_ID_EXTERNAL_MVPU_FPGA:
return ENCODER_OBJECT_ID_MVPU_FPGA;
case ENCODER_ID_INTERNAL_DDI:
return ENCODER_OBJECT_ID_INTERNAL_DDI;
case ENCODER_ID_INTERNAL_UNIPHY:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
case ENCODER_ID_INTERNAL_UNIPHY1:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
case ENCODER_ID_INTERNAL_UNIPHY2:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
case ENCODER_ID_INTERNAL_UNIPHY3:
return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
case ENCODER_ID_INTERNAL_WIRELESS:
return ENCODER_OBJECT_ID_INTERNAL_VCE;
case ENCODER_ID_INTERNAL_VIRTUAL:
return ENCODER_OBJECT_ID_NONE;
case ENCODER_ID_UNKNOWN:
return ENCODER_OBJECT_ID_NONE;
default:
/* Invalid encoder id */
BREAK_TO_DEBUGGER();
return ENCODER_OBJECT_ID_NONE;
}
}

82
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h Normal file
View File

@ -0,0 +1,82 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
#define __DAL_COMMAND_TABLE_HELPER2_H__
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper2_dce112.h"
struct command_table_helper {
bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
uint8_t (*encoder_action_to_atom)(
enum bp_encoder_control_action action);
uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s,
bool enable_dp_audio);
bool (*engine_bp_to_atom)(enum engine_id engine_id,
uint32_t *atom_engine_id);
bool (*clock_source_id_to_atom)(enum clock_source_id id,
uint32_t *atom_pll_id);
bool (*clock_source_id_to_ref_clk_src)(
enum clock_source_id id,
uint32_t *ref_clk_src_id);
uint8_t (*transmitter_bp_to_atom)(enum transmitter t);
uint8_t (*encoder_id_to_atom)(enum encoder_id id);
uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(
enum clock_source_id id);
uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);
uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);
uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
uint8_t (*phy_id_to_atom)(enum transmitter t);
uint8_t (*disp_power_gating_action_to_atom)(
enum bp_pipe_control_action action);
bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
uint32_t *atom_clock_type);
uint8_t (*transmitter_color_depth_to_atom)(
enum transmitter_color_depth id);
};
bool dal_bios_parser_init_cmd_tbl_helper2(const struct command_table_helper **h,
enum dce_version dce);
bool dal_cmd_table_helper_controller_id_to_atom2(
enum controller_id id,
uint8_t *atom_id);
uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
enum signal_type s,
bool enable_dp_audio);
bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
enum clock_source_id id,
uint32_t *ref_clk_src_id);
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
enum transmitter t);
uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
enum encoder_id id);
#endif

364
drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c Normal file
View File

@ -0,0 +1,364 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/bios_parser_types.h"
#include "../command_table_helper.h"
static uint8_t phy_id_to_atom(enum transmitter t)
{
uint8_t atom_phy_id;
switch (t) {
case TRANSMITTER_UNIPHY_A:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
case TRANSMITTER_UNIPHY_B:
atom_phy_id = ATOM_PHY_ID_UNIPHYB;
break;
case TRANSMITTER_UNIPHY_C:
atom_phy_id = ATOM_PHY_ID_UNIPHYC;
break;
case TRANSMITTER_UNIPHY_D:
atom_phy_id = ATOM_PHY_ID_UNIPHYD;
break;
case TRANSMITTER_UNIPHY_E:
atom_phy_id = ATOM_PHY_ID_UNIPHYE;
break;
case TRANSMITTER_UNIPHY_F:
atom_phy_id = ATOM_PHY_ID_UNIPHYF;
break;
case TRANSMITTER_UNIPHY_G:
atom_phy_id = ATOM_PHY_ID_UNIPHYG;
break;
default:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
}
return atom_phy_id;
}
static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
{
uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
switch (s) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
break;
case SIGNAL_TYPE_LVDS:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
break;
default:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
}
return atom_dig_mode;
}
static uint8_t clock_source_id_to_atom_phy_clk_src_id(
enum clock_source_id id)
{
uint8_t atom_phy_clk_src_id = 0;
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
break;
case CLOCK_SOURCE_ID_PLL1:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
case CLOCK_SOURCE_ID_PLL2:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
break;
default:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
}
return atom_phy_clk_src_id >> 2;
}
static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
{
uint8_t atom_hpd_sel = 0;
switch (id) {
case HPD_SOURCEID1:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
break;
case HPD_SOURCEID2:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
break;
case HPD_SOURCEID3:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
break;
case HPD_SOURCEID4:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
break;
case HPD_SOURCEID5:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
break;
case HPD_SOURCEID6:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
break;
case HPD_SOURCEID_UNKNOWN:
default:
atom_hpd_sel = 0;
break;
}
return atom_hpd_sel >> 4;
}
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
uint8_t atom_dig_encoder_sel = 0;
switch (id) {
case ENGINE_ID_DIGA:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
break;
case ENGINE_ID_DIGB:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
break;
case ENGINE_ID_DIGC:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
break;
case ENGINE_ID_DIGD:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
break;
case ENGINE_ID_DIGE:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
break;
case ENGINE_ID_DIGF:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
break;
case ENGINE_ID_DIGG:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
break;
case ENGINE_ID_UNKNOWN:
/* No DIG_FRONT is associated to DIG_BACKEND */
atom_dig_encoder_sel = 0;
break;
default:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
break;
}
return 0;
}
static bool clock_source_id_to_atom(
enum clock_source_id id,
uint32_t *atom_pll_id)
{
bool result = true;
if (atom_pll_id != NULL)
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
*atom_pll_id = ATOM_PPLL0;
break;
case CLOCK_SOURCE_ID_PLL1:
*atom_pll_id = ATOM_PPLL1;
break;
case CLOCK_SOURCE_ID_PLL2:
*atom_pll_id = ATOM_PPLL2;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DFS:
*atom_pll_id = ATOM_EXT_PLL1;
break;
case CLOCK_SOURCE_ID_VCE:
/* for VCE encoding,
* we need to pass in ATOM_PPLL_INVALID
*/
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DP_DTO:
/* When programming DP DTO PLL ID should be invalid */
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_UNDEFINED:
/* Should not happen */
*atom_pll_id = ATOM_PPLL_INVALID;
result = false;
break;
default:
result = false;
break;
}
return result;
}
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
{
bool result = false;
if (atom_engine_id != NULL)
switch (id) {
case ENGINE_ID_DIGA:
*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGB:
*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGC:
*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGD:
*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGE:
*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGF:
*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGG:
*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DACA:
*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
result = true;
break;
default:
break;
}
return result;
}
static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
{
uint8_t atom_action = 0;
switch (action) {
case ENCODER_CONTROL_ENABLE:
atom_action = ATOM_ENABLE;
break;
case ENCODER_CONTROL_DISABLE:
atom_action = ATOM_DISABLE;
break;
case ENCODER_CONTROL_SETUP:
atom_action = ATOM_ENCODER_CMD_SETUP;
break;
case ENCODER_CONTROL_INIT:
atom_action = ATOM_ENCODER_INIT;
break;
default:
BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
break;
}
return atom_action;
}
static uint8_t disp_power_gating_action_to_atom(
enum bp_pipe_control_action action)
{
uint8_t atom_pipe_action = 0;
switch (action) {
case ASIC_PIPE_DISABLE:
atom_pipe_action = ATOM_DISABLE;
break;
case ASIC_PIPE_ENABLE:
atom_pipe_action = ATOM_ENABLE;
break;
case ASIC_PIPE_INIT:
atom_pipe_action = ATOM_INIT;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
return atom_pipe_action;
}
/* function table */
static const struct command_table_helper command_table_helper_funcs = {
.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
.encoder_action_to_atom = encoder_action_to_atom,
.engine_bp_to_atom = engine_bp_to_atom,
.clock_source_id_to_atom = clock_source_id_to_atom,
.clock_source_id_to_atom_phy_clk_src_id =
clock_source_id_to_atom_phy_clk_src_id,
.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
.hpd_sel_to_atom = hpd_sel_to_atom,
.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
.phy_id_to_atom = phy_id_to_atom,
.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
.assign_control_parameter = NULL,
.clock_source_id_to_ref_clk_src = NULL,
.transmitter_bp_to_atom = NULL,
.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
};
/*
* dal_cmd_tbl_helper_dce110_get_table
*
* @brief
* Initialize command table helper functions
*
* @param
* const struct command_table_helper **h - [out] struct of functions
*
*/
const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void)
{
return &command_table_helper_funcs;
}

34
drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER_DCE110_H__
#define __DAL_COMMAND_TABLE_HELPER_DCE110_H__
struct command_table_helper;
/* Initialize command table helper functions */
const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void);
#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */

418
drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c Normal file
View File

@ -0,0 +1,418 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/bios_parser_types.h"
#include "../command_table_helper2.h"
static uint8_t phy_id_to_atom(enum transmitter t)
{
uint8_t atom_phy_id;
switch (t) {
case TRANSMITTER_UNIPHY_A:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
case TRANSMITTER_UNIPHY_B:
atom_phy_id = ATOM_PHY_ID_UNIPHYB;
break;
case TRANSMITTER_UNIPHY_C:
atom_phy_id = ATOM_PHY_ID_UNIPHYC;
break;
case TRANSMITTER_UNIPHY_D:
atom_phy_id = ATOM_PHY_ID_UNIPHYD;
break;
case TRANSMITTER_UNIPHY_E:
atom_phy_id = ATOM_PHY_ID_UNIPHYE;
break;
case TRANSMITTER_UNIPHY_F:
atom_phy_id = ATOM_PHY_ID_UNIPHYF;
break;
case TRANSMITTER_UNIPHY_G:
atom_phy_id = ATOM_PHY_ID_UNIPHYG;
break;
default:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
}
return atom_phy_id;
}
static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
{
uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
switch (s) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
break;
default:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
break;
}
return atom_dig_mode;
}
static uint8_t clock_source_id_to_atom_phy_clk_src_id(
enum clock_source_id id)
{
uint8_t atom_phy_clk_src_id = 0;
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
break;
case CLOCK_SOURCE_ID_PLL1:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
case CLOCK_SOURCE_ID_PLL2:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
break;
default:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
}
return atom_phy_clk_src_id >> 2;
}
static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
{
uint8_t atom_hpd_sel = 0;
switch (id) {
case HPD_SOURCEID1:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
break;
case HPD_SOURCEID2:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
break;
case HPD_SOURCEID3:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
break;
case HPD_SOURCEID4:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
break;
case HPD_SOURCEID5:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
break;
case HPD_SOURCEID6:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
break;
case HPD_SOURCEID_UNKNOWN:
default:
atom_hpd_sel = 0;
break;
}
return atom_hpd_sel;
}
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
uint8_t atom_dig_encoder_sel = 0;
switch (id) {
case ENGINE_ID_DIGA:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
break;
case ENGINE_ID_DIGB:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
break;
case ENGINE_ID_DIGC:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
break;
case ENGINE_ID_DIGD:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
break;
case ENGINE_ID_DIGE:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
break;
case ENGINE_ID_DIGF:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
break;
case ENGINE_ID_DIGG:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
break;
case ENGINE_ID_UNKNOWN:
/* No DIG_FRONT is associated to DIG_BACKEND */
atom_dig_encoder_sel = 0;
break;
default:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
break;
}
return 0;
}
static bool clock_source_id_to_atom(
enum clock_source_id id,
uint32_t *atom_pll_id)
{
bool result = true;
if (atom_pll_id != NULL)
switch (id) {
case CLOCK_SOURCE_COMBO_PHY_PLL0:
*atom_pll_id = ATOM_COMBOPHY_PLL0;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL1:
*atom_pll_id = ATOM_COMBOPHY_PLL1;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL2:
*atom_pll_id = ATOM_COMBOPHY_PLL2;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL3:
*atom_pll_id = ATOM_COMBOPHY_PLL3;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL4:
*atom_pll_id = ATOM_COMBOPHY_PLL4;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL5:
*atom_pll_id = ATOM_COMBOPHY_PLL5;
break;
case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
*atom_pll_id = ATOM_PPLL0;
break;
case CLOCK_SOURCE_ID_DFS:
*atom_pll_id = ATOM_GCK_DFS;
break;
case CLOCK_SOURCE_ID_VCE:
*atom_pll_id = ATOM_DP_DTO;
break;
case CLOCK_SOURCE_ID_DP_DTO:
*atom_pll_id = ATOM_DP_DTO;
break;
case CLOCK_SOURCE_ID_UNDEFINED:
/* Should not happen */
*atom_pll_id = ATOM_PPLL_INVALID;
result = false;
break;
default:
result = false;
break;
}
return result;
}
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
{
bool result = false;
if (atom_engine_id != NULL)
switch (id) {
case ENGINE_ID_DIGA:
*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGB:
*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGC:
*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGD:
*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGE:
*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGF:
*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGG:
*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DACA:
*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
result = true;
break;
default:
break;
}
return result;
}
static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
{
uint8_t atom_action = 0;
switch (action) {
case ENCODER_CONTROL_ENABLE:
atom_action = ATOM_ENABLE;
break;
case ENCODER_CONTROL_DISABLE:
atom_action = ATOM_DISABLE;
break;
case ENCODER_CONTROL_SETUP:
atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
break;
case ENCODER_CONTROL_INIT:
atom_action = ATOM_ENCODER_INIT;
break;
default:
BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
break;
}
return atom_action;
}
static uint8_t disp_power_gating_action_to_atom(
enum bp_pipe_control_action action)
{
uint8_t atom_pipe_action = 0;
switch (action) {
case ASIC_PIPE_DISABLE:
atom_pipe_action = ATOM_DISABLE;
break;
case ASIC_PIPE_ENABLE:
atom_pipe_action = ATOM_ENABLE;
break;
case ASIC_PIPE_INIT:
atom_pipe_action = ATOM_INIT;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
return atom_pipe_action;
}
static bool dc_clock_type_to_atom(
enum bp_dce_clock_type id,
uint32_t *atom_clock_type)
{
bool retCode = true;
if (atom_clock_type != NULL) {
switch (id) {
case DCECLOCK_TYPE_DISPLAY_CLOCK:
*atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
break;
case DCECLOCK_TYPE_DPREFCLK:
*atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
}
return retCode;
}
static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
{
uint8_t atomColorDepth = 0;
switch (id) {
case TRANSMITTER_COLOR_DEPTH_24:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
break;
case TRANSMITTER_COLOR_DEPTH_30:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
break;
case TRANSMITTER_COLOR_DEPTH_36:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
break;
case TRANSMITTER_COLOR_DEPTH_48:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
return atomColorDepth;
}
/* function table */
static const struct command_table_helper command_table_helper_funcs = {
.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2,
.encoder_action_to_atom = encoder_action_to_atom,
.engine_bp_to_atom = engine_bp_to_atom,
.clock_source_id_to_atom = clock_source_id_to_atom,
.clock_source_id_to_atom_phy_clk_src_id =
clock_source_id_to_atom_phy_clk_src_id,
.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
.hpd_sel_to_atom = hpd_sel_to_atom,
.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
.phy_id_to_atom = phy_id_to_atom,
.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
.clock_source_id_to_ref_clk_src = NULL,
.transmitter_bp_to_atom = NULL,
.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2,
.encoder_mode_bp_to_atom =
dal_cmd_table_helper_encoder_mode_bp_to_atom2,
.dc_clock_type_to_atom = dc_clock_type_to_atom,
.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
};
/*
* dal_cmd_tbl_helper_dce110_get_table
*
* @brief
* Initialize command table helper functions
*
* @param
* const struct command_table_helper **h - [out] struct of functions
*
*/
const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void)
{
return &command_table_helper_funcs;
}

34
drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER2_DCE112_H__
#define __DAL_COMMAND_TABLE_HELPER2_DCE112_H__
struct command_table_helper;
/* Initialize command table helper functions */
const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void);
#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */

418
drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c Normal file
View File

@ -0,0 +1,418 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/bios_parser_types.h"
#include "../command_table_helper.h"
static uint8_t phy_id_to_atom(enum transmitter t)
{
uint8_t atom_phy_id;
switch (t) {
case TRANSMITTER_UNIPHY_A:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
case TRANSMITTER_UNIPHY_B:
atom_phy_id = ATOM_PHY_ID_UNIPHYB;
break;
case TRANSMITTER_UNIPHY_C:
atom_phy_id = ATOM_PHY_ID_UNIPHYC;
break;
case TRANSMITTER_UNIPHY_D:
atom_phy_id = ATOM_PHY_ID_UNIPHYD;
break;
case TRANSMITTER_UNIPHY_E:
atom_phy_id = ATOM_PHY_ID_UNIPHYE;
break;
case TRANSMITTER_UNIPHY_F:
atom_phy_id = ATOM_PHY_ID_UNIPHYF;
break;
case TRANSMITTER_UNIPHY_G:
atom_phy_id = ATOM_PHY_ID_UNIPHYG;
break;
default:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
}
return atom_phy_id;
}
static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
{
uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
switch (s) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
break;
default:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
break;
}
return atom_dig_mode;
}
static uint8_t clock_source_id_to_atom_phy_clk_src_id(
enum clock_source_id id)
{
uint8_t atom_phy_clk_src_id = 0;
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
break;
case CLOCK_SOURCE_ID_PLL1:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
case CLOCK_SOURCE_ID_PLL2:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
break;
default:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
}
return atom_phy_clk_src_id >> 2;
}
static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
{
uint8_t atom_hpd_sel = 0;
switch (id) {
case HPD_SOURCEID1:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
break;
case HPD_SOURCEID2:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
break;
case HPD_SOURCEID3:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
break;
case HPD_SOURCEID4:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
break;
case HPD_SOURCEID5:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
break;
case HPD_SOURCEID6:
atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
break;
case HPD_SOURCEID_UNKNOWN:
default:
atom_hpd_sel = 0;
break;
}
return atom_hpd_sel;
}
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
uint8_t atom_dig_encoder_sel = 0;
switch (id) {
case ENGINE_ID_DIGA:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
break;
case ENGINE_ID_DIGB:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
break;
case ENGINE_ID_DIGC:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
break;
case ENGINE_ID_DIGD:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
break;
case ENGINE_ID_DIGE:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
break;
case ENGINE_ID_DIGF:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
break;
case ENGINE_ID_DIGG:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
break;
case ENGINE_ID_UNKNOWN:
/* No DIG_FRONT is associated to DIG_BACKEND */
atom_dig_encoder_sel = 0;
break;
default:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
break;
}
return 0;
}
static bool clock_source_id_to_atom(
enum clock_source_id id,
uint32_t *atom_pll_id)
{
bool result = true;
if (atom_pll_id != NULL)
switch (id) {
case CLOCK_SOURCE_COMBO_PHY_PLL0:
*atom_pll_id = ATOM_COMBOPHY_PLL0;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL1:
*atom_pll_id = ATOM_COMBOPHY_PLL1;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL2:
*atom_pll_id = ATOM_COMBOPHY_PLL2;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL3:
*atom_pll_id = ATOM_COMBOPHY_PLL3;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL4:
*atom_pll_id = ATOM_COMBOPHY_PLL4;
break;
case CLOCK_SOURCE_COMBO_PHY_PLL5:
*atom_pll_id = ATOM_COMBOPHY_PLL5;
break;
case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
*atom_pll_id = ATOM_PPLL0;
break;
case CLOCK_SOURCE_ID_DFS:
*atom_pll_id = ATOM_GCK_DFS;
break;
case CLOCK_SOURCE_ID_VCE:
*atom_pll_id = ATOM_DP_DTO;
break;
case CLOCK_SOURCE_ID_DP_DTO:
*atom_pll_id = ATOM_DP_DTO;
break;
case CLOCK_SOURCE_ID_UNDEFINED:
/* Should not happen */
*atom_pll_id = ATOM_PPLL_INVALID;
result = false;
break;
default:
result = false;
break;
}
return result;
}
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
{
bool result = false;
if (atom_engine_id != NULL)
switch (id) {
case ENGINE_ID_DIGA:
*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGB:
*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGC:
*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGD:
*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGE:
*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGF:
*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGG:
*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DACA:
*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
result = true;
break;
default:
break;
}
return result;
}
static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
{
uint8_t atom_action = 0;
switch (action) {
case ENCODER_CONTROL_ENABLE:
atom_action = ATOM_ENABLE;
break;
case ENCODER_CONTROL_DISABLE:
atom_action = ATOM_DISABLE;
break;
case ENCODER_CONTROL_SETUP:
atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
break;
case ENCODER_CONTROL_INIT:
atom_action = ATOM_ENCODER_INIT;
break;
default:
BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
break;
}
return atom_action;
}
static uint8_t disp_power_gating_action_to_atom(
enum bp_pipe_control_action action)
{
uint8_t atom_pipe_action = 0;
switch (action) {
case ASIC_PIPE_DISABLE:
atom_pipe_action = ATOM_DISABLE;
break;
case ASIC_PIPE_ENABLE:
atom_pipe_action = ATOM_ENABLE;
break;
case ASIC_PIPE_INIT:
atom_pipe_action = ATOM_INIT;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
return atom_pipe_action;
}
static bool dc_clock_type_to_atom(
enum bp_dce_clock_type id,
uint32_t *atom_clock_type)
{
bool retCode = true;
if (atom_clock_type != NULL) {
switch (id) {
case DCECLOCK_TYPE_DISPLAY_CLOCK:
*atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
break;
case DCECLOCK_TYPE_DPREFCLK:
*atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
}
return retCode;
}
static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
{
uint8_t atomColorDepth = 0;
switch (id) {
case TRANSMITTER_COLOR_DEPTH_24:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
break;
case TRANSMITTER_COLOR_DEPTH_30:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
break;
case TRANSMITTER_COLOR_DEPTH_36:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
break;
case TRANSMITTER_COLOR_DEPTH_48:
atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
break;
default:
ASSERT_CRITICAL(false); /* Unhandle action in driver! */
break;
}
return atomColorDepth;
}
/* function table */
static const struct command_table_helper command_table_helper_funcs = {
.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
.encoder_action_to_atom = encoder_action_to_atom,
.engine_bp_to_atom = engine_bp_to_atom,
.clock_source_id_to_atom = clock_source_id_to_atom,
.clock_source_id_to_atom_phy_clk_src_id =
clock_source_id_to_atom_phy_clk_src_id,
.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
.hpd_sel_to_atom = hpd_sel_to_atom,
.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
.phy_id_to_atom = phy_id_to_atom,
.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
.assign_control_parameter = NULL,
.clock_source_id_to_ref_clk_src = NULL,
.transmitter_bp_to_atom = NULL,
.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
.dc_clock_type_to_atom = dc_clock_type_to_atom,
.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
};
/*
* dal_cmd_tbl_helper_dce110_get_table
*
* @brief
* Initialize command table helper functions
*
* @param
* const struct command_table_helper **h - [out] struct of functions
*
*/
const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table(void)
{
return &command_table_helper_funcs;
}

34
drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER_DCE112_H__
#define __DAL_COMMAND_TABLE_HELPER_DCE112_H__
struct command_table_helper;
/* Initialize command table helper functions */
const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table(void);
#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */

354
drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c Normal file
View File

@ -0,0 +1,354 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "atom.h"
#include "include/grph_object_id.h"
#include "include/grph_object_defs.h"
#include "include/bios_parser_types.h"
#include "../command_table_helper.h"
static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
{
uint8_t atom_action = 0;
switch (action) {
case ENCODER_CONTROL_ENABLE:
atom_action = ATOM_ENABLE;
break;
case ENCODER_CONTROL_DISABLE:
atom_action = ATOM_DISABLE;
break;
case ENCODER_CONTROL_SETUP:
atom_action = ATOM_ENCODER_CMD_SETUP;
break;
case ENCODER_CONTROL_INIT:
atom_action = ATOM_ENCODER_INIT;
break;
default:
BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
break;
}
return atom_action;
}
static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
{
bool result = false;
if (atom_engine_id != NULL)
switch (id) {
case ENGINE_ID_DIGA:
*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGB:
*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGC:
*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGD:
*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGE:
*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGF:
*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DIGG:
*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
result = true;
break;
case ENGINE_ID_DACA:
*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
result = true;
break;
default:
break;
}
return result;
}
static bool clock_source_id_to_atom(
enum clock_source_id id,
uint32_t *atom_pll_id)
{
bool result = true;
if (atom_pll_id != NULL)
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
*atom_pll_id = ATOM_PPLL0;
break;
case CLOCK_SOURCE_ID_PLL1:
*atom_pll_id = ATOM_PPLL1;
break;
case CLOCK_SOURCE_ID_PLL2:
*atom_pll_id = ATOM_PPLL2;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DFS:
*atom_pll_id = ATOM_EXT_PLL1;
break;
case CLOCK_SOURCE_ID_VCE:
/* for VCE encoding,
* we need to pass in ATOM_PPLL_INVALID
*/
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DP_DTO:
/* When programming DP DTO PLL ID should be invalid */
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_UNDEFINED:
BREAK_TO_DEBUGGER(); /* check when this will happen! */
*atom_pll_id = ATOM_PPLL_INVALID;
result = false;
break;
default:
result = false;
break;
}
return result;
}
static uint8_t clock_source_id_to_atom_phy_clk_src_id(
enum clock_source_id id)
{
uint8_t atom_phy_clk_src_id = 0;
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
break;
case CLOCK_SOURCE_ID_PLL1:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
case CLOCK_SOURCE_ID_PLL2:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
break;
default:
atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
break;
}
return atom_phy_clk_src_id >> 2;
}
static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
{
uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
switch (s) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
break;
case SIGNAL_TYPE_LVDS:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
break;
default:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
}
return atom_dig_mode;
}
static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
{
uint8_t atom_hpd_sel = 0;
switch (id) {
case HPD_SOURCEID1:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
break;
case HPD_SOURCEID2:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
break;
case HPD_SOURCEID3:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
break;
case HPD_SOURCEID4:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
break;
case HPD_SOURCEID5:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
break;
case HPD_SOURCEID6:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
break;
case HPD_SOURCEID_UNKNOWN:
default:
atom_hpd_sel = 0;
break;
}
return atom_hpd_sel >> 4;
}
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
uint8_t atom_dig_encoder_sel = 0;
switch (id) {
case ENGINE_ID_DIGA:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
break;
case ENGINE_ID_DIGB:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
break;
case ENGINE_ID_DIGC:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
break;
case ENGINE_ID_DIGD:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
break;
case ENGINE_ID_DIGE:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
break;
case ENGINE_ID_DIGF:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
break;
case ENGINE_ID_DIGG:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
break;
default:
atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
break;
}
return atom_dig_encoder_sel;
}
static uint8_t phy_id_to_atom(enum transmitter t)
{
uint8_t atom_phy_id;
switch (t) {
case TRANSMITTER_UNIPHY_A:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
case TRANSMITTER_UNIPHY_B:
atom_phy_id = ATOM_PHY_ID_UNIPHYB;
break;
case TRANSMITTER_UNIPHY_C:
atom_phy_id = ATOM_PHY_ID_UNIPHYC;
break;
case TRANSMITTER_UNIPHY_D:
atom_phy_id = ATOM_PHY_ID_UNIPHYD;
break;
case TRANSMITTER_UNIPHY_E:
atom_phy_id = ATOM_PHY_ID_UNIPHYE;
break;
case TRANSMITTER_UNIPHY_F:
atom_phy_id = ATOM_PHY_ID_UNIPHYF;
break;
case TRANSMITTER_UNIPHY_G:
atom_phy_id = ATOM_PHY_ID_UNIPHYG;
break;
default:
atom_phy_id = ATOM_PHY_ID_UNIPHYA;
break;
}
return atom_phy_id;
}
static uint8_t disp_power_gating_action_to_atom(
enum bp_pipe_control_action action)
{
uint8_t atom_pipe_action = 0;
switch (action) {
case ASIC_PIPE_DISABLE:
atom_pipe_action = ATOM_DISABLE;
break;
case ASIC_PIPE_ENABLE:
atom_pipe_action = ATOM_ENABLE;
break;
case ASIC_PIPE_INIT:
atom_pipe_action = ATOM_INIT;
break;
default:
BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
break;
}
return atom_pipe_action;
}
static const struct command_table_helper command_table_helper_funcs = {
.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
.encoder_action_to_atom = encoder_action_to_atom,
.engine_bp_to_atom = engine_bp_to_atom,
.clock_source_id_to_atom = clock_source_id_to_atom,
.clock_source_id_to_atom_phy_clk_src_id =
clock_source_id_to_atom_phy_clk_src_id,
.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
.hpd_sel_to_atom = hpd_sel_to_atom,
.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
.phy_id_to_atom = phy_id_to_atom,
.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
.assign_control_parameter =
dal_cmd_table_helper_assign_control_parameter,
.clock_source_id_to_ref_clk_src =
dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
.encoder_mode_bp_to_atom =
dal_cmd_table_helper_encoder_mode_bp_to_atom,
};
const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void)
{
return &command_table_helper_funcs;
}

33
drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_COMMAND_TABLE_HELPER_DCE80_H__
#define __DAL_COMMAND_TABLE_HELPER_DCE80_H__
struct command_table_helper;
const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void);
#endif

18
drivers/gpu/drm/amd/display/dc/calcs/Makefile Normal file
View File

@ -0,0 +1,18 @@
#
# Makefile for the 'calcs' sub-component of DAL.
# It calculates Bandwidth and Watermarks values for HW programming
#
CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4 -Wno-tautological-compare
BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
ifdef CONFIG_DRM_AMD_DC_DCN1_0
BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
endif
AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
AMD_DISPLAY_FILES += $(AMD_DAL_BW_CALCS)

191
drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c Normal file
View File

@ -0,0 +1,191 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "bw_fixed.h"
#define MIN_I64 \
(int64_t)(-(1LL << 63))
#define MAX_I64 \
(int64_t)((1ULL << 63) - 1)
#define FRACTIONAL_PART_MASK \
((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1)
#define GET_FRACTIONAL_PART(x) \
(FRACTIONAL_PART_MASK & (x))
static uint64_t abs_i64(int64_t arg)
{
if (arg >= 0)
return (uint64_t)(arg);
else
return (uint64_t)(-arg);
}
struct bw_fixed bw_int_to_fixed_nonconst(int64_t value)
{
struct bw_fixed res;
ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);
res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART;
return res;
}
struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t denominator)
{
struct bw_fixed res;
bool arg1_negative = numerator < 0;
bool arg2_negative = denominator < 0;
uint64_t arg1_value;
uint64_t arg2_value;
uint64_t remainder;
/* determine integer part */
uint64_t res_value;
ASSERT(denominator != 0);
arg1_value = abs_i64(numerator);
arg2_value = abs_i64(denominator);
res_value = div64_u64_rem(arg1_value, arg2_value, &remainder);
ASSERT(res_value <= BW_FIXED_MAX_I32);
/* determine fractional part */
{
uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART;
do
{
remainder <<= 1;
res_value <<= 1;
if (remainder >= arg2_value)
{
res_value |= 1;
remainder -= arg2_value;
}
} while (--i != 0);
}
/* round up LSB */
{
uint64_t summand = (remainder << 1) >= arg2_value;
ASSERT(res_value <= MAX_I64 - summand);
res_value += summand;
}
res.value = (int64_t)(res_value);
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
return res;
}
struct bw_fixed bw_floor2(
const struct bw_fixed arg,
const struct bw_fixed significance)
{
struct bw_fixed result;
int64_t multiplicand;
multiplicand = div64_s64(arg.value, abs_i64(significance.value));
result.value = abs_i64(significance.value) * multiplicand;
ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
return result;
}
struct bw_fixed bw_ceil2(
const struct bw_fixed arg,
const struct bw_fixed significance)
{
struct bw_fixed result;
int64_t multiplicand;
multiplicand = div64_s64(arg.value, abs_i64(significance.value));
result.value = abs_i64(significance.value) * multiplicand;
if (abs_i64(result.value) < abs_i64(arg.value)) {
if (arg.value < 0)
result.value -= abs_i64(significance.value);
else
result.value += abs_i64(significance.value);
}
return result;
}
struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
{
struct bw_fixed res;
bool arg1_negative = arg1.value < 0;
bool arg2_negative = arg2.value < 0;
uint64_t arg1_value = abs_i64(arg1.value);
uint64_t arg2_value = abs_i64(arg2.value);
uint64_t arg1_int = BW_FIXED_GET_INTEGER_PART(arg1_value);
uint64_t arg2_int = BW_FIXED_GET_INTEGER_PART(arg2_value);
uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
uint64_t tmp;
res.value = arg1_int * arg2_int;
ASSERT(res.value <= BW_FIXED_MAX_I32);
res.value <<= BW_FIXED_BITS_PER_FRACTIONAL_PART;
tmp = arg1_int * arg2_fra;
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
res.value += tmp;
tmp = arg2_int * arg1_fra;
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
res.value += tmp;
tmp = arg1_fra * arg2_fra;
tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
res.value += tmp;
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
return res;
}

197
drivers/gpu/drm/amd/display/dc/calcs/custom_float.c Normal file
View File

@ -0,0 +1,197 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "custom_float.h"
static bool build_custom_float(
struct fixed31_32 value,
const struct custom_float_format *format,
bool *negative,
uint32_t *mantissa,
uint32_t *exponenta)
{
uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
const struct fixed31_32 mantissa_constant_plus_max_fraction =
dal_fixed31_32_from_fraction(
(1LL << (format->mantissa_bits + 1)) - 1,
1LL << format->mantissa_bits);
struct fixed31_32 mantiss;
if (dal_fixed31_32_eq(
value,
dal_fixed31_32_zero)) {
*negative = false;
*mantissa = 0;
*exponenta = 0;
return true;
}
if (dal_fixed31_32_lt(
value,
dal_fixed31_32_zero)) {
*negative = format->sign;
value = dal_fixed31_32_neg(value);
} else {
*negative = false;
}
if (dal_fixed31_32_lt(
value,
dal_fixed31_32_one)) {
uint32_t i = 1;
do {
value = dal_fixed31_32_shl(value, 1);
++i;
} while (dal_fixed31_32_lt(
value,
dal_fixed31_32_one));
--i;
if (exp_offset <= i) {
*mantissa = 0;
*exponenta = 0;
return true;
}
*exponenta = exp_offset - i;
} else if (dal_fixed31_32_le(
mantissa_constant_plus_max_fraction,
value)) {
uint32_t i = 1;
do {
value = dal_fixed31_32_shr(value, 1);
++i;
} while (dal_fixed31_32_lt(
mantissa_constant_plus_max_fraction,
value));
*exponenta = exp_offset + i - 1;
} else {
*exponenta = exp_offset;
}
mantiss = dal_fixed31_32_sub(
value,
dal_fixed31_32_one);
if (dal_fixed31_32_lt(
mantiss,
dal_fixed31_32_zero) ||
dal_fixed31_32_lt(
dal_fixed31_32_one,
mantiss))
mantiss = dal_fixed31_32_zero;
else
mantiss = dal_fixed31_32_shl(
mantiss,
format->mantissa_bits);
*mantissa = dal_fixed31_32_floor(mantiss);
return true;
}
static bool setup_custom_float(
const struct custom_float_format *format,
bool negative,
uint32_t mantissa,
uint32_t exponenta,
uint32_t *result)
{
uint32_t i = 0;
uint32_t j = 0;
uint32_t value = 0;
/* verification code:
* once calculation is ok we can remove it
*/
const uint32_t mantissa_mask =
(1 << (format->mantissa_bits + 1)) - 1;
const uint32_t exponenta_mask =
(1 << (format->exponenta_bits + 1)) - 1;
if (mantissa & ~mantissa_mask) {
BREAK_TO_DEBUGGER();
mantissa = mantissa_mask;
}
if (exponenta & ~exponenta_mask) {
BREAK_TO_DEBUGGER();
exponenta = exponenta_mask;
}
/* end of verification code */
while (i < format->mantissa_bits) {
uint32_t mask = 1 << i;
if (mantissa & mask)
value |= mask;
++i;
}
while (j < format->exponenta_bits) {
uint32_t mask = 1 << j;
if (exponenta & mask)
value |= mask << i;
++j;
}
if (negative && format->sign)
value |= 1 << (i + j);
*result = value;
return true;
}
bool convert_to_custom_float_format(
struct fixed31_32 value,
const struct custom_float_format *format,
uint32_t *result)
{
uint32_t mantissa;
uint32_t exponenta;
bool negative;
return build_custom_float(
value, format, &negative, &mantissa, &exponenta) &&
setup_custom_float(
format, negative, mantissa, exponenta, result);
}

3257
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c Normal file
View File

File diff suppressed because it is too large Load Diff

1899
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c Normal file
View File

File diff suppressed because it is too large Load Diff

37
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCN_CALC_AUTO_H_
#define _DCN_CALC_AUTO_H_
#include "dcn_calcs.h"
void scaler_settings_calculation(struct dcn_bw_internal_vars *v);
void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v);
void display_pipe_configuration(struct dcn_bw_internal_vars *v);
void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
struct dcn_bw_internal_vars *v);
#endif /* _DCN_CALC_AUTO_H_ */

120
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c Normal file
View File

@ -0,0 +1,120 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dcn_calc_math.h"
float dcn_bw_mod(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 - arg1 * ((int) (arg1 / arg2));
}
float dcn_bw_min2(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 < arg2 ? arg1 : arg2;
}
unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 > arg2 ? arg1 : arg2;
}
float dcn_bw_max2(const float arg1, const float arg2)
{
if (arg1 != arg1)
return arg2;
if (arg2 != arg2)
return arg1;
return arg1 > arg2 ? arg1 : arg2;
}
float dcn_bw_floor2(const float arg, const float significance)
{
if (significance == 0)
return 0;
return ((int) (arg / significance)) * significance;
}
float dcn_bw_ceil2(const float arg, const float significance)
{
float flr = dcn_bw_floor2(arg, significance);
if (significance == 0)
return 0;
return flr + 0.00001 >= arg ? arg : flr + significance;
}
float dcn_bw_max3(float v1, float v2, float v3)
{
return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2);
}
float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)
{
return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
}
float dcn_bw_pow(float a, float exp)
{
float temp;
/*ASSERT(exp == (int)exp);*/
if ((int)exp == 0)
return 1;
temp = dcn_bw_pow(a, (int)(exp / 2));
if (((int)exp % 2) == 0) {
return temp * temp;
} else {
if ((int)exp > 0)
return a * temp * temp;
else
return (temp * temp) / a;
}
}
float dcn_bw_log(float a, float b)
{
int * const exp_ptr = (int *)(&a);
int x = *exp_ptr;
const int log_2 = ((x >> 23) & 255) - 128;
x &= ~(255 << 23);
x += 127 << 23;
*exp_ptr = x;
a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3;
if (b > 2.00001 || b < 1.99999)
return (a + log_2) / dcn_bw_log(b, 2);
else
return (a + log_2);
}

40
drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCN_CALC_MATH_H_
#define _DCN_CALC_MATH_H_
float dcn_bw_mod(const float arg1, const float arg2);
float dcn_bw_min2(const float arg1, const float arg2);
unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2);
float dcn_bw_max2(const float arg1, const float arg2);
float dcn_bw_floor2(const float arg, const float significance);
float dcn_bw_ceil2(const float arg, const float significance);
float dcn_bw_max3(float v1, float v2, float v3);
float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
float dcn_bw_pow(float a, float exp);
float dcn_bw_log(float a, float b);
#endif /* _DCN_CALC_MATH_H_ */

1626
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c Normal file
View File

File diff suppressed because it is too large Load Diff

1677
drivers/gpu/drm/amd/display/dc/core/dc.c Normal file
View File

File diff suppressed because it is too large Load Diff

359
drivers/gpu/drm/amd/display/dc/core/dc_debug.c Normal file
View File

@ -0,0 +1,359 @@
/*
* dc_debug.c
*
* Created on: Nov 3, 2016
* Author: yonsun
*/
#include "dm_services.h"
#include "dc.h"
#include "core_status.h"
#include "core_types.h"
#include "hw_sequencer.h"
#include "resource.h"
#define SURFACE_TRACE(...) do {\
if (dc->debug.surface_trace) \
dm_logger_write(logger, \
LOG_IF_TRACE, \
##__VA_ARGS__); \
} while (0)
#define TIMING_TRACE(...) do {\
if (dc->debug.timing_trace) \
dm_logger_write(logger, \
LOG_SYNC, \
##__VA_ARGS__); \
} while (0)
#define CLOCK_TRACE(...) do {\
if (dc->debug.clock_trace) \
dm_logger_write(logger, \
LOG_BANDWIDTH_CALCS, \
##__VA_ARGS__); \
} while (0)
void pre_surface_trace(
struct dc *dc,
const struct dc_plane_state *const *plane_states,
int surface_count)
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < surface_count; i++) {
const struct dc_plane_state *plane_state = plane_states[i];
SURFACE_TRACE("Planes %d:\n", i);
SURFACE_TRACE(
"plane_state->visible = %d;\n"
"plane_state->flip_immediate = %d;\n"
"plane_state->address.type = %d;\n"
"plane_state->address.grph.addr.quad_part = 0x%X;\n"
"plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
"plane_state->scaling_quality.h_taps = %d;\n"
"plane_state->scaling_quality.v_taps = %d;\n"
"plane_state->scaling_quality.h_taps_c = %d;\n"
"plane_state->scaling_quality.v_taps_c = %d;\n",
plane_state->visible,
plane_state->flip_immediate,
plane_state->address.type,
plane_state->address.grph.addr.quad_part,
plane_state->address.grph.meta_addr.quad_part,
plane_state->scaling_quality.h_taps,
plane_state->scaling_quality.v_taps,
plane_state->scaling_quality.h_taps_c,
plane_state->scaling_quality.v_taps_c);
SURFACE_TRACE(
"plane_state->src_rect.x = %d;\n"
"plane_state->src_rect.y = %d;\n"
"plane_state->src_rect.width = %d;\n"
"plane_state->src_rect.height = %d;\n"
"plane_state->dst_rect.x = %d;\n"
"plane_state->dst_rect.y = %d;\n"
"plane_state->dst_rect.width = %d;\n"
"plane_state->dst_rect.height = %d;\n"
"plane_state->clip_rect.x = %d;\n"
"plane_state->clip_rect.y = %d;\n"
"plane_state->clip_rect.width = %d;\n"
"plane_state->clip_rect.height = %d;\n",
plane_state->src_rect.x,
plane_state->src_rect.y,
plane_state->src_rect.width,
plane_state->src_rect.height,
plane_state->dst_rect.x,
plane_state->dst_rect.y,
plane_state->dst_rect.width,
plane_state->dst_rect.height,
plane_state->clip_rect.x,
plane_state->clip_rect.y,
plane_state->clip_rect.width,
plane_state->clip_rect.height);
SURFACE_TRACE(
"plane_state->plane_size.grph.surface_size.x = %d;\n"
"plane_state->plane_size.grph.surface_size.y = %d;\n"
"plane_state->plane_size.grph.surface_size.width = %d;\n"
"plane_state->plane_size.grph.surface_size.height = %d;\n"
"plane_state->plane_size.grph.surface_pitch = %d;\n",
plane_state->plane_size.grph.surface_size.x,
plane_state->plane_size.grph.surface_size.y,
plane_state->plane_size.grph.surface_size.width,
plane_state->plane_size.grph.surface_size.height,
plane_state->plane_size.grph.surface_pitch);
SURFACE_TRACE(
"plane_state->tiling_info.gfx8.num_banks = %d;\n"
"plane_state->tiling_info.gfx8.bank_width = %d;\n"
"plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
"plane_state->tiling_info.gfx8.bank_height = %d;\n"
"plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
"plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_split = %d;\n"
"plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
"plane_state->tiling_info.gfx8.tile_mode = %d;\n"
"plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
plane_state->tiling_info.gfx8.num_banks,
plane_state->tiling_info.gfx8.bank_width,
plane_state->tiling_info.gfx8.bank_width_c,
plane_state->tiling_info.gfx8.bank_height,
plane_state->tiling_info.gfx8.bank_height_c,
plane_state->tiling_info.gfx8.tile_aspect,
plane_state->tiling_info.gfx8.tile_aspect_c,
plane_state->tiling_info.gfx8.tile_split,
plane_state->tiling_info.gfx8.tile_split_c,
plane_state->tiling_info.gfx8.tile_mode,
plane_state->tiling_info.gfx8.tile_mode_c);
SURFACE_TRACE(
"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
"plane_state->tiling_info.gfx8.array_mode = %d;\n"
"plane_state->color_space = %d;\n"
"plane_state->dcc.enable = %d;\n"
"plane_state->format = %d;\n"
"plane_state->rotation = %d;\n"
"plane_state->stereo_format = %d;\n",
plane_state->tiling_info.gfx8.pipe_config,
plane_state->tiling_info.gfx8.array_mode,
plane_state->color_space,
plane_state->dcc.enable,
plane_state->format,
plane_state->rotation,
plane_state->stereo_format);
SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
plane_state->tiling_info.gfx9.swizzle);
SURFACE_TRACE("\n");
}
SURFACE_TRACE("\n");
}
void update_surface_trace(
struct dc *dc,
const struct dc_surface_update *updates,
int surface_count)
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < surface_count; i++) {
const struct dc_surface_update *update = &updates[i];
SURFACE_TRACE("Update %d\n", i);
if (update->flip_addr) {
SURFACE_TRACE("flip_addr->address.type = %d;\n"
"flip_addr->address.grph.addr.quad_part = 0x%X;\n"
"flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
"flip_addr->flip_immediate = %d;\n",
update->flip_addr->address.type,
update->flip_addr->address.grph.addr.quad_part,
update->flip_addr->address.grph.meta_addr.quad_part,
update->flip_addr->flip_immediate);
}
if (update->plane_info) {
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
"plane_info->format = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
"plane_info->plane_size.grph.surface_size.width = %d;\n"
"plane_info->plane_size.grph.surface_size.x = %d;\n"
"plane_info->plane_size.grph.surface_size.y = %d;\n"
"plane_info->rotation = %d;\n",
update->plane_info->color_space,
update->plane_info->format,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
update->plane_info->plane_size.grph.surface_size.width,
update->plane_info->plane_size.grph.surface_size.x,
update->plane_info->plane_size.grph.surface_size.y,
update->plane_info->rotation,
update->plane_info->stereo_format);
SURFACE_TRACE(
"plane_info->tiling_info.gfx8.num_banks = %d;\n"
"plane_info->tiling_info.gfx8.bank_width = %d;\n"
"plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
"plane_info->tiling_info.gfx8.bank_height = %d;\n"
"plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
"plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
"plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
"plane_info->tiling_info.gfx8.tile_split = %d;\n"
"plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
"plane_info->tiling_info.gfx8.tile_mode = %d;\n"
"plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
update->plane_info->tiling_info.gfx8.num_banks,
update->plane_info->tiling_info.gfx8.bank_width,
update->plane_info->tiling_info.gfx8.bank_width_c,
update->plane_info->tiling_info.gfx8.bank_height,
update->plane_info->tiling_info.gfx8.bank_height_c,
update->plane_info->tiling_info.gfx8.tile_aspect,
update->plane_info->tiling_info.gfx8.tile_aspect_c,
update->plane_info->tiling_info.gfx8.tile_split,
update->plane_info->tiling_info.gfx8.tile_split_c,
update->plane_info->tiling_info.gfx8.tile_mode,
update->plane_info->tiling_info.gfx8.tile_mode_c);
SURFACE_TRACE(
"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
"plane_info->tiling_info.gfx8.array_mode = %d;\n"
"plane_info->visible = %d;\n"
"plane_info->per_pixel_alpha = %d;\n",
update->plane_info->tiling_info.gfx8.pipe_config,
update->plane_info->tiling_info.gfx8.array_mode,
update->plane_info->visible,
update->plane_info->per_pixel_alpha);
SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
update->plane_info->tiling_info.gfx9.swizzle);
}
if (update->scaling_info) {
SURFACE_TRACE(
"scaling_info->src_rect.x = %d;\n"
"scaling_info->src_rect.y = %d;\n"
"scaling_info->src_rect.width = %d;\n"
"scaling_info->src_rect.height = %d;\n"
"scaling_info->dst_rect.x = %d;\n"
"scaling_info->dst_rect.y = %d;\n"
"scaling_info->dst_rect.width = %d;\n"
"scaling_info->dst_rect.height = %d;\n"
"scaling_info->clip_rect.x = %d;\n"
"scaling_info->clip_rect.y = %d;\n"
"scaling_info->clip_rect.width = %d;\n"
"scaling_info->clip_rect.height = %d;\n"
"scaling_info->scaling_quality.h_taps = %d;\n"
"scaling_info->scaling_quality.v_taps = %d;\n"
"scaling_info->scaling_quality.h_taps_c = %d;\n"
"scaling_info->scaling_quality.v_taps_c = %d;\n",
update->scaling_info->src_rect.x,
update->scaling_info->src_rect.y,
update->scaling_info->src_rect.width,
update->scaling_info->src_rect.height,
update->scaling_info->dst_rect.x,
update->scaling_info->dst_rect.y,
update->scaling_info->dst_rect.width,
update->scaling_info->dst_rect.height,
update->scaling_info->clip_rect.x,
update->scaling_info->clip_rect.y,
update->scaling_info->clip_rect.width,
update->scaling_info->clip_rect.height,
update->scaling_info->scaling_quality.h_taps,
update->scaling_info->scaling_quality.v_taps,
update->scaling_info->scaling_quality.h_taps_c,
update->scaling_info->scaling_quality.v_taps_c);
}
SURFACE_TRACE("\n");
}
SURFACE_TRACE("\n");
}
void post_surface_trace(struct dc *dc)
{
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
SURFACE_TRACE("post surface process.\n");
}
void context_timing_trace(
struct dc *dc,
struct resource_context *res_ctx)
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
struct crtc_position position;
unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
/* get_position() returns CRTC vertical/horizontal counter
* hence not applicable for underlay pipe
*/
if (pipe_ctx->stream == NULL
|| pipe_ctx->pipe_idx == underlay_idx)
continue;
pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
h_pos[i] = position.horizontal_count;
v_pos[i] = position.vertical_count;
}
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->stream == NULL)
continue;
TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
pipe_ctx->stream_res.tg->inst,
pipe_ctx->stream->timing.h_total,
pipe_ctx->stream->timing.v_total,
h_pos[i], v_pos[i]);
}
}
void context_clock_trace(
struct dc *dc,
struct dc_state *context)
{
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
"dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_div,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.dram_ccm_us,
context->bw.dcn.calc_clk.min_active_dram_ccm_us);
CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
"dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_div,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.dram_ccm_us,
context->bw.dcn.calc_clk.min_active_dram_ccm_us);
#endif
}

101
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c Normal file
View File

@ -0,0 +1,101 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "core_types.h"
#include "timing_generator.h"
#include "hw_sequencer.h"
/* used as index in array of black_color_format */
enum black_color_format {
BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
BLACK_COLOR_FORMAT_RGB_LIMITED,
BLACK_COLOR_FORMAT_YUV_TV,
BLACK_COLOR_FORMAT_YUV_CV,
BLACK_COLOR_FORMAT_YUV_SUPER_AA,
BLACK_COLOR_FORMAT_DEBUG,
};
static const struct tg_color black_color_format[] = {
/* BlackColorFormat_RGB_FullRange */
{0, 0, 0},
/* BlackColorFormat_RGB_Limited */
{0x40, 0x40, 0x40},
/* BlackColorFormat_YUV_TV */
{0x200, 0x40, 0x200},
/* BlackColorFormat_YUV_CV */
{0x1f4, 0x40, 0x1f4},
/* BlackColorFormat_YUV_SuperAA */
{0x1a2, 0x20, 0x1a2},
/* visual confirm debug */
{0xff, 0xff, 0},
};
void color_space_to_black_color(
const struct dc *dc,
enum dc_color_space colorspace,
struct tg_color *black_color)
{
switch (colorspace) {
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR601_LIMITED:
case COLOR_SPACE_YCBCR709_LIMITED:
*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
break;
case COLOR_SPACE_SRGB_LIMITED:
*black_color =
black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
break;
default:
/* fefault is sRGB black (full range). */
*black_color =
black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
/* default is sRGB black 0. */
break;
}
}
bool hwss_wait_for_blank_complete(
struct timing_generator *tg)
{
int counter;
for (counter = 0; counter < 100; counter++) {
if (tg->funcs->is_blanked(tg))
break;
msleep(1);
}
if (counter == 100) {
dm_error("DC: failed to blank crtc!\n");
return false;
}
return true;
}

2367
drivers/gpu/drm/amd/display/dc/core/dc_link.c Normal file
View File

File diff suppressed because it is too large Load Diff

775
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c Normal file
View File

@ -0,0 +1,775 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dm_helpers.h"
#include "gpio_service_interface.h"
#include "include/ddc_service_types.h"
#include "include/grph_object_id.h"
#include "include/dpcd_defs.h"
#include "include/logger_interface.h"
#include "include/vector.h"
#include "core_types.h"
#include "dc_link_ddc.h"
#define AUX_POWER_UP_WA_DELAY 500
#define I2C_OVER_AUX_DEFER_WA_DELAY 70
/* CV smart dongle slave address for retrieving supported HDTV modes*/
#define CV_SMART_DONGLE_ADDRESS 0x20
/* DVI-HDMI dongle slave address for retrieving dongle signature*/
#define DVI_HDMI_DONGLE_ADDRESS 0x68
static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
struct dvi_hdmi_dongle_signature_data {
int8_t vendor[3];/* "AMD" */
uint8_t version[2];
uint8_t size;
int8_t id[11];/* "6140063500G"*/
};
/* DP-HDMI dongle slave address for retrieving dongle signature*/
#define DP_HDMI_DONGLE_ADDRESS 0x40
static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
struct dp_hdmi_dongle_signature_data {
int8_t id[15];/* "DP-HDMI ADAPTOR"*/
uint8_t eot;/* end of transmition '\x4' */
};
/* SCDC Address defines (HDMI 2.0)*/
#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
#define HDMI_SCDC_ADDRESS 0x54
#define HDMI_SCDC_SINK_VERSION 0x01
#define HDMI_SCDC_SOURCE_VERSION 0x02
#define HDMI_SCDC_UPDATE_0 0x10
#define HDMI_SCDC_TMDS_CONFIG 0x20
#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
#define HDMI_SCDC_CONFIG_0 0x30
#define HDMI_SCDC_STATUS_FLAGS 0x40
#define HDMI_SCDC_ERR_DETECT 0x50
#define HDMI_SCDC_TEST_CONFIG 0xC0
union hdmi_scdc_update_read_data {
uint8_t byte[2];
struct {
uint8_t STATUS_UPDATE:1;
uint8_t CED_UPDATE:1;
uint8_t RR_TEST:1;
uint8_t RESERVED:5;
uint8_t RESERVED2:8;
} fields;
};
union hdmi_scdc_status_flags_data {
uint8_t byte[2];
struct {
uint8_t CLOCK_DETECTED:1;
uint8_t CH0_LOCKED:1;
uint8_t CH1_LOCKED:1;
uint8_t CH2_LOCKED:1;
uint8_t RESERVED:4;
uint8_t RESERVED2:8;
} fields;
};
union hdmi_scdc_ced_data {
uint8_t byte[7];
struct {
uint8_t CH0_8LOW:8;
uint8_t CH0_7HIGH:7;
uint8_t CH0_VALID:1;
uint8_t CH1_8LOW:8;
uint8_t CH1_7HIGH:7;
uint8_t CH1_VALID:1;
uint8_t CH2_8LOW:8;
uint8_t CH2_7HIGH:7;
uint8_t CH2_VALID:1;
uint8_t CHECKSUM:8;
} fields;
};
union hdmi_scdc_test_config_Data {
uint8_t byte;
struct {
uint8_t TEST_READ_REQUEST_DELAY:7;
uint8_t TEST_READ_REQUEST: 1;
} fields;
};
struct i2c_payloads {
struct vector payloads;
};
struct aux_payloads {
struct vector payloads;
};
static struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
{
struct i2c_payloads *payloads;
payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL);
if (!payloads)
return NULL;
if (dal_vector_construct(
&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
return payloads;
kfree(payloads);
return NULL;
}
static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
{
return (struct i2c_payload *)p->payloads.container;
}
static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
{
return p->payloads.count;
}
static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
{
if (!p || !*p)
return;
dal_vector_destruct(&(*p)->payloads);
kfree(*p);
*p = NULL;
}
static struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
{
struct aux_payloads *payloads;
payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL);
if (!payloads)
return NULL;
if (dal_vector_construct(
&payloads->payloads, ctx, count, sizeof(struct aux_payload)))
return payloads;
kfree(payloads);
return NULL;
}
static struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
{
return (struct aux_payload *)p->payloads.container;
}
static uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
{
return p->payloads.count;
}
static void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
{
if (!p || !*p)
return;
dal_vector_destruct(&(*p)->payloads);
kfree(*p);
*p = NULL;
}
#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
void dal_ddc_i2c_payloads_add(
struct i2c_payloads *payloads,
uint32_t address,
uint32_t len,
uint8_t *data,
bool write)
{
uint32_t payload_size = EDID_SEGMENT_SIZE;
uint32_t pos;
for (pos = 0; pos < len; pos += payload_size) {
struct i2c_payload payload = {
.write = write,
.address = address,
.length = DDC_MIN(payload_size, len - pos),
.data = data + pos };
dal_vector_append(&payloads->payloads, &payload);
}
}
void dal_ddc_aux_payloads_add(
struct aux_payloads *payloads,
uint32_t address,
uint32_t len,
uint8_t *data,
bool write)
{
uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
uint32_t pos;
for (pos = 0; pos < len; pos += payload_size) {
struct aux_payload payload = {
.i2c_over_aux = true,
.write = write,
.address = address,
.length = DDC_MIN(payload_size, len - pos),
.data = data + pos };
dal_vector_append(&payloads->payloads, &payload);
}
}
static void construct(
struct ddc_service *ddc_service,
struct ddc_service_init_data *init_data)
{
enum connector_id connector_id =
dal_graphics_object_id_get_connector_id(init_data->id);
struct gpio_service *gpio_service = init_data->ctx->gpio_service;
struct graphics_object_i2c_info i2c_info;
struct gpio_ddc_hw_info hw_info;
struct dc_bios *dcb = init_data->ctx->dc_bios;
ddc_service->link = init_data->link;
ddc_service->ctx = init_data->ctx;
if (BP_RESULT_OK != dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info)) {
ddc_service->ddc_pin = NULL;
} else {
hw_info.ddc_channel = i2c_info.i2c_line;
hw_info.hw_supported = i2c_info.i2c_hw_assist;
ddc_service->ddc_pin = dal_gpio_create_ddc(
gpio_service,
i2c_info.gpio_info.clk_a_register_index,
1 << i2c_info.gpio_info.clk_a_shift,
&hw_info);
}
ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
ddc_service->flags.FORCE_READ_REPEATED_START = false;
ddc_service->flags.EDID_STRESS_READ = false;
ddc_service->flags.IS_INTERNAL_DISPLAY =
connector_id == CONNECTOR_ID_EDP ||
connector_id == CONNECTOR_ID_LVDS;
ddc_service->wa.raw = 0;
}
struct ddc_service *dal_ddc_service_create(
struct ddc_service_init_data *init_data)
{
struct ddc_service *ddc_service;
ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
if (!ddc_service)
return NULL;
construct(ddc_service, init_data);
return ddc_service;
}
static void destruct(struct ddc_service *ddc)
{
if (ddc->ddc_pin)
dal_gpio_destroy_ddc(&ddc->ddc_pin);
}
void dal_ddc_service_destroy(struct ddc_service **ddc)
{
if (!ddc || !*ddc) {
BREAK_TO_DEBUGGER();
return;
}
destruct(*ddc);
kfree(*ddc);
*ddc = NULL;
}
enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
{
return DDC_SERVICE_TYPE_CONNECTOR;
}
void dal_ddc_service_set_transaction_type(
struct ddc_service *ddc,
enum ddc_transaction_type type)
{
ddc->transaction_type = type;
}
bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
{
switch (ddc->transaction_type) {
case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
return true;
default:
break;
}
return false;
}
void ddc_service_set_dongle_type(struct ddc_service *ddc,
enum display_dongle_type dongle_type)
{
ddc->dongle_type = dongle_type;
}
static uint32_t defer_delay_converter_wa(
struct ddc_service *ddc,
uint32_t defer_delay)
{
struct dc_link *link = ddc->link;
if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
!memcmp(link->dpcd_caps.branch_dev_name,
DP_DVI_CONVERTER_ID_4,
sizeof(link->dpcd_caps.branch_dev_name)))
return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
return defer_delay;
}
#define DP_TRANSLATOR_DELAY 5
uint32_t get_defer_delay(struct ddc_service *ddc)
{
uint32_t defer_delay = 0;
switch (ddc->transaction_type) {
case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
ddc->dongle_type)) {
defer_delay = DP_TRANSLATOR_DELAY;
defer_delay =
defer_delay_converter_wa(ddc, defer_delay);
} else /*sink has a delay different from an Active Converter*/
defer_delay = 0;
break;
case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
defer_delay = DP_TRANSLATOR_DELAY;
break;
default:
break;
}
return defer_delay;
}
static bool i2c_read(
struct ddc_service *ddc,
uint32_t address,
uint8_t *buffer,
uint32_t len)
{
uint8_t offs_data = 0;
struct i2c_payload payloads[2] = {
{
.write = true,
.address = address,
.length = 1,
.data = &offs_data },
{
.write = false,
.address = address,
.length = len,
.data = buffer } };
struct i2c_command command = {
.payloads = payloads,
.number_of_payloads = 2,
.engine = DDC_I2C_COMMAND_ENGINE,
.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
return dm_helpers_submit_i2c(
ddc->ctx,
ddc->link,
&command);
}
void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
struct ddc_service *ddc,
struct display_sink_capability *sink_cap)
{
uint8_t i;
bool is_valid_hdmi_signature;
enum display_dongle_type *dongle = &sink_cap->dongle_type;
uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
bool is_type2_dongle = false;
struct dp_hdmi_dongle_signature_data *dongle_signature;
/* Assume we have no valid DP passive dongle connected */
*dongle = DISPLAY_DONGLE_NONE;
sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
if (!i2c_read(
ddc,
DP_HDMI_DONGLE_ADDRESS,
type2_dongle_buf,
sizeof(type2_dongle_buf))) {
*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
"DP-DVI passive dongle %dMhz: ",
DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
return;
}
/* Check if Type 2 dongle.*/
if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
is_type2_dongle = true;
dongle_signature =
(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
is_valid_hdmi_signature = true;
/* Check EOT */
if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
is_valid_hdmi_signature = false;
}
/* Check signature */
for (i = 0; i < sizeof(dongle_signature->id); ++i) {
/* If its not the right signature,
* skip mismatch in subversion byte.*/
if (dongle_signature->id[i] !=
dp_hdmi_dongle_signature_str[i] && i != 3) {
if (is_type2_dongle) {
is_valid_hdmi_signature = false;
break;
}
}
}
if (is_type2_dongle) {
uint32_t max_tmds_clk =
type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
if (0 == max_tmds_clk ||
max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
sizeof(type2_dongle_buf),
"DP-DVI passive dongle %dMhz: ",
DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
} else {
if (is_valid_hdmi_signature == true) {
*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
sizeof(type2_dongle_buf),
"Type 2 DP-HDMI passive dongle %dMhz: ",
max_tmds_clk);
} else {
*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
sizeof(type2_dongle_buf),
"Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
max_tmds_clk);
}
/* Multiply by 1000 to convert to kHz. */
sink_cap->max_hdmi_pixel_clock =
max_tmds_clk * 1000;
}
} else {
if (is_valid_hdmi_signature == true) {
*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
sizeof(type2_dongle_buf),
"Type 1 DP-HDMI passive dongle %dMhz: ",
sink_cap->max_hdmi_pixel_clock / 1000);
} else {
*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
sizeof(type2_dongle_buf),
"Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
sink_cap->max_hdmi_pixel_clock / 1000);
}
}
return;
}
enum {
DP_SINK_CAP_SIZE =
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
};
bool dal_ddc_service_query_ddc_data(
struct ddc_service *ddc,
uint32_t address,
uint8_t *write_buf,
uint32_t write_size,
uint8_t *read_buf,
uint32_t read_size)
{
bool ret;
uint32_t payload_size =
dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
uint32_t write_payloads =
(write_size + payload_size - 1) / payload_size;
uint32_t read_payloads =
(read_size + payload_size - 1) / payload_size;
uint32_t payloads_num = write_payloads + read_payloads;
if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
return false;
/*TODO: len of payload data for i2c and aux is uint8!!!!,
* but we want to read 256 over i2c!!!!*/
if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
struct aux_payloads *payloads =
dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
struct aux_command command = {
.payloads = dal_ddc_aux_payloads_get(payloads),
.number_of_payloads = 0,
.defer_delay = get_defer_delay(ddc),
.max_defer_write_retry = 0 };
dal_ddc_aux_payloads_add(
payloads, address, write_size, write_buf, true);
dal_ddc_aux_payloads_add(
payloads, address, read_size, read_buf, false);
command.number_of_payloads =
dal_ddc_aux_payloads_get_count(payloads);
ret = dal_i2caux_submit_aux_command(
ddc->ctx->i2caux,
ddc->ddc_pin,
&command);
dal_ddc_aux_payloads_destroy(&payloads);
} else {
struct i2c_payloads *payloads =
dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
struct i2c_command command = {
.payloads = dal_ddc_i2c_payloads_get(payloads),
.number_of_payloads = 0,
.engine = DDC_I2C_COMMAND_ENGINE,
.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
dal_ddc_i2c_payloads_add(
payloads, address, write_size, write_buf, true);
dal_ddc_i2c_payloads_add(
payloads, address, read_size, read_buf, false);
command.number_of_payloads =
dal_ddc_i2c_payloads_get_count(payloads);
ret = dm_helpers_submit_i2c(
ddc->ctx,
ddc->link,
&command);
dal_ddc_i2c_payloads_destroy(&payloads);
}
return ret;
}
enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
uint32_t len)
{
struct aux_payload read_payload = {
.i2c_over_aux = i2c,
.write = false,
.address = address,
.length = len,
.data = data,
};
struct aux_command command = {
.payloads = &read_payload,
.number_of_payloads = 1,
.defer_delay = 0,
.max_defer_write_retry = 0,
.mot = mot
};
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
BREAK_TO_DEBUGGER();
return DDC_RESULT_FAILED_INVALID_OPERATION;
}
if (dal_i2caux_submit_aux_command(
ddc->ctx->i2caux,
ddc->ddc_pin,
&command))
return DDC_RESULT_SUCESSFULL;
return DDC_RESULT_FAILED_OPERATION;
}
enum ddc_result dal_ddc_service_write_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
const uint8_t *data,
uint32_t len)
{
struct aux_payload write_payload = {
.i2c_over_aux = i2c,
.write = true,
.address = address,
.length = len,
.data = (uint8_t *)data,
};
struct aux_command command = {
.payloads = &write_payload,
.number_of_payloads = 1,
.defer_delay = 0,
.max_defer_write_retry = 0,
.mot = mot
};
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
BREAK_TO_DEBUGGER();
return DDC_RESULT_FAILED_INVALID_OPERATION;
}
if (dal_i2caux_submit_aux_command(
ddc->ctx->i2caux,
ddc->ddc_pin,
&command))
return DDC_RESULT_SUCESSFULL;
return DDC_RESULT_FAILED_OPERATION;
}
/*test only function*/
void dal_ddc_service_set_ddc_pin(
struct ddc_service *ddc_service,
struct ddc *ddc)
{
ddc_service->ddc_pin = ddc;
}
struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
{
return ddc_service->ddc_pin;
}
void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
uint32_t pix_clk,
bool lte_340_scramble)
{
bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
uint8_t slave_address = HDMI_SCDC_ADDRESS;
uint8_t offset = HDMI_SCDC_SINK_VERSION;
uint8_t sink_version = 0;
uint8_t write_buffer[2] = {0};
/*Lower than 340 Scramble bit from SCDC caps*/
dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
sizeof(offset), &sink_version, sizeof(sink_version));
if (sink_version == 1) {
/*Source Version = 1*/
write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
write_buffer[1] = 1;
dal_ddc_service_query_ddc_data(ddc_service, slave_address,
write_buffer, sizeof(write_buffer), NULL, 0);
/*Read Request from SCDC caps*/
}
write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
if (over_340_mhz) {
write_buffer[1] = 3;
} else if (lte_340_scramble) {
write_buffer[1] = 1;
} else {
write_buffer[1] = 0;
}
dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
sizeof(write_buffer), NULL, 0);
}
void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
{
uint8_t slave_address = HDMI_SCDC_ADDRESS;
uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
uint8_t tmds_config = 0;
dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
sizeof(offset), &tmds_config, sizeof(tmds_config));
if (tmds_config & 0x1) {
union hdmi_scdc_status_flags_data status_data = { {0} };
uint8_t scramble_status = 0;
offset = HDMI_SCDC_SCRAMBLER_STATUS;
dal_ddc_service_query_ddc_data(ddc_service, slave_address,
&offset, sizeof(offset), &scramble_status,
sizeof(scramble_status));
offset = HDMI_SCDC_STATUS_FLAGS;
dal_ddc_service_query_ddc_data(ddc_service, slave_address,
&offset, sizeof(offset), status_data.byte,
sizeof(status_data.byte));
}
}

2587
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c Normal file
View File

File diff suppressed because it is too large Load Diff

331
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c Normal file
View File

@ -0,0 +1,331 @@
/* Copyright 2015 Advanced Micro Devices, Inc. */
#include "dm_services.h"
#include "dc.h"
#include "inc/core_types.h"
#include "include/ddc_service_types.h"
#include "include/i2caux_interface.h"
#include "link_hwss.h"
#include "hw_sequencer.h"
#include "dc_link_dp.h"
#include "dc_link_ddc.h"
#include "dm_helpers.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
#include "dpcd_defs.h"
enum dc_status core_link_read_dpcd(
struct dc_link *link,
uint32_t address,
uint8_t *data,
uint32_t size)
{
if (!dm_helpers_dp_read_dpcd(link->ctx,
link,
address, data, size))
return DC_ERROR_UNEXPECTED;
return DC_OK;
}
enum dc_status core_link_write_dpcd(
struct dc_link *link,
uint32_t address,
const uint8_t *data,
uint32_t size)
{
if (!dm_helpers_dp_write_dpcd(link->ctx,
link,
address, data, size))
return DC_ERROR_UNEXPECTED;
return DC_OK;
}
void dp_receiver_power_ctrl(struct dc_link *link, bool on)
{
uint8_t state;
state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
core_link_write_dpcd(link, DP_SET_POWER, &state,
sizeof(state));
}
void dp_enable_link_phy(
struct dc_link *link,
enum signal_type signal,
enum clock_source_id clock_source,
const struct dc_link_settings *link_settings)
{
struct link_encoder *link_enc = link->link_enc;
struct pipe_ctx *pipes =
link->dc->current_state->res_ctx.pipe_ctx;
struct clock_source *dp_cs =
link->dc->res_pool->dp_clock_source;
unsigned int i;
/* If the current pixel clock source is not DTO(happens after
* switching from HDMI passive dongle to DP on the same connector),
* switch the pixel clock source to DTO.
*/
for (i = 0; i < MAX_PIPES; i++) {
if (pipes[i].stream != NULL &&
pipes[i].stream->sink != NULL &&
pipes[i].stream->sink->link == link) {
if (pipes[i].clock_source != NULL &&
pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
pipes[i].clock_source = dp_cs;
pipes[i].stream_res.pix_clk_params.requested_pix_clk =
pipes[i].stream->timing.pix_clk_khz;
pipes[i].clock_source->funcs->program_pix_clk(
pipes[i].clock_source,
&pipes[i].stream_res.pix_clk_params,
&pipes[i].pll_settings);
}
}
}
if (dc_is_dp_sst_signal(signal)) {
if (signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_power_control(link->link_enc, true);
link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
clock_source);
link->dc->hwss.edp_backlight_control(link, true);
} else
link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
clock_source);
} else {
link_enc->funcs->enable_dp_mst_output(
link_enc,
link_settings,
clock_source);
}
dp_receiver_power_ctrl(link, true);
}
static bool edp_receiver_ready_T9(struct dc_link *link)
{
unsigned int tries = 0;
unsigned char sinkstatus = 0;
unsigned char edpRev = 0;
enum dc_status result = DC_OK;
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
if (edpRev < DP_EDP_12)
return true;
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
do {
sinkstatus = 1;
result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
if (sinkstatus == 0)
break;
if (result != DC_OK)
break;
udelay(100); //MAx T9
} while (++tries < 50);
return result;
}
void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
{
if (!link->wa_flags.dp_keep_receiver_powered)
dp_receiver_power_ctrl(link, false);
if (signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, false);
edp_receiver_ready_T9(link);
link->link_enc->funcs->disable_output(link->link_enc, signal, link);
link->dc->hwss.edp_power_control(link->link_enc, false);
} else
link->link_enc->funcs->disable_output(link->link_enc, signal, link);
/* Clear current link setting.*/
memset(&link->cur_link_settings, 0,
sizeof(link->cur_link_settings));
}
void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
{
/* MST disable link only when no stream use the link */
if (link->mst_stream_alloc_table.stream_count > 0)
return;
dp_disable_link_phy(link, signal);
/* set the sink to SST mode after disabling the link */
dp_enable_mst_on_sink(link, false);
}
bool dp_set_hw_training_pattern(
struct dc_link *link,
enum hw_dp_training_pattern pattern)
{
enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
switch (pattern) {
case HW_DP_TRAINING_PATTERN_1:
test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
break;
case HW_DP_TRAINING_PATTERN_2:
test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
break;
case HW_DP_TRAINING_PATTERN_3:
test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
break;
case HW_DP_TRAINING_PATTERN_4:
test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
break;
default:
break;
}
dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
return true;
}
void dp_set_hw_lane_settings(
struct dc_link *link,
const struct link_training_settings *link_settings)
{
struct link_encoder *encoder = link->link_enc;
/* call Encoder to set lane settings */
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
}
enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
{
/* We need to explicitly check that connector
* is not DP. Some Travis_VGA get reported
* by video bios as DP.
*/
if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
switch (link->dpcd_caps.branch_dev_id) {
case DP_BRANCH_DEVICE_ID_2:
if (strncmp(
link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_2,
sizeof(
link->dpcd_caps.
branch_dev_name)) == 0) {
return DP_PANEL_MODE_SPECIAL;
}
break;
case DP_BRANCH_DEVICE_ID_3:
if (strncmp(link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_3,
sizeof(
link->dpcd_caps.
branch_dev_name)) == 0) {
return DP_PANEL_MODE_SPECIAL;
}
break;
default:
break;
}
}
if (link->dpcd_caps.panel_mode_edp) {
return DP_PANEL_MODE_EDP;
}
return DP_PANEL_MODE_DEFAULT;
}
void dp_set_hw_test_pattern(
struct dc_link *link,
enum dp_test_pattern test_pattern,
uint8_t *custom_pattern,
uint32_t custom_pattern_size)
{
struct encoder_set_dp_phy_pattern_param pattern_param = {0};
struct link_encoder *encoder = link->link_enc;
pattern_param.dp_phy_pattern = test_pattern;
pattern_param.custom_pattern = custom_pattern;
pattern_param.custom_pattern_size = custom_pattern_size;
pattern_param.dp_panel_mode = dp_get_panel_mode(link);
encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
}
void dp_retrain_link_dp_test(struct dc_link *link,
struct dc_link_settings *link_setting,
bool skip_video_pattern)
{
struct pipe_ctx *pipes =
&link->dc->current_state->res_ctx.pipe_ctx[0];
unsigned int i;
for (i = 0; i < MAX_PIPES; i++) {
if (pipes[i].stream != NULL &&
pipes[i].stream->sink != NULL &&
pipes[i].stream->sink->link != NULL &&
pipes[i].stream_res.stream_enc != NULL &&
pipes[i].stream->sink->link == link) {
udelay(100);
pipes[i].stream_res.stream_enc->funcs->dp_blank(
pipes[i].stream_res.stream_enc);
/* disable any test pattern that might be active */
dp_set_hw_test_pattern(link,
DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
dp_receiver_power_ctrl(link, false);
link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
link->link_enc->funcs->disable_output(
link->link_enc,
SIGNAL_TYPE_DISPLAY_PORT,
link);
/* Clear current link setting. */
memset(&link->cur_link_settings, 0,
sizeof(link->cur_link_settings));
link->link_enc->funcs->enable_dp_output(
link->link_enc,
link_setting,
pipes[i].clock_source->id);
dp_receiver_power_ctrl(link, true);
perform_link_training_with_retries(
link,
link_setting,
skip_video_pattern,
LINK_TRAINING_ATTEMPTS);
link->cur_link_settings = *link_setting;
link->dc->hwss.enable_stream(&pipes[i]);
link->dc->hwss.unblank_stream(&pipes[i],
link_setting);
if (pipes[i].stream_res.audio) {
/* notify audio driver for
* audio modes of monitor */
pipes[i].stream_res.audio->funcs->az_enable(
pipes[i].stream_res.audio);
/* un-mute audio */
/* TODO: audio should be per stream rather than
* per link */
pipes[i].stream_res.stream_enc->funcs->
audio_mute_control(
pipes[i].stream_res.stream_enc, false);
}
}
}
}

2795
drivers/gpu/drm/amd/display/dc/core/dc_resource.c Normal file
View File

File diff suppressed because it is too large Load Diff

104
drivers/gpu/drm/amd/display/dc/core/dc_sink.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dm_helpers.h"
#include "core_types.h"
/*******************************************************************************
* Private functions
******************************************************************************/
static void destruct(struct dc_sink *sink)
{
if (sink->dc_container_id) {
kfree(sink->dc_container_id);
sink->dc_container_id = NULL;
}
}
static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
{
struct dc_link *link = init_params->link;
if (!link)
return false;
sink->sink_signal = init_params->sink_signal;
sink->link = link;
sink->ctx = link->ctx;
sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk;
sink->converter_disable_audio = init_params->converter_disable_audio;
sink->dc_container_id = NULL;
return true;
}
/*******************************************************************************
* Public functions
******************************************************************************/
void dc_sink_retain(struct dc_sink *sink)
{
kref_get(&sink->refcount);
}
static void dc_sink_free(struct kref *kref)
{
struct dc_sink *sink = container_of(kref, struct dc_sink, refcount);
destruct(sink);
kfree(sink);
}
void dc_sink_release(struct dc_sink *sink)
{
kref_put(&sink->refcount, dc_sink_free);
}
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
{
struct dc_sink *sink = kzalloc(sizeof(*sink), GFP_KERNEL);
if (NULL == sink)
goto alloc_fail;
if (false == construct(sink, init_params))
goto construct_fail;
kref_init(&sink->refcount);
return sink;
construct_fail:
kfree(sink);
alloc_fail:
return NULL;
}
/*******************************************************************************
* Protected functions - visible only inside of DC (not visible in DM)
******************************************************************************/

398
drivers/gpu/drm/amd/display/dc/core/dc_stream.c Normal file
View File

@ -0,0 +1,398 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "dc.h"
#include "core_types.h"
#include "resource.h"
#include "ipp.h"
#include "timing_generator.h"
/*******************************************************************************
* Private functions
******************************************************************************/
#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
static void update_stream_signal(struct dc_stream_state *stream)
{
if (stream->output_signal == SIGNAL_TYPE_NONE) {
struct dc_sink *dc_sink = stream->sink;
if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
stream->signal = stream->sink->link->connector_signal;
else
stream->signal = dc_sink->sink_signal;
} else {
stream->signal = stream->output_signal;
}
if (dc_is_dvi_signal(stream->signal)) {
if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
else
stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
}
static void construct(struct dc_stream_state *stream,
struct dc_sink *dc_sink_data)
{
uint32_t i = 0;
stream->sink = dc_sink_data;
stream->ctx = stream->sink->ctx;
dc_sink_retain(dc_sink_data);
/* Copy audio modes */
/* TODO - Remove this translation */
for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
{
stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
}
stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
memmove(
stream->audio_info.display_name,
dc_sink_data->edid_caps.display_name,
AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
if (dc_sink_data->dc_container_id != NULL) {
struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
stream->audio_info.port_id[0] = dc_container_id->portId[0];
stream->audio_info.port_id[1] = dc_container_id->portId[1];
} else {
/* TODO - WindowDM has implemented,
other DMs need Unhardcode port_id */
stream->audio_info.port_id[0] = 0x5558859e;
stream->audio_info.port_id[1] = 0xd989449;
}
/* EDID CAP translation for HDMI 2.0 */
stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
stream->status.link = stream->sink->link;
update_stream_signal(stream);
}
static void destruct(struct dc_stream_state *stream)
{
dc_sink_release(stream->sink);
if (stream->out_transfer_func != NULL) {
dc_transfer_func_release(
stream->out_transfer_func);
stream->out_transfer_func = NULL;
}
}
void dc_stream_retain(struct dc_stream_state *stream)
{
kref_get(&stream->refcount);
}
static void dc_stream_free(struct kref *kref)
{
struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
destruct(stream);
kfree(stream);
}
void dc_stream_release(struct dc_stream_state *stream)
{
if (stream != NULL) {
kref_put(&stream->refcount, dc_stream_free);
}
}
struct dc_stream_state *dc_create_stream_for_sink(
struct dc_sink *sink)
{
struct dc_stream_state *stream;
if (sink == NULL)
return NULL;
stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
if (stream == NULL)
return NULL;
construct(stream, sink);
kref_init(&stream->refcount);
return stream;
}
struct dc_stream_status *dc_stream_get_status(
struct dc_stream_state *stream)
{
uint8_t i;
struct dc *dc = stream->ctx->dc;
for (i = 0; i < dc->current_state->stream_count; i++) {
if (stream == dc->current_state->streams[i])
return &dc->current_state->stream_status[i];
}
return NULL;
}
/**
* Update the cursor attributes and set cursor surface address
*/
bool dc_stream_set_cursor_attributes(
struct dc_stream_state *stream,
const struct dc_cursor_attributes *attributes)
{
int i;
struct dc *core_dc;
struct resource_context *res_ctx;
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
return false;
}
if (NULL == attributes) {
dm_error("DC: attributes is NULL!\n");
return false;
}
if (attributes->address.quad_part == 0) {
dm_output_to_console("DC: Cursor address is 0!\n");
return false;
}
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_state->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
continue;
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
continue;
if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)
pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
pipe_ctx->plane_res.ipp, attributes);
if (pipe_ctx->plane_res.hubp != NULL &&
pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.hubp, attributes);
if (pipe_ctx->plane_res.mi != NULL &&
pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
pipe_ctx->plane_res.mi, attributes);
if (pipe_ctx->plane_res.xfm != NULL &&
pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
pipe_ctx->plane_res.xfm, attributes);
if (pipe_ctx->plane_res.dpp != NULL &&
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.dpp, attributes);
}
stream->cursor_attributes = *attributes;
return true;
}
bool dc_stream_set_cursor_position(
struct dc_stream_state *stream,
const struct dc_cursor_position *position)
{
int i;
struct dc *core_dc;
struct resource_context *res_ctx;
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
return false;
}
if (NULL == position) {
dm_error("DC: cursor position is NULL!\n");
return false;
}
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_state->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
struct mem_input *mi = pipe_ctx->plane_res.mi;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
struct transform *xfm = pipe_ctx->plane_res.xfm;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_cursor_position pos_cpy = *position;
struct dc_cursor_mi_param param = {
.pixel_clk_khz = stream->timing.pix_clk_khz,
.ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
};
if (pipe_ctx->stream != stream ||
(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
!pipe_ctx->plane_state ||
(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
continue;
if (pipe_ctx->plane_state->address.type
== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
pos_cpy.enable = false;
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
pos_cpy.enable = false;
if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
if (mi != NULL && mi->funcs->set_cursor_position != NULL)
mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
if (hubp != NULL && hubp->funcs->set_cursor_position != NULL)
hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
if (xfm != NULL && xfm->funcs->set_cursor_position != NULL)
xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, hubp->curs_attr.width);
if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
}
return true;
}
uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
{
uint8_t i;
struct dc *core_dc = stream->ctx->dc;
struct resource_context *res_ctx =
&core_dc->current_state->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
if (res_ctx->pipe_ctx[i].stream != stream)
continue;
return tg->funcs->get_frame_count(tg);
}
return 0;
}
bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
uint32_t *v_blank_start,
uint32_t *v_blank_end,
uint32_t *h_position,
uint32_t *v_position)
{
uint8_t i;
bool ret = false;
struct dc *core_dc = stream->ctx->dc;
struct resource_context *res_ctx =
&core_dc->current_state->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
if (res_ctx->pipe_ctx[i].stream != stream)
continue;
tg->funcs->get_scanoutpos(tg,
v_blank_start,
v_blank_end,
h_position,
v_position);
ret = true;
break;
}
return ret;
}
void dc_stream_log(
const struct dc_stream_state *stream,
struct dal_logger *dm_logger,
enum dc_log_type log_type)
{
dm_logger_write(dm_logger,
log_type,
"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
stream,
stream->src.x,
stream->src.y,
stream->src.width,
stream->src.height,
stream->dst.x,
stream->dst.y,
stream->dst.width,
stream->dst.height,
stream->output_color_space);
dm_logger_write(dm_logger,
log_type,
"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
stream->timing.pix_clk_khz,
stream->timing.h_total,
stream->timing.v_total,
stream->timing.pixel_encoding,
stream->timing.display_color_depth);
dm_logger_write(dm_logger,
log_type,
"\tsink name: %s, serial: %d\n",
stream->sink->edid_caps.display_name,
stream->sink->edid_caps.serial_number);
dm_logger_write(dm_logger,
log_type,
"\tlink: %d\n",
stream->sink->link->link_index);
}

193
drivers/gpu/drm/amd/display/dc/core/dc_surface.c Normal file
View File

@ -0,0 +1,193 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
/* DC interface (public) */
#include "dm_services.h"
#include "dc.h"
/* DC core (private) */
#include "core_types.h"
#include "transform.h"
#include "dpp.h"
/*******************************************************************************
* Private functions
******************************************************************************/
static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
{
plane_state->ctx = ctx;
}
static void destruct(struct dc_plane_state *plane_state)
{
if (plane_state->gamma_correction != NULL) {
dc_gamma_release(&plane_state->gamma_correction);
}
if (plane_state->in_transfer_func != NULL) {
dc_transfer_func_release(
plane_state->in_transfer_func);
plane_state->in_transfer_func = NULL;
}
}
/*******************************************************************************
* Public functions
******************************************************************************/
void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
uint32_t controller_id)
{
plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
/*register_flip_interrupt(surface);*/
}
struct dc_plane_state *dc_create_plane_state(struct dc *dc)
{
struct dc *core_dc = dc;
struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
GFP_KERNEL);
if (NULL == plane_state)
return NULL;
kref_init(&plane_state->refcount);
construct(core_dc->ctx, plane_state);
return plane_state;
}
const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state)
{
const struct dc_plane_status *plane_status;
struct dc *core_dc;
int i;
if (!plane_state ||
!plane_state->ctx ||
!plane_state->ctx->dc) {
ASSERT(0);
return NULL; /* remove this if above assert never hit */
}
plane_status = &plane_state->status;
core_dc = plane_state->ctx->dc;
if (core_dc->current_state == NULL)
return NULL;
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx =
&core_dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state != plane_state)
continue;
core_dc->hwss.update_pending_status(pipe_ctx);
}
return plane_status;
}
void dc_plane_state_retain(struct dc_plane_state *plane_state)
{
kref_get(&plane_state->refcount);
}
static void dc_plane_state_free(struct kref *kref)
{
struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
destruct(plane_state);
kfree(plane_state);
}
void dc_plane_state_release(struct dc_plane_state *plane_state)
{
kref_put(&plane_state->refcount, dc_plane_state_free);
}
void dc_gamma_retain(struct dc_gamma *gamma)
{
kref_get(&gamma->refcount);
}
static void dc_gamma_free(struct kref *kref)
{
struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
kfree(gamma);
}
void dc_gamma_release(struct dc_gamma **gamma)
{
kref_put(&(*gamma)->refcount, dc_gamma_free);
*gamma = NULL;
}
struct dc_gamma *dc_create_gamma(void)
{
struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
if (gamma == NULL)
goto alloc_fail;
kref_init(&gamma->refcount);
return gamma;
alloc_fail:
return NULL;
}
void dc_transfer_func_retain(struct dc_transfer_func *tf)
{
kref_get(&tf->refcount);
}
static void dc_transfer_func_free(struct kref *kref)
{
struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
kfree(tf);
}
void dc_transfer_func_release(struct dc_transfer_func *tf)
{
kref_put(&tf->refcount, dc_transfer_func_free);
}
struct dc_transfer_func *dc_create_transfer_func(void)
{
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
if (tf == NULL)
goto alloc_fail;
kref_init(&tf->refcount);
return tf;
alloc_fail:
return NULL;
}

1103
drivers/gpu/drm/amd/display/dc/dc.h Normal file
View File

File diff suppressed because it is too large Load Diff

218
drivers/gpu/drm/amd/display/dc/dc_bios_types.h Normal file
View File

@ -0,0 +1,218 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DC_BIOS_TYPES_H
#define DC_BIOS_TYPES_H
/******************************************************************************
* Interface file for VBIOS implementations.
*
* The default implementation is inside DC.
* Display Manager (which instantiates DC) has the option to supply it's own
* (external to DC) implementation of VBIOS, which will be called by DC, using
* this interface.
* (The intended use is Diagnostics, but other uses may appear.)
*****************************************************************************/
#include "include/bios_parser_types.h"
struct dc_vbios_funcs {
uint8_t (*get_connectors_number)(struct dc_bios *bios);
struct graphics_object_id (*get_encoder_id)(
struct dc_bios *bios,
uint32_t i);
struct graphics_object_id (*get_connector_id)(
struct dc_bios *bios,
uint8_t connector_index);
uint32_t (*get_dst_number)(
struct dc_bios *bios,
struct graphics_object_id id);
enum bp_result (*get_src_obj)(
struct dc_bios *bios,
struct graphics_object_id object_id, uint32_t index,
struct graphics_object_id *src_object_id);
enum bp_result (*get_dst_obj)(
struct dc_bios *bios,
struct graphics_object_id object_id, uint32_t index,
struct graphics_object_id *dest_object_id);
enum bp_result (*get_i2c_info)(
struct dc_bios *dcb,
struct graphics_object_id id,
struct graphics_object_i2c_info *info);
enum bp_result (*get_voltage_ddc_info)(
struct dc_bios *bios,
uint32_t index,
struct graphics_object_i2c_info *info);
enum bp_result (*get_thermal_ddc_info)(
struct dc_bios *bios,
uint32_t i2c_channel_id,
struct graphics_object_i2c_info *info);
enum bp_result (*get_hpd_info)(
struct dc_bios *bios,
struct graphics_object_id id,
struct graphics_object_hpd_info *info);
enum bp_result (*get_device_tag)(
struct dc_bios *bios,
struct graphics_object_id connector_object_id,
uint32_t device_tag_index,
struct connector_device_tag_info *info);
enum bp_result (*get_firmware_info)(
struct dc_bios *bios,
struct dc_firmware_info *info);
enum bp_result (*get_spread_spectrum_info)(
struct dc_bios *bios,
enum as_signal_type signal,
uint32_t index,
struct spread_spectrum_info *ss_info);
uint32_t (*get_ss_entry_number)(
struct dc_bios *bios,
enum as_signal_type signal);
enum bp_result (*get_embedded_panel_info)(
struct dc_bios *bios,
struct embedded_panel_info *info);
enum bp_result (*get_gpio_pin_info)(
struct dc_bios *bios,
uint32_t gpio_id,
struct gpio_pin_info *info);
enum bp_result (*get_encoder_cap_info)(
struct dc_bios *bios,
struct graphics_object_id object_id,
struct bp_encoder_cap_info *info);
bool (*is_lid_status_changed)(
struct dc_bios *bios);
bool (*is_display_config_changed)(
struct dc_bios *bios);
bool (*is_accelerated_mode)(
struct dc_bios *bios);
void (*get_bios_event_info)(
struct dc_bios *bios,
struct bios_event_info *info);
void (*update_requested_backlight_level)(
struct dc_bios *bios,
uint32_t backlight_8bit);
uint32_t (*get_requested_backlight_level)(
struct dc_bios *bios);
void (*take_backlight_control)(
struct dc_bios *bios,
bool cntl);
bool (*is_active_display)(
struct dc_bios *bios,
enum signal_type signal,
const struct connector_device_tag_info *device_tag);
enum controller_id (*get_embedded_display_controller_id)(
struct dc_bios *bios);
uint32_t (*get_embedded_display_refresh_rate)(
struct dc_bios *bios);
void (*set_scratch_critical_state)(
struct dc_bios *bios,
bool state);
bool (*is_device_id_supported)(
struct dc_bios *bios,
struct device_id id);
/* COMMANDS */
enum bp_result (*encoder_control)(
struct dc_bios *bios,
struct bp_encoder_control *cntl);
enum bp_result (*transmitter_control)(
struct dc_bios *bios,
struct bp_transmitter_control *cntl);
enum bp_result (*crt_control)(
struct dc_bios *bios,
enum engine_id engine_id,
bool enable,
uint32_t pixel_clock);
enum bp_result (*enable_crtc)(
struct dc_bios *bios,
enum controller_id id,
bool enable);
enum bp_result (*adjust_pixel_clock)(
struct dc_bios *bios,
struct bp_adjust_pixel_clock_parameters *bp_params);
enum bp_result (*set_pixel_clock)(
struct dc_bios *bios,
struct bp_pixel_clock_parameters *bp_params);
enum bp_result (*set_dce_clock)(
struct dc_bios *bios,
struct bp_set_dce_clock_parameters *bp_params);
unsigned int (*get_smu_clock_info)(
struct dc_bios *bios);
enum bp_result (*enable_spread_spectrum_on_ppll)(
struct dc_bios *bios,
struct bp_spread_spectrum_parameters *bp_params,
bool enable);
enum bp_result (*program_crtc_timing)(
struct dc_bios *bios,
struct bp_hw_crtc_timing_parameters *bp_params);
enum bp_result (*crtc_source_select)(
struct dc_bios *bios,
struct bp_crtc_source_select *bp_params);
enum bp_result (*program_display_engine_pll)(
struct dc_bios *bios,
struct bp_pixel_clock_parameters *bp_params);
enum signal_type (*dac_load_detect)(
struct dc_bios *bios,
struct graphics_object_id encoder,
struct graphics_object_id connector,
enum signal_type display_signal);
enum bp_result (*enable_disp_power_gating)(
struct dc_bios *bios,
enum controller_id controller_id,
enum bp_pipe_control_action action);
void (*post_init)(struct dc_bios *bios);
void (*bios_parser_destroy)(struct dc_bios **dcb);
};
struct bios_registers {
uint32_t BIOS_SCRATCH_6;
};
struct dc_bios {
const struct dc_vbios_funcs *funcs;
uint8_t *bios;
uint32_t bios_size;
uint8_t *bios_local_image;
struct dc_context *ctx;
const struct bios_registers *regs;
struct integrated_info *integrated_info;
};
#endif /* DC_BIOS_TYPES_H */

115
drivers/gpu/drm/amd/display/dc/dc_ddc_types.h Normal file
View File

@ -0,0 +1,115 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DC_DDC_TYPES_H_
#define DC_DDC_TYPES_H_
struct i2c_payload {
bool write;
uint8_t address;
uint32_t length;
uint8_t *data;
};
enum i2c_command_engine {
I2C_COMMAND_ENGINE_DEFAULT,
I2C_COMMAND_ENGINE_SW,
I2C_COMMAND_ENGINE_HW
};
struct i2c_command {
struct i2c_payload *payloads;
uint8_t number_of_payloads;
enum i2c_command_engine engine;
/* expressed in KHz
* zero means "use default value" */
uint32_t speed;
};
struct gpio_ddc_hw_info {
bool hw_supported;
uint32_t ddc_channel;
};
struct ddc {
struct gpio *pin_data;
struct gpio *pin_clock;
struct gpio_ddc_hw_info hw_info;
struct dc_context *ctx;
};
union ddc_wa {
struct {
uint32_t DP_SKIP_POWER_OFF:1;
uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
} bits;
uint32_t raw;
};
struct ddc_flags {
uint8_t EDID_QUERY_DONE_ONCE:1;
uint8_t IS_INTERNAL_DISPLAY:1;
uint8_t FORCE_READ_REPEATED_START:1;
uint8_t EDID_STRESS_READ:1;
};
enum ddc_transaction_type {
DDC_TRANSACTION_TYPE_NONE = 0,
DDC_TRANSACTION_TYPE_I2C,
DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
};
enum display_dongle_type {
DISPLAY_DONGLE_NONE = 0,
/* Active converter types*/
DISPLAY_DONGLE_DP_VGA_CONVERTER,
DISPLAY_DONGLE_DP_DVI_CONVERTER,
DISPLAY_DONGLE_DP_HDMI_CONVERTER,
/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
DISPLAY_DONGLE_DP_DVI_DONGLE,
DISPLAY_DONGLE_DP_HDMI_DONGLE,
/* Other types of dongle*/
DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
};
struct ddc_service {
struct ddc *ddc_pin;
struct ddc_flags flags;
union ddc_wa wa;
enum ddc_transaction_type transaction_type;
enum display_dongle_type dongle_type;
struct dc_context *ctx;
struct dc_link *link;
uint32_t address;
uint32_t edid_buf_len;
uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
};
#endif /* DC_DDC_TYPES_H_ */

467
drivers/gpu/drm/amd/display/dc/dc_dp_types.h Normal file
View File

@ -0,0 +1,467 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DC_DP_TYPES_H
#define DC_DP_TYPES_H
enum dc_lane_count {
LANE_COUNT_UNKNOWN = 0,
LANE_COUNT_ONE = 1,
LANE_COUNT_TWO = 2,
LANE_COUNT_FOUR = 4,
LANE_COUNT_EIGHT = 8,
LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
};
/* This is actually a reference clock (27MHz) multiplier
* 162MBps bandwidth for 1.62GHz like rate,
* 270MBps for 2.70GHz,
* 324MBps for 3.24Ghz,
* 540MBps for 5.40GHz
* 810MBps for 8.10GHz
*/
enum dc_link_rate {
LINK_RATE_UNKNOWN = 0,
LINK_RATE_LOW = 0x06,
LINK_RATE_HIGH = 0x0A,
LINK_RATE_RBR2 = 0x0C,
LINK_RATE_HIGH2 = 0x14,
LINK_RATE_HIGH3 = 0x1E
};
enum dc_link_spread {
LINK_SPREAD_DISABLED = 0x00,
/* 0.5 % downspread 30 kHz */
LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
/* 0.5 % downspread 33 kHz */
LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
};
enum dc_voltage_swing {
VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */
VOLTAGE_SWING_LEVEL1,
VOLTAGE_SWING_LEVEL2,
VOLTAGE_SWING_LEVEL3,
VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
};
enum dc_pre_emphasis {
PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */
PRE_EMPHASIS_LEVEL1,
PRE_EMPHASIS_LEVEL2,
PRE_EMPHASIS_LEVEL3,
PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
};
/* Post Cursor 2 is optional for transmitter
* and it applies only to the main link operating at HBR2
*/
enum dc_post_cursor2 {
POST_CURSOR2_DISABLED = 0, /* direct HW translation! */
POST_CURSOR2_LEVEL1,
POST_CURSOR2_LEVEL2,
POST_CURSOR2_LEVEL3,
POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
};
struct dc_link_settings {
enum dc_lane_count lane_count;
enum dc_link_rate link_rate;
enum dc_link_spread link_spread;
};
struct dc_lane_settings {
enum dc_voltage_swing VOLTAGE_SWING;
enum dc_pre_emphasis PRE_EMPHASIS;
enum dc_post_cursor2 POST_CURSOR2;
};
struct dc_link_training_settings {
struct dc_link_settings link;
struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
};
union dpcd_rev {
struct {
uint8_t MINOR:4;
uint8_t MAJOR:4;
} bits;
uint8_t raw;
};
union max_lane_count {
struct {
uint8_t MAX_LANE_COUNT:5;
uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
uint8_t TPS3_SUPPORTED:1;
uint8_t ENHANCED_FRAME_CAP:1;
} bits;
uint8_t raw;
};
union max_down_spread {
struct {
uint8_t MAX_DOWN_SPREAD:1;
uint8_t RESERVED:5;
uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
uint8_t TPS4_SUPPORTED:1;
} bits;
uint8_t raw;
};
union mstm_cap {
struct {
uint8_t MST_CAP:1;
uint8_t RESERVED:7;
} bits;
uint8_t raw;
};
union lane_count_set {
struct {
uint8_t LANE_COUNT_SET:5;
uint8_t POST_LT_ADJ_REQ_GRANTED:1;
uint8_t RESERVED:1;
uint8_t ENHANCED_FRAMING:1;
} bits;
uint8_t raw;
};
union lane_status {
struct {
uint8_t CR_DONE_0:1;
uint8_t CHANNEL_EQ_DONE_0:1;
uint8_t SYMBOL_LOCKED_0:1;
uint8_t RESERVED0:1;
uint8_t CR_DONE_1:1;
uint8_t CHANNEL_EQ_DONE_1:1;
uint8_t SYMBOL_LOCKED_1:1;
uint8_t RESERVED_1:1;
} bits;
uint8_t raw;
};
union device_service_irq {
struct {
uint8_t REMOTE_CONTROL_CMD_PENDING:1;
uint8_t AUTOMATED_TEST:1;
uint8_t CP_IRQ:1;
uint8_t MCCS_IRQ:1;
uint8_t DOWN_REP_MSG_RDY:1;
uint8_t UP_REQ_MSG_RDY:1;
uint8_t SINK_SPECIFIC:1;
uint8_t reserved:1;
} bits;
uint8_t raw;
};
union sink_count {
struct {
uint8_t SINK_COUNT:6;
uint8_t CPREADY:1;
uint8_t RESERVED:1;
} bits;
uint8_t raw;
};
union lane_align_status_updated {
struct {
uint8_t INTERLANE_ALIGN_DONE:1;
uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
uint8_t RESERVED:4;
uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
uint8_t LINK_STATUS_UPDATED:1;
} bits;
uint8_t raw;
};
union lane_adjust {
struct {
uint8_t VOLTAGE_SWING_LANE:2;
uint8_t PRE_EMPHASIS_LANE:2;
uint8_t RESERVED:4;
} bits;
uint8_t raw;
};
union dpcd_training_pattern {
struct {
uint8_t TRAINING_PATTERN_SET:4;
uint8_t RECOVERED_CLOCK_OUT_EN:1;
uint8_t SCRAMBLING_DISABLE:1;
uint8_t SYMBOL_ERROR_COUNT_SEL:2;
} v1_4;
struct {
uint8_t TRAINING_PATTERN_SET:2;
uint8_t LINK_QUAL_PATTERN_SET:2;
uint8_t RESERVED:4;
} v1_3;
uint8_t raw;
};
/* Training Lane is used to configure downstream DP device's voltage swing
and pre-emphasis levels*/
/* The DPCD addresses are from 0x103 to 0x106*/
union dpcd_training_lane {
struct {
uint8_t VOLTAGE_SWING_SET:2;
uint8_t MAX_SWING_REACHED:1;
uint8_t PRE_EMPHASIS_SET:2;
uint8_t MAX_PRE_EMPHASIS_REACHED:1;
uint8_t RESERVED:2;
} bits;
uint8_t raw;
};
/* TMDS-converter related */
union dwnstream_port_caps_byte0 {
struct {
uint8_t DWN_STRM_PORTX_TYPE:3;
uint8_t DWN_STRM_PORTX_HPD:1;
uint8_t RESERVERD:4;
} bits;
uint8_t raw;
};
/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
enum dpcd_downstream_port_detailed_type {
DOWN_STREAM_DETAILED_DP = 0,
DOWN_STREAM_DETAILED_VGA,
DOWN_STREAM_DETAILED_DVI,
DOWN_STREAM_DETAILED_HDMI,
DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
DOWN_STREAM_DETAILED_DP_PLUS_PLUS
};
union dwnstream_port_caps_byte1 {
struct {
uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
uint8_t RESERVED:6;
} bits;
uint8_t raw;
};
union dp_downstream_port_present {
uint8_t byte;
struct {
uint8_t PORT_PRESENT:1;
uint8_t PORT_TYPE:2;
uint8_t FMT_CONVERSION:1;
uint8_t DETAILED_CAPS:1;
uint8_t RESERVED:3;
} fields;
};
union dwnstream_port_caps_byte3_dvi {
struct {
uint8_t RESERVED1:1;
uint8_t DUAL_LINK:1;
uint8_t HIGH_COLOR_DEPTH:1;
uint8_t RESERVED2:5;
} bits;
uint8_t raw;
};
union dwnstream_port_caps_byte3_hdmi {
struct {
uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
uint8_t YCrCr422_PASS_THROUGH:1;
uint8_t YCrCr420_PASS_THROUGH:1;
uint8_t YCrCr422_CONVERSION:1;
uint8_t YCrCr420_CONVERSION:1;
uint8_t RESERVED:3;
} bits;
uint8_t raw;
};
/*4-byte structure for detailed capabilities of a down-stream port
(DP-to-TMDS converter).*/
union sink_status {
struct {
uint8_t RX_PORT0_STATUS:1;
uint8_t RX_PORT1_STATUS:1;
uint8_t RESERVED:6;
} bits;
uint8_t raw;
};
/*6-byte structure corresponding to 6 registers (200h-205h)
read during handling of HPD-IRQ*/
union hpd_irq_data {
struct {
union sink_count sink_cnt;/* 200h */
union device_service_irq device_service_irq;/* 201h */
union lane_status lane01_status;/* 202h */
union lane_status lane23_status;/* 203h */
union lane_align_status_updated lane_status_updated;/* 204h */
union sink_status sink_status;
} bytes;
uint8_t raw[6];
};
union down_stream_port_count {
struct {
uint8_t DOWN_STR_PORT_COUNT:4;
uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
/*Bit 6 = MSA_TIMING_PAR_IGNORED
0 = Sink device requires the MSA timing parameters
1 = Sink device is capable of rendering incoming video
stream without MSA timing parameters*/
uint8_t IGNORE_MSA_TIMING_PARAM:1;
/*Bit 7 = OUI Support
0 = OUI not supported
1 = OUI supported
(OUI and Device Identification mandatory for DP 1.2)*/
uint8_t OUI_SUPPORT:1;
} bits;
uint8_t raw;
};
union down_spread_ctrl {
struct {
uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
/* Bits 4 = SPREAD_AMP. Spreading amplitude
0 = Main link signal is not downspread
1 = Main link signal is downspread <= 0.5%
with frequency in the range of 30kHz ~ 33kHz*/
uint8_t SPREAD_AMP:1;
uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
0 = Source device will send valid data for the MSA Timing Params
1 = Source device may send invalid data for these MSA Timing Params*/
uint8_t IGNORE_MSA_TIMING_PARAM:1;
} bits;
uint8_t raw;
};
union dpcd_edp_config {
struct {
uint8_t PANEL_MODE_EDP:1;
uint8_t FRAMING_CHANGE_ENABLE:1;
uint8_t RESERVED:5;
uint8_t PANEL_SELF_TEST_ENABLE:1;
} bits;
uint8_t raw;
};
struct dp_device_vendor_id {
uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
};
struct dp_sink_hw_fw_revision {
uint8_t ieee_hw_rev;
uint8_t ieee_fw_rev[2];
};
/*DPCD register of DP receiver capability field bits-*/
union edp_configuration_cap {
struct {
uint8_t ALT_SCRAMBLER_RESET:1;
uint8_t FRAMING_CHANGE:1;
uint8_t RESERVED:1;
uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
uint8_t RESERVED2:4;
} bits;
uint8_t raw;
};
union training_aux_rd_interval {
struct {
uint8_t TRAINIG_AUX_RD_INTERVAL:7;
uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
} bits;
uint8_t raw;
};
/* Automated test structures */
union test_request {
struct {
uint8_t LINK_TRAINING :1;
uint8_t LINK_TEST_PATTRN :1;
uint8_t EDID_REAT :1;
uint8_t PHY_TEST_PATTERN :1;
uint8_t AUDIO_TEST_PATTERN :1;
uint8_t RESERVED :1;
uint8_t TEST_STEREO_3D :1;
} bits;
uint8_t raw;
};
union test_response {
struct {
uint8_t ACK :1;
uint8_t NO_ACK :1;
uint8_t RESERVED :6;
} bits;
uint8_t raw;
};
union phy_test_pattern {
struct {
/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
* and 3 bits for DP1.2.
*/
uint8_t PATTERN :3;
/* BY speci, bit7:2 is 0 for DP1.1. */
uint8_t RESERVED :5;
} bits;
uint8_t raw;
};
/* States of Compliance Test Specification (CTS DP1.2). */
union compliance_test_state {
struct {
unsigned char STEREO_3D_RUNNING : 1;
unsigned char RESERVED : 7;
} bits;
unsigned char raw;
};
union link_test_pattern {
struct {
/* dpcd_link_test_patterns */
unsigned char PATTERN :2;
unsigned char RESERVED:6;
} bits;
unsigned char raw;
};
union test_misc {
struct dpcd_test_misc_bits {
unsigned char SYNC_CLOCK :1;
/* dpcd_test_color_format */
unsigned char CLR_FORMAT :2;
/* dpcd_test_dyn_range */
unsigned char DYN_RANGE :1;
unsigned char YCBCR :1;
/* dpcd_test_bit_depth */
unsigned char BPC :3;
} bits;
unsigned char raw;
};
#endif /* DC_DP_TYPES_H */

171
drivers/gpu/drm/amd/display/dc/dc_helper.c Normal file
View File

@ -0,0 +1,171 @@
/*
* dc_helper.c
*
* Created on: Aug 30, 2016
* Author: agrodzov
*/
#include "dm_services.h"
#include <stdarg.h>
uint32_t generic_reg_update_ex(const struct dc_context *ctx,
uint32_t addr, uint32_t reg_val, int n,
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
...)
{
uint32_t shift, mask, field_value;
int i = 1;
va_list ap;
va_start(ap, field_value1);
reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
while (i < n) {
shift = va_arg(ap, uint32_t);
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t);
reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
i++;
}
dm_write_reg(ctx, addr, reg_val);
va_end(ap);
return reg_val;
}
uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
uint8_t shift, uint32_t mask, uint32_t *field_value)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value = get_reg_field_value_ex(reg_val, mask, shift);
return reg_val;
}
uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
return reg_val;
}
uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
return reg_val;
}
uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
return reg_val;
}
uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
return reg_val;
}
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
* compiler won't be able to check for size match and is prone to stack corruption type of bugs
uint32_t generic_reg_get(const struct dc_context *ctx,
uint32_t addr, int n, ...)
{
uint32_t shift, mask;
uint32_t *field_value;
uint32_t reg_val;
int i = 0;
reg_val = dm_read_reg(ctx, addr);
va_list ap;
va_start(ap, n);
while (i < n) {
shift = va_arg(ap, uint32_t);
mask = va_arg(ap, uint32_t);
field_value = va_arg(ap, uint32_t *);
*field_value = get_reg_field_value_ex(reg_val, mask, shift);
i++;
}
va_end(ap);
return reg_val;
}
*/
uint32_t generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
const char *func_name, int line)
{
uint32_t field_value;
uint32_t reg_val;
int i;
/* something is terribly wrong if time out is > 200ms. (5Hz) */
ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
/* 35 seconds */
delay_between_poll_us = 35000;
time_out_num_tries = 1000;
}
for (i = 0; i <= time_out_num_tries; i++) {
if (i) {
if (delay_between_poll_us >= 1000)
msleep(delay_between_poll_us/1000);
else if (delay_between_poll_us > 0)
udelay(delay_between_poll_us);
}
reg_val = dm_read_reg(ctx, addr);
field_value = get_reg_field_value_ex(reg_val, mask, shift);
if (field_value == condition_value)
return reg_val;
}
dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
delay_between_poll_us, time_out_num_tries,
func_name, line);
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
BREAK_TO_DEBUGGER();
return reg_val;
}

706
drivers/gpu/drm/amd/display/dc/dc_hw_types.h Normal file
View File

@ -0,0 +1,706 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DC_HW_TYPES_H
#define DC_HW_TYPES_H
#include "os_types.h"
#include "fixed31_32.h"
#include "signal_types.h"
/******************************************************************************
* Data types for Virtual HW Layer of DAL3.
* (see DAL3 design documents for HW Layer definition)
*
* The intended uses are:
* 1. Generation pseudocode sequences for HW programming.
* 2. Implementation of real HW programming by HW Sequencer of DAL3.
*
* Note: do *not* add any types which are *not* used for HW programming - this
* will ensure separation of Logic layer from HW layer.
******************************************************************************/
union large_integer {
struct {
uint32_t low_part;
int32_t high_part;
};
struct {
uint32_t low_part;
int32_t high_part;
} u;
int64_t quad_part;
};
#define PHYSICAL_ADDRESS_LOC union large_integer
enum dc_plane_addr_type {
PLN_ADDR_TYPE_GRAPHICS = 0,
PLN_ADDR_TYPE_GRPH_STEREO,
PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
};
struct dc_plane_address {
enum dc_plane_addr_type type;
bool tmz_surface;
union {
struct{
PHYSICAL_ADDRESS_LOC addr;
PHYSICAL_ADDRESS_LOC meta_addr;
union large_integer dcc_const_color;
} grph;
/*stereo*/
struct {
PHYSICAL_ADDRESS_LOC left_addr;
PHYSICAL_ADDRESS_LOC left_meta_addr;
union large_integer left_dcc_const_color;
PHYSICAL_ADDRESS_LOC right_addr;
PHYSICAL_ADDRESS_LOC right_meta_addr;
union large_integer right_dcc_const_color;
} grph_stereo;
/*video progressive*/
struct {
PHYSICAL_ADDRESS_LOC luma_addr;
PHYSICAL_ADDRESS_LOC luma_meta_addr;
union large_integer luma_dcc_const_color;
PHYSICAL_ADDRESS_LOC chroma_addr;
PHYSICAL_ADDRESS_LOC chroma_meta_addr;
union large_integer chroma_dcc_const_color;
} video_progressive;
};
};
struct dc_size {
int width;
int height;
};
struct rect {
int x;
int y;
int width;
int height;
};
union plane_size {
/* Grph or Video will be selected
* based on format above:
* Use Video structure if
* format >= DalPixelFormat_VideoBegin
* else use Grph structure
*/
struct {
struct rect surface_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch
* is 32 pixel aligned.
*/
int surface_pitch;
} grph;
struct {
struct rect luma_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch is
* 32 pixel aligned.
*/
int luma_pitch;
struct rect chroma_size;
/* Graphic surface pitch in pixels.
* In LINEAR_GENERAL mode, pitch is
* 32 pixel aligned.
*/
int chroma_pitch;
} video;
};
struct dc_plane_dcc_param {
bool enable;
union {
struct {
int meta_pitch;
bool independent_64b_blks;
} grph;
struct {
int meta_pitch_l;
bool independent_64b_blks_l;
int meta_pitch_c;
bool independent_64b_blks_c;
} video;
};
};
/*Displayable pixel format in fb*/
enum surface_pixel_format {
SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
/*TOBE REMOVED paletta 256 colors*/
SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
/*16 bpp*/
SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
/*16 bpp*/
SURFACE_PIXEL_FORMAT_GRPH_RGB565,
/*32 bpp*/
SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
/*32 bpp swaped*/
SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
/*swaped*/
SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
/*TOBE REMOVED swaped, XR_BIAS has no differance
* for pixel layout than previous and we can
* delete this after discusion*/
SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
/*64 bpp */
SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
/*float*/
SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
/*swaped & float*/
SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
/*grow graphics here if necessary */
SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
SURFACE_PIXEL_FORMAT_INVALID
/*grow 444 video here if necessary */
};
/* Pixel format */
enum pixel_format {
/*graph*/
PIXEL_FORMAT_UNINITIALIZED,
PIXEL_FORMAT_INDEX8,
PIXEL_FORMAT_RGB565,
PIXEL_FORMAT_ARGB8888,
PIXEL_FORMAT_ARGB2101010,
PIXEL_FORMAT_ARGB2101010_XRBIAS,
PIXEL_FORMAT_FP16,
/*video*/
PIXEL_FORMAT_420BPP8,
PIXEL_FORMAT_420BPP10,
/*end of pixel format definition*/
PIXEL_FORMAT_INVALID,
PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
PIXEL_FORMAT_UNKNOWN
};
enum tile_split_values {
DC_DISPLAY_MICRO_TILING = 0x0,
DC_THIN_MICRO_TILING = 0x1,
DC_DEPTH_MICRO_TILING = 0x2,
DC_ROTATED_MICRO_TILING = 0x3,
};
/* TODO: These values come from hardware spec. We need to readdress this
* if they ever change.
*/
enum array_mode_values {
DC_ARRAY_LINEAR_GENERAL = 0,
DC_ARRAY_LINEAR_ALLIGNED,
DC_ARRAY_1D_TILED_THIN1,
DC_ARRAY_1D_TILED_THICK,
DC_ARRAY_2D_TILED_THIN1,
DC_ARRAY_PRT_TILED_THIN1,
DC_ARRAY_PRT_2D_TILED_THIN1,
DC_ARRAY_2D_TILED_THICK,
DC_ARRAY_2D_TILED_X_THICK,
DC_ARRAY_PRT_TILED_THICK,
DC_ARRAY_PRT_2D_TILED_THICK,
DC_ARRAY_PRT_3D_TILED_THIN1,
DC_ARRAY_3D_TILED_THIN1,
DC_ARRAY_3D_TILED_THICK,
DC_ARRAY_3D_TILED_X_THICK,
DC_ARRAY_PRT_3D_TILED_THICK,
};
enum tile_mode_values {
DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
};
enum swizzle_mode_values {
DC_SW_LINEAR = 0,
DC_SW_256B_S = 1,
DC_SW_256_D = 2,
DC_SW_256_R = 3,
DC_SW_4KB_S = 5,
DC_SW_4KB_D = 6,
DC_SW_4KB_R = 7,
DC_SW_64KB_S = 9,
DC_SW_64KB_D = 10,
DC_SW_64KB_R = 11,
DC_SW_VAR_S = 13,
DC_SW_VAR_D = 14,
DC_SW_VAR_R = 15,
DC_SW_64KB_S_T = 17,
DC_SW_64KB_D_T = 18,
DC_SW_4KB_S_X = 21,
DC_SW_4KB_D_X = 22,
DC_SW_4KB_R_X = 23,
DC_SW_64KB_S_X = 25,
DC_SW_64KB_D_X = 26,
DC_SW_64KB_R_X = 27,
DC_SW_VAR_S_X = 29,
DC_SW_VAR_D_X = 30,
DC_SW_VAR_R_X = 31,
DC_SW_MAX
};
union dc_tiling_info {
struct {
/* Specifies the number of memory banks for tiling
* purposes.
* Only applies to 2D and 3D tiling modes.
* POSSIBLE VALUES: 2,4,8,16
*/
unsigned int num_banks;
/* Specifies the number of tiles in the x direction
* to be incorporated into the same bank.
* Only applies to 2D and 3D tiling modes.
* POSSIBLE VALUES: 1,2,4,8
*/
unsigned int bank_width;
unsigned int bank_width_c;
/* Specifies the number of tiles in the y direction to
* be incorporated into the same bank.
* Only applies to 2D and 3D tiling modes.
* POSSIBLE VALUES: 1,2,4,8
*/
unsigned int bank_height;
unsigned int bank_height_c;
/* Specifies the macro tile aspect ratio. Only applies
* to 2D and 3D tiling modes.
*/
unsigned int tile_aspect;
unsigned int tile_aspect_c;
/* Specifies the number of bytes that will be stored
* contiguously for each tile.
* If the tile data requires more storage than this
* amount, it is split into multiple slices.
* This field must not be larger than
* GB_ADDR_CONFIG.DRAM_ROW_SIZE.
* Only applies to 2D and 3D tiling modes.
* For color render targets, TILE_SPLIT >= 256B.
*/
enum tile_split_values tile_split;
enum tile_split_values tile_split_c;
/* Specifies the addressing within a tile.
* 0x0 - DISPLAY_MICRO_TILING
* 0x1 - THIN_MICRO_TILING
* 0x2 - DEPTH_MICRO_TILING
* 0x3 - ROTATED_MICRO_TILING
*/
enum tile_mode_values tile_mode;
enum tile_mode_values tile_mode_c;
/* Specifies the number of pipes and how they are
* interleaved in the surface.
* Refer to memory addressing document for complete
* details and constraints.
*/
unsigned int pipe_config;
/* Specifies the tiling mode of the surface.
* THIN tiles use an 8x8x1 tile size.
* THICK tiles use an 8x8x4 tile size.
* 2D tiling modes rotate banks for successive Z slices
* 3D tiling modes rotate pipes and banks for Z slices
* Refer to memory addressing document for complete
* details and constraints.
*/
enum array_mode_values array_mode;
} gfx8;
struct {
unsigned int num_pipes;
unsigned int num_banks;
unsigned int pipe_interleave;
unsigned int num_shader_engines;
unsigned int num_rb_per_se;
unsigned int max_compressed_frags;
bool shaderEnable;
enum swizzle_mode_values swizzle;
bool meta_linear;
bool rb_aligned;
bool pipe_aligned;
} gfx9;
};
/* Rotation angle */
enum dc_rotation_angle {
ROTATION_ANGLE_0 = 0,
ROTATION_ANGLE_90,
ROTATION_ANGLE_180,
ROTATION_ANGLE_270,
ROTATION_ANGLE_COUNT
};
enum dc_scan_direction {
SCAN_DIRECTION_UNKNOWN = 0,
SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
};
struct dc_cursor_position {
uint32_t x;
uint32_t y;
uint32_t x_hotspot;
uint32_t y_hotspot;
/*
* This parameter indicates whether HW cursor should be enabled
*/
bool enable;
};
struct dc_cursor_mi_param {
unsigned int pixel_clk_khz;
unsigned int ref_clk_khz;
unsigned int viewport_x_start;
unsigned int viewport_width;
struct fixed31_32 h_scale_ratio;
};
/* IPP related types */
enum {
GAMMA_RGB_256_ENTRIES = 256,
GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
GAMMA_MAX_ENTRIES = 1024
};
enum dc_gamma_type {
GAMMA_RGB_256 = 1,
GAMMA_RGB_FLOAT_1024 = 2
};
struct dc_gamma {
struct kref refcount;
enum dc_gamma_type type;
unsigned int num_entries;
struct dc_gamma_entries {
struct fixed31_32 red[GAMMA_MAX_ENTRIES];
struct fixed31_32 green[GAMMA_MAX_ENTRIES];
struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
} entries;
/* private to DC core */
struct dc_context *ctx;
};
/* Used by both ipp amd opp functions*/
/* TODO: to be consolidated with enum color_space */
/*
* This enum is for programming CURSOR_MODE register field. What this register
* should be programmed to depends on OS requested cursor shape flags and what
* we stored in the cursor surface.
*/
enum dc_cursor_color_format {
CURSOR_MODE_MONO,
CURSOR_MODE_COLOR_1BIT_AND,
CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
};
/*
* This is all the parameters required by DAL in order to update the cursor
* attributes, including the new cursor image surface address, size, hotspot
* location, color format, etc.
*/
union dc_cursor_attribute_flags {
struct {
uint32_t ENABLE_MAGNIFICATION:1;
uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
uint32_t HORIZONTAL_MIRROR:1;
uint32_t VERTICAL_MIRROR:1;
uint32_t INVERT_PIXEL_DATA:1;
uint32_t ZERO_EXPANSION:1;
uint32_t MIN_MAX_INVERT:1;
uint32_t RESERVED:25;
} bits;
uint32_t value;
};
struct dc_cursor_attributes {
PHYSICAL_ADDRESS_LOC address;
uint32_t pitch;
/* Width and height should correspond to cursor surface width x heigh */
uint32_t width;
uint32_t height;
enum dc_cursor_color_format color_format;
/* In case we support HW Cursor rotation in the future */
enum dc_rotation_angle rotation_angle;
union dc_cursor_attribute_flags attribute_flags;
};
/* OPP */
enum dc_color_space {
COLOR_SPACE_UNKNOWN,
COLOR_SPACE_SRGB,
COLOR_SPACE_SRGB_LIMITED,
COLOR_SPACE_YCBCR601,
COLOR_SPACE_YCBCR709,
COLOR_SPACE_YCBCR601_LIMITED,
COLOR_SPACE_YCBCR709_LIMITED,
COLOR_SPACE_2020_RGB_FULLRANGE,
COLOR_SPACE_2020_RGB_LIMITEDRANGE,
COLOR_SPACE_2020_YCBCR,
COLOR_SPACE_ADOBERGB,
};
enum dc_dither_option {
DITHER_OPTION_DEFAULT,
DITHER_OPTION_DISABLE,
DITHER_OPTION_FM6,
DITHER_OPTION_FM8,
DITHER_OPTION_FM10,
DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
DITHER_OPTION_SPATIAL6,
DITHER_OPTION_SPATIAL8,
DITHER_OPTION_SPATIAL10,
DITHER_OPTION_TRUN6,
DITHER_OPTION_TRUN8,
DITHER_OPTION_TRUN10,
DITHER_OPTION_TRUN10_SPATIAL8,
DITHER_OPTION_TRUN10_SPATIAL6,
DITHER_OPTION_TRUN10_FM8,
DITHER_OPTION_TRUN10_FM6,
DITHER_OPTION_TRUN10_SPATIAL8_FM6,
DITHER_OPTION_SPATIAL10_FM8,
DITHER_OPTION_SPATIAL10_FM6,
DITHER_OPTION_TRUN8_SPATIAL6,
DITHER_OPTION_TRUN8_FM6,
DITHER_OPTION_SPATIAL8_FM6,
DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
DITHER_OPTION_INVALID
};
enum dc_quantization_range {
QUANTIZATION_RANGE_UNKNOWN,
QUANTIZATION_RANGE_FULL,
QUANTIZATION_RANGE_LIMITED
};
/* XFM */
/* used in struct dc_plane_state */
struct scaling_taps {
uint32_t v_taps;
uint32_t h_taps;
uint32_t v_taps_c;
uint32_t h_taps_c;
};
enum dc_timing_standard {
TIMING_STANDARD_UNDEFINED,
TIMING_STANDARD_DMT,
TIMING_STANDARD_GTF,
TIMING_STANDARD_CVT,
TIMING_STANDARD_CVT_RB,
TIMING_STANDARD_CEA770,
TIMING_STANDARD_CEA861,
TIMING_STANDARD_HDMI,
TIMING_STANDARD_TV_NTSC,
TIMING_STANDARD_TV_NTSC_J,
TIMING_STANDARD_TV_PAL,
TIMING_STANDARD_TV_PAL_M,
TIMING_STANDARD_TV_PAL_CN,
TIMING_STANDARD_TV_SECAM,
TIMING_STANDARD_EXPLICIT,
/*!< For explicit timings from EDID, VBIOS, etc.*/
TIMING_STANDARD_USER_OVERRIDE,
/*!< For mode timing override by user*/
TIMING_STANDARD_MAX
};
enum dc_color_depth {
COLOR_DEPTH_UNDEFINED,
COLOR_DEPTH_666,
COLOR_DEPTH_888,
COLOR_DEPTH_101010,
COLOR_DEPTH_121212,
COLOR_DEPTH_141414,
COLOR_DEPTH_161616,
COLOR_DEPTH_COUNT
};
enum dc_pixel_encoding {
PIXEL_ENCODING_UNDEFINED,
PIXEL_ENCODING_RGB,
PIXEL_ENCODING_YCBCR422,
PIXEL_ENCODING_YCBCR444,
PIXEL_ENCODING_YCBCR420,
PIXEL_ENCODING_COUNT
};
enum dc_aspect_ratio {
ASPECT_RATIO_NO_DATA,
ASPECT_RATIO_4_3,
ASPECT_RATIO_16_9,
ASPECT_RATIO_64_27,
ASPECT_RATIO_256_135,
ASPECT_RATIO_FUTURE
};
enum scanning_type {
SCANNING_TYPE_NODATA = 0,
SCANNING_TYPE_OVERSCAN,
SCANNING_TYPE_UNDERSCAN,
SCANNING_TYPE_FUTURE,
SCANNING_TYPE_UNDEFINED
};
struct dc_crtc_timing_flags {
uint32_t INTERLACE :1;
uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
it is positive polarity --reversed with dal1 or video bios define*/
uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
it is positive polarity --reversed with dal1 or video bios define*/
uint32_t HORZ_COUNT_BY_TWO:1;
uint32_t EXCLUSIVE_3D :1; /* if this bit set,
timing can be driven in 3D format only
and there is no corresponding 2D timing*/
uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
(right eye = '1', left eye = '0') */
uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled
when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
because corresponding 2D timing also present in the list*/
uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
and we want to match priority of corresponding 3D timing*/
uint32_t Y_ONLY :1;
uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
uint32_t DTD_COUNTER :5; /* values 1 to 16 */
uint32_t FORCE_HDR :1;
/* HDMI 2.0 - Support scrambling for TMDS character
* rates less than or equal to 340Mcsc */
uint32_t LTE_340MCSC_SCRAMBLE:1;
};
enum dc_timing_3d_format {
TIMING_3D_FORMAT_NONE,
TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
/* for active DP-HDMI dongle*/
TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
TIMING_3D_FORMAT_HW_FRAME_PACKING,
TIMING_3D_FORMAT_SW_FRAME_PACKING,
TIMING_3D_FORMAT_ROW_INTERLEAVE,
TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
TIMING_3D_FORMAT_SIDE_BY_SIDE,
TIMING_3D_FORMAT_TOP_AND_BOTTOM,
TIMING_3D_FORMAT_SBS_SW_PACKED,
/* Side-by-side, packed by application/driver into 2D frame*/
TIMING_3D_FORMAT_TB_SW_PACKED,
/* Top-and-bottom, packed by application/driver into 2D frame*/
TIMING_3D_FORMAT_MAX,
};
struct dc_crtc_timing {
uint32_t h_total;
uint32_t h_border_left;
uint32_t h_addressable;
uint32_t h_border_right;
uint32_t h_front_porch;
uint32_t h_sync_width;
uint32_t v_total;
uint32_t v_border_top;
uint32_t v_addressable;
uint32_t v_border_bottom;
uint32_t v_front_porch;
uint32_t v_sync_width;
uint32_t pix_clk_khz;
uint32_t vic;
uint32_t hdmi_vic;
enum dc_timing_3d_format timing_3d_format;
enum dc_color_depth display_color_depth;
enum dc_pixel_encoding pixel_encoding;
enum dc_aspect_ratio aspect_ratio;
enum scanning_type scan_type;
struct dc_crtc_timing_flags flags;
};
#define MAX_TG_COLOR_VALUE 0x3FF
struct tg_color {
/* Maximum 10 bits color value */
uint16_t color_r_cr;
uint16_t color_g_y;
uint16_t color_b_cb;
};
#endif /* DC_HW_TYPES_H */

652
drivers/gpu/drm/amd/display/dc/dc_types.h Normal file
View File

@ -0,0 +1,652 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DC_TYPES_H_
#define DC_TYPES_H_
#include "fixed32_32.h"
#include "fixed31_32.h"
#include "irq_types.h"
#include "dc_dp_types.h"
#include "dc_hw_types.h"
#include "dal_types.h"
#include "grph_object_defs.h"
/* forward declarations */
struct dc_plane_state;
struct dc_stream_state;
struct dc_link;
struct dc_sink;
struct dal;
/********************************
* Environment definitions
********************************/
enum dce_environment {
DCE_ENV_PRODUCTION_DRV = 0,
/* Emulation on FPGA, in "Maximus" System.
* This environment enforces that *only* DC registers accessed.
* (access to non-DC registers will hang FPGA) */
DCE_ENV_FPGA_MAXIMUS,
/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
* requirements of Diagnostics team. */
DCE_ENV_DIAG
};
/* Note: use these macro definitions instead of direct comparison! */
#define IS_FPGA_MAXIMUS_DC(dce_environment) \
(dce_environment == DCE_ENV_FPGA_MAXIMUS)
#define IS_DIAG_DC(dce_environment) \
(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
struct hw_asic_id {
uint32_t chip_id;
uint32_t chip_family;
uint32_t pci_revision_id;
uint32_t hw_internal_rev;
uint32_t vram_type;
uint32_t vram_width;
uint32_t feature_flags;
uint32_t fake_paths_num;
void *atombios_base_address;
};
struct dc_context {
struct dc *dc;
void *driver_context; /* e.g. amdgpu_device */
struct dal_logger *logger;
void *cgs_device;
enum dce_environment dce_environment;
struct hw_asic_id asic_id;
/* todo: below should probably move to dc. to facilitate removal
* of AS we will store these here
*/
enum dce_version dce_version;
struct dc_bios *dc_bios;
bool created_bios;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
#if defined(CONFIG_DRM_AMD_DC_FBC)
uint64_t fbc_gpu_addr;
#endif
};
#define MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
#define MAX_SURFACE_NUM 4
#define NUM_PIXEL_FORMATS 10
#include "dc_ddc_types.h"
enum tiling_mode {
TILING_MODE_INVALID,
TILING_MODE_LINEAR,
TILING_MODE_TILED,
TILING_MODE_COUNT
};
enum view_3d_format {
VIEW_3D_FORMAT_NONE = 0,
VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
VIEW_3D_FORMAT_SIDE_BY_SIDE,
VIEW_3D_FORMAT_TOP_AND_BOTTOM,
VIEW_3D_FORMAT_COUNT,
VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
};
enum plane_stereo_format {
PLANE_STEREO_FORMAT_NONE = 0,
PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
};
/* TODO: Find way to calculate number of bits
* Please increase if pixel_format enum increases
* num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
*/
enum dc_edid_connector_type {
EDID_CONNECTOR_UNKNOWN = 0,
EDID_CONNECTOR_ANALOG = 1,
EDID_CONNECTOR_DIGITAL = 10,
EDID_CONNECTOR_DVI = 11,
EDID_CONNECTOR_HDMIA = 12,
EDID_CONNECTOR_MDDI = 14,
EDID_CONNECTOR_DISPLAYPORT = 15
};
enum dc_edid_status {
EDID_OK,
EDID_BAD_INPUT,
EDID_NO_RESPONSE,
EDID_BAD_CHECKSUM,
EDID_THE_SAME,
};
/* audio capability from EDID*/
struct dc_cea_audio_mode {
uint8_t format_code; /* ucData[0] [6:3]*/
uint8_t channel_count; /* ucData[0] [2:0]*/
uint8_t sample_rate; /* ucData[1]*/
union {
uint8_t sample_size; /* for LPCM*/
/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
uint8_t max_bit_rate;
uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
};
};
struct dc_edid {
uint32_t length;
uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
};
/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
* is used. In this case we assume speaker location are: front left, front
* right and front center. */
#define DEFAULT_SPEAKER_LOCATION 5
#define DC_MAX_AUDIO_DESC_COUNT 16
#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
union display_content_support {
unsigned int raw;
struct {
unsigned int valid_content_type :1;
unsigned int game_content :1;
unsigned int cinema_content :1;
unsigned int photo_content :1;
unsigned int graphics_content :1;
unsigned int reserved :27;
} bits;
};
struct dc_edid_caps {
/* sink identification */
uint16_t manufacturer_id;
uint16_t product_id;
uint32_t serial_number;
uint8_t manufacture_week;
uint8_t manufacture_year;
uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
/* audio caps */
uint8_t speaker_flags;
uint32_t audio_mode_count;
struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
uint32_t audio_latency;
uint32_t video_latency;
union display_content_support content_support;
uint8_t qs_bit;
uint8_t qy_bit;
/*HDMI 2.0 caps*/
bool lte_340mcsc_scramble;
bool edid_hdmi;
};
struct view {
uint32_t width;
uint32_t height;
};
struct dc_mode_flags {
/* note: part of refresh rate flag*/
uint32_t INTERLACE :1;
/* native display timing*/
uint32_t NATIVE :1;
/* preferred is the recommended mode, one per display */
uint32_t PREFERRED :1;
/* true if this mode should use reduced blanking timings
*_not_ related to the Reduced Blanking adjustment*/
uint32_t REDUCED_BLANKING :1;
/* note: part of refreshrate flag*/
uint32_t VIDEO_OPTIMIZED_RATE :1;
/* should be reported to upper layers as mode_flags*/
uint32_t PACKED_PIXEL_FORMAT :1;
/*< preferred view*/
uint32_t PREFERRED_VIEW :1;
/* this timing should be used only in tiled mode*/
uint32_t TILED_MODE :1;
uint32_t DSE_MODE :1;
/* Refresh rate divider when Miracast sink is using a
different rate than the output display device
Must be zero for wired displays and non-zero for
Miracast displays*/
uint32_t MIRACAST_REFRESH_DIVIDER;
};
enum dc_timing_source {
TIMING_SOURCE_UNDEFINED,
/* explicitly specifed by user, most important*/
TIMING_SOURCE_USER_FORCED,
TIMING_SOURCE_USER_OVERRIDE,
TIMING_SOURCE_CUSTOM,
TIMING_SOURCE_EXPLICIT,
/* explicitly specified by the display device, more important*/
TIMING_SOURCE_EDID_CEA_SVD_3D,
TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
TIMING_SOURCE_EDID_CEA_SVD_420,
TIMING_SOURCE_EDID_DETAILED,
TIMING_SOURCE_EDID_ESTABLISHED,
TIMING_SOURCE_EDID_STANDARD,
TIMING_SOURCE_EDID_CEA_SVD,
TIMING_SOURCE_EDID_CVT_3BYTE,
TIMING_SOURCE_EDID_4BYTE,
TIMING_SOURCE_VBIOS,
TIMING_SOURCE_CV,
TIMING_SOURCE_TV,
TIMING_SOURCE_HDMI_VIC,
/* implicitly specified by display device, still safe but less important*/
TIMING_SOURCE_DEFAULT,
/* only used for custom base modes */
TIMING_SOURCE_CUSTOM_BASE,
/* these timing might not work, least important*/
TIMING_SOURCE_RANGELIMIT,
TIMING_SOURCE_OS_FORCED,
TIMING_SOURCE_IMPLICIT,
/* only used by default mode list*/
TIMING_SOURCE_BASICMODE,
TIMING_SOURCE_COUNT
};
struct stereo_3d_features {
bool supported ;
bool allTimings ;
bool cloneMode ;
bool scaling ;
bool singleFrameSWPacked;
};
enum dc_timing_support_method {
TIMING_SUPPORT_METHOD_UNDEFINED,
TIMING_SUPPORT_METHOD_EXPLICIT,
TIMING_SUPPORT_METHOD_IMPLICIT,
TIMING_SUPPORT_METHOD_NATIVE
};
struct dc_mode_info {
uint32_t pixel_width;
uint32_t pixel_height;
uint32_t field_rate;
/* Vertical refresh rate for progressive modes.
* Field rate for interlaced modes.*/
enum dc_timing_standard timing_standard;
enum dc_timing_source timing_source;
struct dc_mode_flags flags;
};
enum dc_power_state {
DC_POWER_STATE_ON = 1,
DC_POWER_STATE_STANDBY,
DC_POWER_STATE_SUSPEND,
DC_POWER_STATE_OFF
};
/* DC PowerStates */
enum dc_video_power_state {
DC_VIDEO_POWER_UNSPECIFIED = 0,
DC_VIDEO_POWER_ON = 1,
DC_VIDEO_POWER_STANDBY,
DC_VIDEO_POWER_SUSPEND,
DC_VIDEO_POWER_OFF,
DC_VIDEO_POWER_HIBERNATE,
DC_VIDEO_POWER_SHUTDOWN,
DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
DC_VIDEO_POWER_AFTER_RESET,
DC_VIDEO_POWER_MAXIMUM
};
enum dc_acpi_cm_power_state {
DC_ACPI_CM_POWER_STATE_D0 = 1,
DC_ACPI_CM_POWER_STATE_D1 = 2,
DC_ACPI_CM_POWER_STATE_D2 = 4,
DC_ACPI_CM_POWER_STATE_D3 = 8
};
enum dc_connection_type {
dc_connection_none,
dc_connection_single,
dc_connection_mst_branch,
dc_connection_active_dongle
};
struct dc_csc_adjustments {
struct fixed31_32 contrast;
struct fixed31_32 saturation;
struct fixed31_32 brightness;
struct fixed31_32 hue;
};
enum {
MAX_LANES = 2,
MAX_COFUNC_PATH = 6,
LAYER_INDEX_PRIMARY = -1,
};
enum dpcd_downstream_port_max_bpc {
DOWN_STREAM_MAX_8BPC = 0,
DOWN_STREAM_MAX_10BPC,
DOWN_STREAM_MAX_12BPC,
DOWN_STREAM_MAX_16BPC
};
struct dc_dongle_caps {
/* dongle type (DP converter, CV smart dongle) */
enum display_dongle_type dongle_type;
bool extendedCapValid;
/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
bool is_dp_hdmi_s3d_converter;
bool is_dp_hdmi_ycbcr422_pass_through;
bool is_dp_hdmi_ycbcr420_pass_through;
bool is_dp_hdmi_ycbcr422_converter;
bool is_dp_hdmi_ycbcr420_converter;
uint32_t dp_hdmi_max_bpc;
uint32_t dp_hdmi_max_pixel_clk;
};
/* Scaling format */
enum scaling_transformation {
SCALING_TRANSFORMATION_UNINITIALIZED,
SCALING_TRANSFORMATION_IDENTITY = 0x0001,
SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
SCALING_TRANSFORMATION_INVALID = 0x80000000,
/* Flag the first and last */
SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
SCALING_TRANSFORMATION_END =
SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
};
enum display_content_type {
DISPLAY_CONTENT_TYPE_NO_DATA = 0,
DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
DISPLAY_CONTENT_TYPE_PHOTO = 2,
DISPLAY_CONTENT_TYPE_CINEMA = 4,
DISPLAY_CONTENT_TYPE_GAME = 8
};
/* audio*/
union audio_sample_rates {
struct sample_rates {
uint8_t RATE_32:1;
uint8_t RATE_44_1:1;
uint8_t RATE_48:1;
uint8_t RATE_88_2:1;
uint8_t RATE_96:1;
uint8_t RATE_176_4:1;
uint8_t RATE_192:1;
} rate;
uint8_t all;
};
struct audio_speaker_flags {
uint32_t FL_FR:1;
uint32_t LFE:1;
uint32_t FC:1;
uint32_t RL_RR:1;
uint32_t RC:1;
uint32_t FLC_FRC:1;
uint32_t RLC_RRC:1;
uint32_t SUPPORT_AI:1;
};
struct audio_speaker_info {
uint32_t ALLSPEAKERS:7;
uint32_t SUPPORT_AI:1;
};
struct audio_info_flags {
union {
struct audio_speaker_flags speaker_flags;
struct audio_speaker_info info;
uint8_t all;
};
};
enum audio_format_code {
AUDIO_FORMAT_CODE_FIRST = 1,
AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
AUDIO_FORMAT_CODE_AC3,
/*Layers 1 & 2 */
AUDIO_FORMAT_CODE_MPEG1,
/*MPEG1 Layer 3 */
AUDIO_FORMAT_CODE_MP3,
/*multichannel */
AUDIO_FORMAT_CODE_MPEG2,
AUDIO_FORMAT_CODE_AAC,
AUDIO_FORMAT_CODE_DTS,
AUDIO_FORMAT_CODE_ATRAC,
AUDIO_FORMAT_CODE_1BITAUDIO,
AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
AUDIO_FORMAT_CODE_DTS_HD,
AUDIO_FORMAT_CODE_MAT_MLP,
AUDIO_FORMAT_CODE_DST,
AUDIO_FORMAT_CODE_WMAPRO,
AUDIO_FORMAT_CODE_LAST,
AUDIO_FORMAT_CODE_COUNT =
AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
};
struct audio_mode {
/* ucData[0] [6:3] */
enum audio_format_code format_code;
/* ucData[0] [2:0] */
uint8_t channel_count;
/* ucData[1] */
union audio_sample_rates sample_rates;
union {
/* for LPCM */
uint8_t sample_size;
/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
uint8_t max_bit_rate;
/* for Audio Formats 9-15 */
uint8_t vendor_specific;
};
};
struct audio_info {
struct audio_info_flags flags;
uint32_t video_latency;
uint32_t audio_latency;
uint32_t display_index;
uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
uint32_t manufacture_id;
uint32_t product_id;
/* PortID used for ContainerID when defined */
uint32_t port_id[2];
uint32_t mode_count;
/* this field must be last in this struct */
struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
};
struct freesync_context {
bool supported;
bool enabled;
bool active;
unsigned int min_refresh_in_micro_hz;
unsigned int nominal_refresh_in_micro_hz;
};
struct psr_config {
unsigned char psr_version;
unsigned int psr_rfb_setup_time;
bool psr_exit_link_training_required;
bool psr_frame_capture_indication_req;
unsigned int psr_sdp_transmit_line_num_deadline;
};
union dmcu_psr_level {
struct {
unsigned int SKIP_CRC:1;
unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
unsigned int SKIP_PHY_POWER_DOWN:1;
unsigned int SKIP_AUX_ACK_CHECK:1;
unsigned int SKIP_CRTC_DISABLE:1;
unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
unsigned int SKIP_SMU_NOTIFICATION:1;
unsigned int SKIP_AUTO_STATE_ADVANCE:1;
unsigned int DISABLE_PSR_ENTRY_ABORT:1;
unsigned int SKIP_SINGLE_OTG_DISABLE:1;
unsigned int RESERVED:22;
} bits;
unsigned int u32all;
};
enum physical_phy_id {
PHYLD_0,
PHYLD_1,
PHYLD_2,
PHYLD_3,
PHYLD_4,
PHYLD_5,
PHYLD_6,
PHYLD_7,
PHYLD_8,
PHYLD_9,
PHYLD_COUNT,
PHYLD_UNKNOWN = (-1L)
};
enum phy_type {
PHY_TYPE_UNKNOWN = 1,
PHY_TYPE_PCIE_PHY = 2,
PHY_TYPE_UNIPHY = 3,
};
struct psr_context {
/* ddc line */
enum channel_id channel;
/* Transmitter id */
enum transmitter transmitterId;
/* Engine Id is used for Dig Be source select */
enum engine_id engineId;
/* Controller Id used for Dig Fe source select */
enum controller_id controllerId;
/* Pcie or Uniphy */
enum phy_type phyType;
/* Physical PHY Id used by SMU interpretation */
enum physical_phy_id smuPhyId;
/* Vertical total pixels from crtc timing.
* This is used for static screen detection.
* ie. If we want to detect half a frame,
* we use this to determine the hyst lines.
*/
unsigned int crtcTimingVerticalTotal;
/* PSR supported from panel capabilities and
* current display configuration
*/
bool psrSupportedDisplayConfig;
/* Whether fast link training is supported by the panel */
bool psrExitLinkTrainingRequired;
/* If RFB setup time is greater than the total VBLANK time,
* it is not possible for the sink to capture the video frame
* in the same frame the SDP is sent. In this case,
* the frame capture indication bit should be set and an extra
* static frame should be transmitted to the sink.
*/
bool psrFrameCaptureIndicationReq;
/* Set the last possible line SDP may be transmitted without violating
* the RFB setup time or entering the active video frame.
*/
unsigned int sdpTransmitLineNumDeadline;
/* The VSync rate in Hz used to calculate the
* step size for smooth brightness feature
*/
unsigned int vsyncRateHz;
unsigned int skipPsrWaitForPllLock;
unsigned int numberOfControllers;
/* Unused, for future use. To indicate that first changed frame from
* state3 shouldn't result in psr_inactive, but rather to perform
* an automatic single frame rfb_update.
*/
bool rfb_update_auto_en;
/* Number of frame before entering static screen */
unsigned int timehyst_frames;
/* Partial frames before entering static screen */
unsigned int hyst_lines;
/* # of repeated AUX transaction attempts to make before
* indicating failure to the driver
*/
unsigned int aux_repeats;
/* Controls hw blocks to power down during PSR active state */
union dmcu_psr_level psr_level;
/* Controls additional delay after remote frame capture before
* continuing powerd own
*/
unsigned int frame_delay;
};
struct colorspace_transform {
struct fixed31_32 matrix[12];
bool enable_remap;
};
struct csc_transform {
uint16_t matrix[12];
bool enable_adjustment;
};
enum i2c_mot_mode {
I2C_MOT_UNDEF,
I2C_MOT_TRUE,
I2C_MOT_FALSE
};
#endif /* DC_TYPES_H_ */

15
drivers/gpu/drm/amd/display/dc/dce/Makefile Normal file
View File

@ -0,0 +1,15 @@
#
# Makefile for common 'dce' logic
# HW object file under this folder follow similar pattern for HW programming
# - register offset and/or shift + mask stored in the dec_hw struct
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
AMD_DISPLAY_FILES += $(AMD_DAL_DCE)

485
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c Normal file
View File

@ -0,0 +1,485 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dce_abm.h"
#include "dm_services.h"
#include "reg_helper.h"
#include "fixed32_32.h"
#include "dc.h"
#include "atom.h"
#define TO_DCE_ABM(abm)\
container_of(abm, struct dce_abm, base)
#define REG(reg) \
(abm_dce->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
#define CTX \
abm_dce->base.ctx
#define MCP_ABM_LEVEL_SET 0x65
#define MCP_ABM_PIPE_SET 0x66
#define MCP_BL_SET 0x67
#define MCP_DISABLE_ABM_IMMEDIATELY 255
struct abm_backlight_registers {
unsigned int BL_PWM_CNTL;
unsigned int BL_PWM_CNTL2;
unsigned int BL_PWM_PERIOD_CNTL;
unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
};
/* registers setting needs to be save and restored used at InitBacklight */
static struct abm_backlight_registers stored_backlight_registers = {0};
static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
{
uint64_t current_backlight;
uint32_t round_result;
uint32_t pwm_period_cntl, bl_period, bl_int_count;
uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
uint32_t bl_period_mask, bl_pwm_mask;
pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
if (bl_int_count == 0)
bl_int_count = 16;
bl_period_mask = (1 << bl_int_count) - 1;
bl_period &= bl_period_mask;
bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
if (fractional_duty_cycle_en == 0)
bl_pwm &= bl_pwm_mask;
else
bl_pwm &= 0xFFFF;
current_backlight = bl_pwm << (1 + bl_int_count);
if (bl_period == 0)
bl_period = 0xFFFF;
current_backlight = div_u64(current_backlight, bl_period);
current_backlight = (current_backlight + 1) >> 1;
current_backlight = (uint64_t)(current_backlight) * bl_period;
round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
round_result = (round_result >> (bl_int_count-1)) & 1;
current_backlight >>= bl_int_count;
current_backlight += round_result;
return (uint32_t)(current_backlight);
}
static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level)
{
uint32_t backlight_24bit;
uint32_t backlight_17bit;
uint32_t backlight_16bit;
uint32_t masked_pwm_period;
uint8_t rounding_bit;
uint8_t bit_count;
uint64_t active_duty_cycle;
uint32_t pwm_period_bitcnt;
/*
* 1. Convert 8-bit value to 17 bit U1.16 format
* (1 integer, 16 fractional bits)
*/
/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
* effectively multiplying value by 256/255
* eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
*/
backlight_24bit = level * 0x10101;
/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
* used for rounding, take most significant bit of fraction for
* rounding, e.g. for 0xEFEFEF, rounding bit is 1
*/
rounding_bit = (backlight_24bit >> 7) & 1;
/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
* resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
*/
backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
/*
* 2. Find 16 bit backlight active duty cycle, where 0 <= backlight
* active duty cycle <= backlight period
*/
/* 2.1 Apply bitmask for backlight period value based on value of BITCNT
*/
REG_GET_2(BL_PWM_PERIOD_CNTL,
BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
BL_PWM_PERIOD, &masked_pwm_period);
if (pwm_period_bitcnt == 0)
bit_count = 16;
else
bit_count = pwm_period_bitcnt;
/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
/* 2.2 Calculate integer active duty cycle required upper 16 bits
* contain integer component, lower 16 bits contain fractional component
* of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
*/
active_duty_cycle = backlight_17bit * masked_pwm_period;
/* 2.3 Calculate 16 bit active duty cycle from integer and fractional
* components shift by bitCount then mask 16 bits and add rounding bit
* from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
*/
backlight_16bit = active_duty_cycle >> bit_count;
backlight_16bit &= 0xFFFF;
backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
/*
* 3. Program register with updated value
*/
/* 3.1 Lock group 2 backlight registers */
REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
BL_PWM_GRP1_REG_LOCK, 1);
// 3.2 Write new active duty cycle
REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
/* 3.3 Unlock group 2 backlight registers */
REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK, 0);
/* 5.4.4 Wait for pending bit to be cleared */
REG_WAIT(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
1, 10000);
}
static void dmcu_set_backlight_level(
struct dce_abm *abm_dce,
uint32_t level,
uint32_t frame_ramp,
uint32_t controller_id)
{
unsigned int backlight_16_bit = (level * 0x10101) >> 8;
unsigned int backlight_17_bit = backlight_16_bit +
(((backlight_16_bit & 0x80) >> 7) & 1);
uint32_t rampingBoundary = 0xFFFF;
uint32_t s2;
/* set ramping boundary */
REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
/* setDMCUParam_Pipe */
REG_UPDATE_2(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
MASTER_COMM_CMD_REG_BYTE1, controller_id);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
0, 1, 80000);
/* setDMCUParam_BL */
REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
/* write ramp */
if (controller_id == 0)
frame_ramp = 0;
REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
/* setDMCUParam_Cmd */
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
/* UpdateRequestedBacklightLevel */
s2 = REG_READ(BIOS_SCRATCH_2);
s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
REG_WRITE(BIOS_SCRATCH_2, s2);
}
static void dce_abm_init(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
unsigned int backlight = get_current_backlight_16_bit(abm_dce);
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
ABM1_HG_NUM_OF_BINS_SEL, 0,
ABM1_HG_VMAX_SEL, 1,
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
ABM1_IPCSC_COEFF_SEL_R, 2,
ABM1_IPCSC_COEFF_SEL_G, 4,
ABM1_IPCSC_COEFF_SEL_B, 2);
REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
BL1_PWM_CURRENT_ABM_LEVEL, backlight);
REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
BL1_PWM_TARGET_ABM_LEVEL, backlight);
REG_UPDATE(BL1_PWM_USER_LEVEL,
BL1_PWM_USER_LEVEL, backlight);
REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
}
static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
return (backlight >> 8);
}
static bool dce_abm_set_level(struct abm *abm, uint32_t level)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
1, 80000);
/* setDMCUParam_ABMLevel */
REG_UPDATE_2(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
MASTER_COMM_CMD_REG_BYTE2, level);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
return true;
}
static bool dce_abm_immediate_disable(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
1, 80000);
/* setDMCUParam_ABMLevel */
REG_UPDATE_2(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
return true;
}
static bool dce_abm_init_backlight(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
uint32_t value;
/* It must not be 0, so we have to restore them
* Bios bug w/a - period resets to zero,
* restoring to cache values which is always correct
*/
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
if (value == 0 || value == 1) {
if (stored_backlight_registers.BL_PWM_CNTL != 0) {
REG_WRITE(BL_PWM_CNTL,
stored_backlight_registers.BL_PWM_CNTL);
REG_WRITE(BL_PWM_CNTL2,
stored_backlight_registers.BL_PWM_CNTL2);
REG_WRITE(BL_PWM_PERIOD_CNTL,
stored_backlight_registers.BL_PWM_PERIOD_CNTL);
REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
BL_PWM_REF_DIV,
stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else {
/* TODO: Note: This should not really happen since VBIOS
* should have initialized PWM registers on boot.
*/
REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
}
} else {
stored_backlight_registers.BL_PWM_CNTL =
REG_READ(BL_PWM_CNTL);
stored_backlight_registers.BL_PWM_CNTL2 =
REG_READ(BL_PWM_CNTL2);
stored_backlight_registers.BL_PWM_PERIOD_CNTL =
REG_READ(BL_PWM_PERIOD_CNTL);
REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
&stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
}
/* Have driver take backlight control
* TakeBacklightControl(true)
*/
value = REG_READ(BIOS_SCRATCH_2);
value |= ATOM_S2_VRI_BRIGHT_ENABLE;
REG_WRITE(BIOS_SCRATCH_2, value);
/* Enable the backlight output */
REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
/* Unlock group 2 backlight registers */
REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK, 0);
return true;
}
static bool is_dmcu_initialized(struct abm *abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
unsigned int dmcu_uc_reset;
REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
return !dmcu_uc_reset;
}
static bool dce_abm_set_backlight_level(
struct abm *abm,
unsigned int backlight_level,
unsigned int frame_ramp,
unsigned int controller_id)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT,
"New Backlight level: %d (0x%X)\n",
backlight_level, backlight_level);
/* If DMCU is in reset state, DMCU is uninitialized */
if (is_dmcu_initialized(abm))
dmcu_set_backlight_level(abm_dce,
backlight_level,
frame_ramp,
controller_id);
else
driver_set_backlight_level(abm_dce, backlight_level);
return true;
}
static const struct abm_funcs dce_funcs = {
.abm_init = dce_abm_init,
.set_abm_level = dce_abm_set_level,
.init_backlight = dce_abm_init_backlight,
.set_backlight_level = dce_abm_set_backlight_level,
.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
.set_abm_immediate_disable = dce_abm_immediate_disable,
.is_dmcu_initialized = is_dmcu_initialized
};
static void dce_abm_construct(
struct dce_abm *abm_dce,
struct dc_context *ctx,
const struct dce_abm_registers *regs,
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
struct abm *base = &abm_dce->base;
base->ctx = ctx;
base->funcs = &dce_funcs;
abm_dce->regs = regs;
abm_dce->abm_shift = abm_shift;
abm_dce->abm_mask = abm_mask;
}
struct abm *dce_abm_create(
struct dc_context *ctx,
const struct dce_abm_registers *regs,
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask)
{
struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
if (abm_dce == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
abm_dce->base.funcs = &dce_funcs;
return &abm_dce->base;
}
void dce_abm_destroy(struct abm **abm)
{
struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
kfree(abm_dce);
*abm = NULL;
}

228
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h Normal file
View File

@ -0,0 +1,228 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCE_ABM_H_
#define _DCE_ABM_H_
#include "abm.h"
#define ABM_COMMON_REG_LIST_DCE_BASE() \
SR(BL_PWM_PERIOD_CNTL), \
SR(BL_PWM_CNTL), \
SR(BL_PWM_CNTL2), \
SR(BL_PWM_GRP1_REG_LOCK), \
SR(LVTMA_PWRSEQ_REF_DIV), \
SR(MASTER_COMM_CNTL_REG), \
SR(MASTER_COMM_CMD_REG), \
SR(MASTER_COMM_DATA_REG1), \
SR(DMCU_STATUS)
#define ABM_DCE110_COMMON_REG_LIST() \
ABM_COMMON_REG_LIST_DCE_BASE(), \
SR(DC_ABM1_HG_SAMPLE_RATE), \
SR(DC_ABM1_LS_SAMPLE_RATE), \
SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
SR(DC_ABM1_HG_MISC_CTRL), \
SR(DC_ABM1_IPCSC_COEFF_SEL), \
SR(BL1_PWM_CURRENT_ABM_LEVEL), \
SR(BL1_PWM_TARGET_ABM_LEVEL), \
SR(BL1_PWM_USER_LEVEL), \
SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
SR(BIOS_SCRATCH_2)
#define ABM_DCN10_REG_LIST(id)\
ABM_COMMON_REG_LIST_DCE_BASE(), \
SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
SRI(BL1_PWM_USER_LEVEL, ABM, id), \
SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
NBIO_SR(BIOS_SCRATCH_2)
#define ABM_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \
ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh)
#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
ABM_SF(DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_VMAX_SEL, mask_sh), \
ABM_SF(DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
ABM_SF(BL1_PWM_USER_LEVEL, \
BL1_PWM_USER_LEVEL, mask_sh), \
ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_VMAX_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
BL1_PWM_USER_LEVEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
type ABM1_IPCSC_COEFF_SEL_R; \
type ABM1_IPCSC_COEFF_SEL_G; \
type ABM1_IPCSC_COEFF_SEL_B; \
type BL1_PWM_CURRENT_ABM_LEVEL; \
type BL1_PWM_TARGET_ABM_LEVEL; \
type BL1_PWM_USER_LEVEL; \
type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
type BL_PWM_PERIOD; \
type BL_PWM_PERIOD_BITCNT; \
type BL_ACTIVE_INT_FRAC_CNT; \
type BL_PWM_FRACTIONAL_EN; \
type MASTER_COMM_INTERRUPT; \
type MASTER_COMM_CMD_REG_BYTE0; \
type MASTER_COMM_CMD_REG_BYTE1; \
type MASTER_COMM_CMD_REG_BYTE2; \
type BL_PWM_REF_DIV; \
type BL_PWM_EN; \
type UC_IN_RESET; \
type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
type BL_PWM_GRP1_REG_LOCK; \
type BL_PWM_GRP1_REG_UPDATE_PENDING
struct dce_abm_shift {
ABM_REG_FIELD_LIST(uint8_t);
};
struct dce_abm_mask {
ABM_REG_FIELD_LIST(uint32_t);
};
struct dce_abm_registers {
uint32_t BL_PWM_PERIOD_CNTL;
uint32_t BL_PWM_CNTL;
uint32_t BL_PWM_CNTL2;
uint32_t LVTMA_PWRSEQ_REF_DIV;
uint32_t DC_ABM1_HG_SAMPLE_RATE;
uint32_t DC_ABM1_LS_SAMPLE_RATE;
uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
uint32_t DC_ABM1_HG_MISC_CTRL;
uint32_t DC_ABM1_IPCSC_COEFF_SEL;
uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
uint32_t BL1_PWM_TARGET_ABM_LEVEL;
uint32_t BL1_PWM_USER_LEVEL;
uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
uint32_t MASTER_COMM_CNTL_REG;
uint32_t MASTER_COMM_CMD_REG;
uint32_t MASTER_COMM_DATA_REG1;
uint32_t BIOS_SCRATCH_2;
uint32_t DMCU_STATUS;
uint32_t BL_PWM_GRP1_REG_LOCK;
};
struct dce_abm {
struct abm base;
const struct dce_abm_registers *regs;
const struct dce_abm_shift *abm_shift;
const struct dce_abm_mask *abm_mask;
};
struct abm *dce_abm_create(
struct dc_context *ctx,
const struct dce_abm_registers *regs,
const struct dce_abm_shift *abm_shift,
const struct dce_abm_mask *abm_mask);
void dce_abm_destroy(struct abm **abm);
#endif /* _DCE_ABM_H_ */

945
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c Normal file
View File

@ -0,0 +1,945 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "reg_helper.h"
#include "dce_audio.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#define DCE_AUD(audio)\
container_of(audio, struct dce_audio, base)
#define CTX \
aud->base.ctx
#define REG(reg)\
(aud->regs->reg)
#undef FN
#define FN(reg_name, field_name) \
aud->shifts->field_name, aud->masks->field_name
#define IX_REG(reg)\
ix ## reg
#define AZ_REG_READ(reg_name) \
read_indirect_azalia_reg(audio, IX_REG(reg_name))
#define AZ_REG_WRITE(reg_name, value) \
write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
static void write_indirect_azalia_reg(struct audio *audio,
uint32_t reg_index,
uint32_t reg_data)
{
struct dce_audio *aud = DCE_AUD(audio);
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
AZALIA_ENDPOINT_REG_DATA, reg_data);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
reg_index, reg_data);
}
static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = 0;
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
reg_index, value);
return value;
}
static bool is_audio_format_supported(
const struct audio_info *audio_info,
enum audio_format_code audio_format_code,
uint32_t *format_index)
{
uint32_t index;
uint32_t max_channe_index = 0;
bool found = false;
if (audio_info == NULL)
return found;
/* pass through whole array */
for (index = 0; index < audio_info->mode_count; index++) {
if (audio_info->modes[index].format_code == audio_format_code) {
if (found) {
/* format has multiply entries, choose one with
* highst number of channels */
if (audio_info->modes[index].channel_count >
audio_info->modes[max_channe_index].channel_count) {
max_channe_index = index;
}
} else {
/* format found, save it's index */
found = true;
max_channe_index = index;
}
}
}
/* return index */
if (found && format_index != NULL)
*format_index = max_channe_index;
return found;
}
/*For HDMI, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_hdmi(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
uint32_t samples;
uint32_t h_blank;
bool limit_freq_to_48_khz = false;
bool limit_freq_to_88_2_khz = false;
bool limit_freq_to_96_khz = false;
bool limit_freq_to_174_4_khz = false;
/* For two channels supported return whatever sink support,unmodified*/
if (channel_count > 2) {
/* Based on HDMI spec 1.3 Table 7.5 */
if ((crtc_info->requested_pixel_clock <= 27000) &&
(crtc_info->v_active <= 576) &&
!(crtc_info->interlaced) &&
!(crtc_info->pixel_repetition == 2 ||
crtc_info->pixel_repetition == 4)) {
limit_freq_to_48_khz = true;
} else if ((crtc_info->requested_pixel_clock <= 27000) &&
(crtc_info->v_active <= 576) &&
(crtc_info->interlaced) &&
(crtc_info->pixel_repetition == 2)) {
limit_freq_to_88_2_khz = true;
} else if ((crtc_info->requested_pixel_clock <= 54000) &&
(crtc_info->v_active <= 576) &&
!(crtc_info->interlaced)) {
limit_freq_to_174_4_khz = true;
}
}
/* Also do some calculation for the available Audio Bandwidth for the
* 8 ch (i.e. for the Layout 1 => ch > 2)
*/
h_blank = crtc_info->h_total - crtc_info->h_active;
if (crtc_info->pixel_repetition)
h_blank *= crtc_info->pixel_repetition;
/*based on HDMI spec 1.3 Table 7.5 */
h_blank -= 58;
/*for Control Period */
h_blank -= 16;
samples = h_blank * 10;
/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
* of Audio samples per line multiplied by 10 - Layout 1)
*/
samples /= 32;
samples *= crtc_info->v_active;
/*Number of samples multiplied by 10, per second */
samples *= crtc_info->refresh_rate;
/*Number of Audio samples per second */
samples /= 10;
/* @todo do it after deep color is implemented
* 8xx - deep color bandwidth scaling
* Extra bandwidth is avaliable in deep color b/c link runs faster than
* pixel rate. This has the effect of allowing more tmds characters to
* be transmitted during blank
*/
switch (crtc_info->color_depth) {
case COLOR_DEPTH_888:
samples *= 4;
break;
case COLOR_DEPTH_101010:
samples *= 5;
break;
case COLOR_DEPTH_121212:
samples *= 6;
break;
default:
samples *= 4;
break;
}
samples /= 4;
/*check limitation*/
if (samples < 88200)
limit_freq_to_48_khz = true;
else if (samples < 96000)
limit_freq_to_88_2_khz = true;
else if (samples < 176400)
limit_freq_to_96_khz = true;
else if (samples < 192000)
limit_freq_to_174_4_khz = true;
if (sample_rates != NULL) {
/* limit frequencies */
if (limit_freq_to_174_4_khz)
sample_rates->rate.RATE_192 = 0;
if (limit_freq_to_96_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
}
if (limit_freq_to_88_2_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
sample_rates->rate.RATE_96 = 0;
}
if (limit_freq_to_48_khz) {
sample_rates->rate.RATE_192 = 0;
sample_rates->rate.RATE_176_4 = 0;
sample_rates->rate.RATE_96 = 0;
sample_rates->rate.RATE_88_2 = 0;
}
}
}
/*For DP SST, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_dpsst(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
/* do nothing */
}
/*For DP MST, calculate if specified sample rates can fit into a given timing */
static void check_audio_bandwidth_dpmst(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
union audio_sample_rates *sample_rates)
{
/* do nothing */
}
static void check_audio_bandwidth(
const struct audio_crtc_info *crtc_info,
uint32_t channel_count,
enum signal_type signal,
union audio_sample_rates *sample_rates)
{
switch (signal) {
case SIGNAL_TYPE_HDMI_TYPE_A:
check_audio_bandwidth_hdmi(
crtc_info, channel_count, sample_rates);
break;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT:
check_audio_bandwidth_dpsst(
crtc_info, channel_count, sample_rates);
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
check_audio_bandwidth_dpmst(
crtc_info, channel_count, sample_rates);
break;
default:
break;
}
}
/* expose/not expose HBR capability to Audio driver */
static void set_high_bit_rate_capable(
struct audio *audio,
bool capable)
{
uint32_t value = 0;
/* set high bit rate audio capable*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
set_reg_field_value(value, capable,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
HBR_CAPABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
}
/* set video latency in in ms/2+1 */
static void set_video_latency(
struct audio *audio,
int latency_in_ms)
{
uint32_t value = 0;
if ((latency_in_ms < 0) || (latency_in_ms > 255))
return;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
set_reg_field_value(value, latency_in_ms,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
VIDEO_LIPSYNC);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
value);
}
/* set audio latency in in ms/2+1 */
static void set_audio_latency(
struct audio *audio,
int latency_in_ms)
{
uint32_t value = 0;
if (latency_in_ms < 0)
latency_in_ms = 0;
if (latency_in_ms > 255)
latency_in_ms = 255;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
set_reg_field_value(value, latency_in_ms,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
AUDIO_LIPSYNC);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
value);
}
void dce_aud_az_enable(struct audio *audio)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
audio->inst, value);
}
void dce_aud_az_disable(struct audio *audio)
{
uint32_t value;
struct dce_audio *aud = DCE_AUD(audio);
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 0,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
AUDIO_ENABLED);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
set_reg_field_value(value, 0,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
audio->inst, value);
}
void dce_aud_az_configure(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_info *audio_info)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
uint32_t value;
uint32_t field = 0;
enum audio_format_code audio_format_code;
uint32_t format_index;
uint32_t index;
bool is_ac3_supported = false;
union audio_sample_rates sample_rate;
uint32_t strlen = 0;
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
/* Speaker Allocation */
/*
uint32_t value;
uint32_t field = 0;*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
set_reg_field_value(value,
speakers,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
SPEAKER_ALLOCATION);
/* LFE_PLAYBACK_LEVEL = LFEPBL
* LFEPBL = 0 : Unknown or refer to other information
* LFEPBL = 1 : 0dB playback
* LFEPBL = 2 : +10dB playback
* LFE_BL = 3 : Reserved
*/
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
LFE_PLAYBACK_LEVEL);
/* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
* why are we writing to it? DCE8 does not write this */
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
HDMI_CONNECTION);
set_reg_field_value(value,
0,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
DP_CONNECTION);
field = get_reg_field_value(value,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
EXTRA_CONNECTION_INFO);
field &= ~0x1;
set_reg_field_value(value,
field,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
EXTRA_CONNECTION_INFO);
/* set audio for output signal */
switch (signal) {
case SIGNAL_TYPE_HDMI_TYPE_A:
set_reg_field_value(value,
1,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
HDMI_CONNECTION);
break;
case SIGNAL_TYPE_EDP:
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
set_reg_field_value(value,
1,
AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
DP_CONNECTION);
break;
default:
BREAK_TO_DEBUGGER();
break;
}
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
/* Audio Descriptors */
/* pass through all formats */
for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
format_index++) {
audio_format_code =
(AUDIO_FORMAT_CODE_FIRST + format_index);
/* those are unsupported, skip programming */
if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
audio_format_code == AUDIO_FORMAT_CODE_DST)
continue;
value = 0;
/* check if supported */
if (is_audio_format_supported(
audio_info, audio_format_code, &index)) {
const struct audio_mode *audio_mode =
&audio_info->modes[index];
union audio_sample_rates sample_rates =
audio_mode->sample_rates;
uint8_t byte2 = audio_mode->max_bit_rate;
/* adjust specific properties */
switch (audio_format_code) {
case AUDIO_FORMAT_CODE_LINEARPCM: {
check_audio_bandwidth(
crtc_info,
audio_mode->channel_count,
signal,
&sample_rates);
byte2 = audio_mode->sample_size;
set_reg_field_value(value,
sample_rates.all,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
SUPPORTED_FREQUENCIES_STEREO);
}
break;
case AUDIO_FORMAT_CODE_AC3:
is_ac3_supported = true;
break;
case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
case AUDIO_FORMAT_CODE_DTS_HD:
case AUDIO_FORMAT_CODE_MAT_MLP:
case AUDIO_FORMAT_CODE_DST:
case AUDIO_FORMAT_CODE_WMAPRO:
byte2 = audio_mode->vendor_specific;
break;
default:
break;
}
/* fill audio format data */
set_reg_field_value(value,
audio_mode->channel_count - 1,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
MAX_CHANNELS);
set_reg_field_value(value,
sample_rates.all,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
SUPPORTED_FREQUENCIES);
set_reg_field_value(value,
byte2,
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
DESCRIPTOR_BYTE_2);
} /* if */
AZ_REG_WRITE(
AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
value);
} /* for */
if (is_ac3_supported)
/* todo: this reg global. why program global register? */
REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
0x05);
/* check for 192khz/8-Ch support for HBR requirements */
sample_rate.all = 0;
sample_rate.rate.RATE_192 = 1;
check_audio_bandwidth(
crtc_info,
8,
signal,
&sample_rate);
set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
/* Audio and Video Lipsync */
set_video_latency(audio, audio_info->video_latency);
set_audio_latency(audio, audio_info->audio_latency);
value = 0;
set_reg_field_value(value, audio_info->manufacture_id,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
MANUFACTURER_ID);
set_reg_field_value(value, audio_info->product_id,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
PRODUCT_ID);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
value);
value = 0;
/*get display name string length */
while (audio_info->display_name[strlen++] != '\0') {
if (strlen >=
MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
break;
}
set_reg_field_value(value, strlen,
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
SINK_DESCRIPTION_LEN);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
/*
*write the port ID:
*PORT_ID0 = display index
*PORT_ID1 = 16bit BDF
*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
*/
value = 0;
set_reg_field_value(value, audio_info->port_id[0],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
PORT_ID0);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
value = 0;
set_reg_field_value(value, audio_info->port_id[1],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
PORT_ID1);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
/*write the 18 char monitor string */
value = 0;
set_reg_field_value(value, audio_info->display_name[0],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION0);
set_reg_field_value(value, audio_info->display_name[1],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION1);
set_reg_field_value(value, audio_info->display_name[2],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION2);
set_reg_field_value(value, audio_info->display_name[3],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
DESCRIPTION3);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[4],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION4);
set_reg_field_value(value, audio_info->display_name[5],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION5);
set_reg_field_value(value, audio_info->display_name[6],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION6);
set_reg_field_value(value, audio_info->display_name[7],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
DESCRIPTION7);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[8],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION8);
set_reg_field_value(value, audio_info->display_name[9],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION9);
set_reg_field_value(value, audio_info->display_name[10],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION10);
set_reg_field_value(value, audio_info->display_name[11],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
DESCRIPTION11);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[12],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION12);
set_reg_field_value(value, audio_info->display_name[13],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION13);
set_reg_field_value(value, audio_info->display_name[14],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION14);
set_reg_field_value(value, audio_info->display_name[15],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
DESCRIPTION15);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
value = 0;
set_reg_field_value(value, audio_info->display_name[16],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
DESCRIPTION16);
set_reg_field_value(value, audio_info->display_name[17],
AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
DESCRIPTION17);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
}
/*
* todo: wall clk related functionality probably belong to clock_src.
*/
/* search pixel clock value for Azalia HDMI Audio */
static void get_azalia_clock_info_hdmi(
uint32_t crtc_pixel_clock_in_khz,
uint32_t actual_pixel_clock_in_khz,
struct azalia_clock_info *azalia_clock_info)
{
/* audio_dto_phase= 24 * 10,000;
* 24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase =
24 * 10000;
/* audio_dto_module = PCLKFrequency * 10,000;
* [khz] -> [100Hz] */
azalia_clock_info->audio_dto_module =
actual_pixel_clock_in_khz * 10;
}
static void get_azalia_clock_info_dp(
uint32_t requested_pixel_clock_in_khz,
const struct audio_pll_info *pll_info,
struct azalia_clock_info *azalia_clock_info)
{
/* Reported dpDtoSourceClockInkhz value for
* DCE8 already adjusted for SS, do not need any
* adjustment here anymore
*/
/*audio_dto_phase = 24 * 10,000;
* 24MHz in [100Hz] units */
azalia_clock_info->audio_dto_phase = 24 * 10000;
/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
* [khz] ->[100Hz] */
azalia_clock_info->audio_dto_module =
pll_info->dp_dto_source_clock_in_khz * 10;
}
void dce_aud_wall_dto_setup(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,
const struct audio_pll_info *pll_info)
{
struct dce_audio *aud = DCE_AUD(audio);
struct azalia_clock_info clock_info = { 0 };
if (dc_is_hdmi_signal(signal)) {
uint32_t src_sel;
/*DTO0 Programming goal:
-generate 24MHz, 128*Fs from 24MHz
-use DTO0 when an active HDMI port is connected
(optionally a DP is connected) */
/* calculate DTO settings */
get_azalia_clock_info_hdmi(
crtc_info->requested_pixel_clock,
crtc_info->calculated_pixel_clock,
&clock_info);
dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
"\n%s:Input::requested_pixel_clock = %d"\
"calculated_pixel_clock =%d\n"\
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
crtc_info->requested_pixel_clock,\
crtc_info->calculated_pixel_clock,\
clock_info.audio_dto_module,\
clock_info.audio_dto_phase);
/* On TN/SI, Program DTO source select and DTO select before
programming DTO modulo and DTO phase. These bits must be
programmed first, otherwise there will be no HDMI audio at boot
up. This is a HW sequence change (different from old ASICs).
Caution when changing this programming sequence.
HDMI enabled, using DTO0
program master CRTC for DTO0 */
src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
DCCG_AUDIO_DTO_SEL, 0);
/* module */
REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
} else {
/*DTO1 Programming goal:
-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-default is to used DTO1, and switch to DTO0 when an audio
master HDMI port is connected
-use as default for DP
calculate DTO settings */
get_azalia_clock_info_dp(
crtc_info->requested_pixel_clock,
pll_info,
&clock_info);
/* Program DTO select before programming DTO modulo and DTO
phase. default to use DTO1 */
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO_SEL, 1);
/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
* Select 512fs for DP TODO: web register definition
* does not match register header file
* DCE11 version it's commented out while DCE8 it's set to 1
*/
/* module */
REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
/* phase */
REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
}
}
static bool dce_aud_endpoint_valid(struct audio *audio)
{
uint32_t value;
uint32_t port_connectivity;
value = AZ_REG_READ(
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
port_connectivity = get_reg_field_value(value,
AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
PORT_CONNECTIVITY);
return !(port_connectivity == 1);
}
/* initialize HW state */
void dce_aud_hw_init(
struct audio *audio)
{
uint32_t value;
struct dce_audio *aud = DCE_AUD(audio);
/* we only need to program the following registers once, so we only do
it for the inst 0*/
if (audio->inst != 0)
return;
/* Suport R5 - 32khz
* Suport R6 - 44.1khz
* Suport R7 - 48khz
*/
/*disable clock gating before write to endpoint register*/
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
CLOCK_GATING_DISABLE);
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
AUDIO_RATE_CAPABILITIES, 0x70);
/*Keep alive bit to verify HW block in BU. */
REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
CLKSTOP, 1,
EPSS, 1);
}
static const struct audio_funcs funcs = {
.endpoint_valid = dce_aud_endpoint_valid,
.hw_init = dce_aud_hw_init,
.wall_dto_setup = dce_aud_wall_dto_setup,
.az_enable = dce_aud_az_enable,
.az_disable = dce_aud_az_disable,
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
};
void dce_aud_destroy(struct audio **audio)
{
struct dce_audio *aud = DCE_AUD(*audio);
kfree(aud);
*audio = NULL;
}
struct audio *dce_audio_create(
struct dc_context *ctx,
unsigned int inst,
const struct dce_audio_registers *reg,
const struct dce_audio_shift *shifts,
const struct dce_aduio_mask *masks
)
{
struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
if (audio == NULL) {
ASSERT_CRITICAL(audio);
return NULL;
}
audio->base.ctx = ctx;
audio->base.inst = inst;
audio->base.funcs = &funcs;
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
return &audio->base;
}

Some files were not shown because too many files have changed in this diff Show More