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drm/i915: Export the generic, not arch specific, intel_update_watermarks() 

Rather than export every single architecture specific update_wm, just
export the wrapper around the display vtable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson 2012-04-14 21:56:08 +01:00 committed by Daniel Vetter
parent fc6826d1dc
commit f681fa235f
3 changed files with 5 additions and 6 deletions
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5
drivers/gpu/drm/i915/intel_display.c
View File

@ -45,7 +45,6 @@
#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
bool intel_pipe_has_type(struct drm_crtc *crtc, int type); bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static void intel_update_watermarks(struct drm_device *dev);
static void intel_increase_pllclock(struct drm_crtc *crtc); static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
@ -4820,7 +4819,7 @@ static void ironlake_update_wm(struct drm_device *dev)
*/ */
} }
void sandybridge_update_wm(struct drm_device *dev) static void sandybridge_update_wm(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
@ -5125,7 +5124,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
* We don't use the sprite, so we can ignore that. And on Crestline we have * We don't use the sprite, so we can ignore that. And on Crestline we have
* to set the non-SR watermarks to 8. * to set the non-SR watermarks to 8.
*/ */
static void intel_update_watermarks(struct drm_device *dev) void intel_update_watermarks(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -422,7 +422,7 @@ extern void intel_write_eld(struct drm_encoder *encoder,
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
/* For use by IVB LP watermark workaround in intel_sprite.c */ /* For use by IVB LP watermark workaround in intel_sprite.c */
extern void sandybridge_update_wm(struct drm_device *dev); extern void intel_update_watermarks(struct drm_device *dev);
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
uint32_t sprite_width, uint32_t sprite_width,
int pixel_size); int pixel_size);

4
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -112,13 +112,13 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
*/ */
if (crtc_w != src_w || crtc_h != src_h) { if (crtc_w != src_w || crtc_h != src_h) {
dev_priv->sprite_scaling_enabled = true; dev_priv->sprite_scaling_enabled = true;
sandybridge_update_wm(dev); intel_update_watermarks(dev);
intel_wait_for_vblank(dev, pipe); intel_wait_for_vblank(dev, pipe);
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
} else { } else {
dev_priv->sprite_scaling_enabled = false; dev_priv->sprite_scaling_enabled = false;
/* potentially re-enable LP watermarks */ /* potentially re-enable LP watermarks */
sandybridge_update_wm(dev); intel_update_watermarks(dev);
} }
I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);