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mmc: sdhci-cadence: fix PHY write 

Accordingly to Cadence documentation, PHY write procedure is:

1. Software sets the PHY Register Address (HRS04[5:0]) and the
   PHY Write Data (HRS04[15:8]) fields.
2. Software sets the PHY Write Transaction Request (HRS04[24]) field to 1.
3. Software waits as the PHY Write Transaction Acknowledge (HRS04[26])
   field is equal to 0.
4. Hardware performs the write transaction to PHY register where
   HRS04[15:8] is a data written to register under HRS04[5:0] address.
5. Hardware sets the PHY Transaction Acknowledge (HRS04[26]) to 1 when
   transaction is completed.
6. Software clears the PHY Write Transaction Request (HRS04[24]) to 1
   after noticing that the PHY Write Transaction Acknowledge (HRS04[26])
   field is equal to 1.
7. Software waits for the PHY Acknowledge Register (HRS04[26]) field is
   equal to 0.

Add missing steps 3 and 7. Lack of these steps causes
integrity errors detested by hardware.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Link: https://lore.kernel.org/r/20200525074053.7309-1-vladimir.kondratiev@intel.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Vladimir Kondratiev 2020-05-25 10:40:53 +03:00 committed by Ulf Hansson
parent 798dd3c311
commit f6bc8186a5
1 changed files with 9 additions and 1 deletions
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10
drivers/mmc/host/sdhci-cadence.c
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@ -97,6 +97,11 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
u32 tmp;
int ret;
ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
0, 10);
if (ret)
return ret;
tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
writel(tmp, reg);
@ -111,7 +116,10 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
tmp &= ~SDHCI_CDNS_HRS04_WR;
writel(tmp, reg);
return 0;
ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
0, 10);
return ret;
}
static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)