mirror of https://gitee.com/openkylin/linux.git
drm/i915: Set M2_N2 registers during mode set
For Gen < 8, set M2_N2 registers on every mode set. This is required to make sure M2_N2 registers are set during boot, resume from sleep for cross- checking the state. The register is set only if DRRS is supported. v2: Patch rebased v3: Daniel's review comments - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to track drrs support v4: Jesse's review comments - Made changes to set m2_n2 in intel_dp_set_m_n() Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -91,11 +91,11 @@ static int intel_framebuffer_init(struct drm_device *dev,
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struct intel_framebuffer *ifb,
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struct drm_mode_fb_cmd2 *mode_cmd,
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struct drm_i915_gem_object *obj);
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static void intel_dp_set_m_n(struct intel_crtc *crtc);
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static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
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static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
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static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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struct intel_link_m_n *m_n);
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struct intel_link_m_n *m_n,
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struct intel_link_m_n *m2_n2);
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static void ironlake_set_pipeconf(struct drm_crtc *crtc);
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static void haswell_set_pipeconf(struct drm_crtc *crtc);
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static void intel_set_pipe_csc(struct drm_crtc *crtc);
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@ -3980,7 +3980,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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if (intel_crtc->config.has_pch_encoder) {
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intel_cpu_transcoder_set_m_n(intel_crtc,
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&intel_crtc->config.fdi_m_n);
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&intel_crtc->config.fdi_m_n, NULL);
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}
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ironlake_set_pipeconf(crtc);
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@ -4093,7 +4093,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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if (intel_crtc->config.has_pch_encoder) {
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intel_cpu_transcoder_set_m_n(intel_crtc,
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&intel_crtc->config.fdi_m_n);
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&intel_crtc->config.fdi_m_n, NULL);
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}
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haswell_set_pipeconf(crtc);
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@ -5509,7 +5509,8 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
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}
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static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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struct intel_link_m_n *m_n)
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struct intel_link_m_n *m_n,
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struct intel_link_m_n *m2_n2)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -5521,6 +5522,18 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
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I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
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I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
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/* M2_N2 registers to be set only for gen < 8 (M2_N2 available
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* for gen < 8) and if DRRS is supported (to make sure the
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* registers are not unnecessarily accessed).
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*/
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if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
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crtc->config.has_drrs) {
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I915_WRITE(PIPE_DATA_M2(transcoder),
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TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
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I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
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I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
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I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
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}
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} else {
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I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
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I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
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@ -5529,12 +5542,13 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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}
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}
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static void intel_dp_set_m_n(struct intel_crtc *crtc)
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void intel_dp_set_m_n(struct intel_crtc *crtc)
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{
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if (crtc->config.has_pch_encoder)
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intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
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else
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intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
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intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
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&crtc->config.dp_m2_n2);
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}
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static void vlv_update_pll(struct intel_crtc *crtc)
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@ -828,20 +828,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
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}
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}
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static void
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intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum transcoder transcoder = crtc->config.cpu_transcoder;
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I915_WRITE(PIPE_DATA_M2(transcoder),
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TU_SIZE(m_n->tu) | m_n->gmch_m);
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I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
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I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
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I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
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}
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bool
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intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_config *pipe_config)
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@ -867,6 +853,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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pipe_config->has_pch_encoder = true;
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pipe_config->has_dp_encoder = true;
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pipe_config->has_drrs = false;
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pipe_config->has_audio = intel_dp->has_audio;
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if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
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@ -970,6 +957,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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if (intel_connector->panel.downclock_mode != NULL &&
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intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
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pipe_config->has_drrs = true;
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intel_link_compute_m_n(bpp, lane_count,
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intel_connector->panel.downclock_mode->clock,
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pipe_config->port_clock,
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@ -4389,7 +4377,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
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val = I915_READ(reg);
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if (index > DRRS_HIGH_RR) {
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val |= PIPECONF_EDP_RR_MODE_SWITCH;
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intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
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intel_dp_set_m_n(intel_crtc);
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} else {
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val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
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}
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@ -324,6 +324,7 @@ struct intel_crtc_config {
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/* m2_n2 for eDP downclock */
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struct intel_link_m_n dp_m2_n2;
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bool has_drrs;
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/*
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* Frequence the dpll for the port should run at. Differs from the
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@ -877,6 +878,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
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void hsw_disable_pc8(struct drm_i915_private *dev_priv);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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struct intel_crtc_config *pipe_config);
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void intel_dp_set_m_n(struct intel_crtc *crtc);
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int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
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void
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ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
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@ -892,7 +894,6 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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int intel_format_to_fourcc(int format);
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void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
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/* intel_dp.c */
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void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
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bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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