mirror of https://gitee.com/openkylin/linux.git
Merge tag 'drm-fixes-5.4-2019-11-20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
drm-fixes-5.4-2019-11-20: amdgpu: - Remove experimental flag for navi14 - Fix confusing power message failures on older VI parts - Hang fix for gfxoff when using the read register interface - Two stability regression fixes for Raven Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191120235130.23755-1-alexander.deucher@amd.com
This commit is contained in:
commit
f824c1b35a
drivers/gpu/drm/amd
amdgpu
display/amdgpu_dm
powerplay
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@ -511,7 +511,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
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* Also, don't allow GTT domain if the BO doens't have USWC falg set.
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*/
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if (adev->asic_type >= CHIP_CARRIZO &&
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adev->asic_type <= CHIP_RAVEN &&
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adev->asic_type < CHIP_RAVEN &&
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(adev->flags & AMD_IS_APU) &&
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(bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
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amdgpu_bo_support_uswc(bo_flags) &&
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@ -1013,10 +1013,10 @@ static const struct pci_device_id pciidlist[] = {
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{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
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{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
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/* Navi14 */
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{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
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{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
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{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
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{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
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{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
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{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
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{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
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{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
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/* Renoir */
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{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
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@ -649,15 +649,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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return -ENOMEM;
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alloc_size = info->read_mmr_reg.count * sizeof(*regs);
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for (i = 0; i < info->read_mmr_reg.count; i++)
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amdgpu_gfx_off_ctrl(adev, false);
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for (i = 0; i < info->read_mmr_reg.count; i++) {
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if (amdgpu_asic_read_register(adev, se_num, sh_num,
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info->read_mmr_reg.dword_offset + i,
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®s[i])) {
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DRM_DEBUG_KMS("unallowed offset %#x\n",
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info->read_mmr_reg.dword_offset + i);
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kfree(regs);
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amdgpu_gfx_off_ctrl(adev, true);
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return -EFAULT;
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}
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}
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amdgpu_gfx_off_ctrl(adev, true);
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n = copy_to_user(out, regs, min(size, alloc_size));
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kfree(regs);
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return n ? -EFAULT : 0;
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@ -1038,8 +1038,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
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case CHIP_VEGA20:
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break;
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case CHIP_RAVEN:
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if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
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&&((adev->gfx.rlc_fw_version != 106 &&
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/* Disable GFXOFF on original raven. There are combinations
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* of sbios and platforms that are not stable.
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*/
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if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
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adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
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else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
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&&((adev->gfx.rlc_fw_version != 106 &&
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adev->gfx.rlc_fw_version < 531) ||
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(adev->gfx.rlc_fw_version == 53815) ||
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(adev->gfx.rlc_feature_version < 1) ||
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@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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*/
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if (adev->flags & AMD_IS_APU &&
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adev->asic_type >= CHIP_CARRIZO &&
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adev->asic_type <= CHIP_RAVEN)
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adev->asic_type < CHIP_RAVEN)
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init_data.flags.gpu_vm_support = true;
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if (amdgpu_dc_feature_mask & DC_FBC_MASK)
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@ -3478,18 +3478,31 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
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static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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int i;
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u32 tmp = 0;
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if (!query)
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return -EINVAL;
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
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tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
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*query = tmp;
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/*
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* PPSMC_MSG_GetCurrPkgPwr is not supported on:
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* - Hawaii
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* - Bonaire
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* - Fiji
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* - Tonga
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*/
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if ((adev->asic_type != CHIP_HAWAII) &&
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(adev->asic_type != CHIP_BONAIRE) &&
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(adev->asic_type != CHIP_FIJI) &&
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(adev->asic_type != CHIP_TONGA)) {
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smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
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tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
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*query = tmp;
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if (tmp != 0)
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return 0;
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if (tmp != 0)
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return 0;
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}
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
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@ -759,6 +759,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
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case SMU_UCLK:
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case SMU_DCEFCLK:
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case SMU_FCLK:
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/* There is only 2 levels for fine grained DPM */
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if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
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soft_max_level = (soft_max_level >= 1 ? 1 : 0);
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soft_min_level = (soft_min_level >= 1 ? 1 : 0);
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}
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ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
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if (ret)
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return size;
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