mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu/gfx: Improvement on EDC GPR workarounds
SPI limits total CS waves in flight per SE to no more than 32 * num_cu and we need to stuff 40 waves on a CU to completely clean the SGPR. This is accomplished in the WR by cleaning the SE in two steps, half of the CU per step. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu
Alex Deucher
parent
79c4c8ea91
commit
f83f5a1e11
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@ -3938,24 +3938,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
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};
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static const struct soc15_reg_entry sgpr_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
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static const struct soc15_reg_entry sgpr1_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
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};
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static const struct soc15_reg_entry sgpr2_init_regs[] = {
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
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{ SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
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};
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@ -4065,7 +4078,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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total_size =
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((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
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total_size +=
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((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
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((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
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total_size +=
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((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
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total_size = ALIGN(total_size, 256);
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vgpr_offset = total_size;
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total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
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@ -4108,7 +4123,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 256; /* x */
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ib.ptr[ib.length_dw++] = 0x40*2; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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@ -4118,13 +4133,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* SGPR */
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/* SGPR1 */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(sgpr_init_regs); i++) {
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for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i++) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr_init_regs[i])
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ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = sgpr_init_regs[i].reg_value;
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ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
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@ -4136,7 +4151,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 256; /* x */
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ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
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/* write CS partial flush packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
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ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
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/* SGPR2 */
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/* write the register state for the compute dispatch */
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for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i++) {
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
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ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
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}
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/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
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gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
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ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
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- PACKET3_SET_SH_REG_START;
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ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
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ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
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/* write dispatch packet */
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ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
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ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
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ib.ptr[ib.length_dw++] = 1; /* y */
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ib.ptr[ib.length_dw++] = 1; /* z */
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ib.ptr[ib.length_dw++] =
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