mirror of https://gitee.com/openkylin/linux.git
rtl8187: change rtl8187_dev.c to support RTL8187B (part 1)
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Herton Ronaldo Krzesinski <herton@mandriva.com.br> Signed-off-by: Hin-Tak Leung <htl10@users.sourceforge.net> Signed-off-by: Pavel Roskin <proski@gnu.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Hin-Tak Leung
John W. Linville
parent
e7d414ff21
commit
f8a08c3426
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@ -27,19 +27,21 @@
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MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
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MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
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MODULE_DESCRIPTION("RTL8187 USB wireless driver");
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MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
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MODULE_LICENSE("GPL");
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static struct usb_device_id rtl8187_table[] __devinitdata = {
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/* Realtek */
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{USB_DEVICE(0x0bda, 0x8187)},
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{USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
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{USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
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{USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
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/* Netgear */
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{USB_DEVICE(0x0846, 0x6100)},
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{USB_DEVICE(0x0846, 0x6a00)},
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{USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
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{USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
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/* HP */
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{USB_DEVICE(0x03f0, 0xca02)},
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{USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
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/* Sitecom */
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{USB_DEVICE(0x0df6, 0x000d)},
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{USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
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{}
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};
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@ -318,29 +320,12 @@ static int rtl8187_init_urbs(struct ieee80211_hw *dev)
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return 0;
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}
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static int rtl8187_init_hw(struct ieee80211_hw *dev)
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static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
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{
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struct rtl8187_priv *priv = dev->priv;
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u8 reg;
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int i;
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/* reset */
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
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msleep(200);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
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msleep(200);
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reg = rtl818x_ioread8(priv, &priv->map->CMD);
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reg &= (1 << 1);
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reg |= RTL818X_CMD_RESET;
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@ -376,12 +361,48 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
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return -ETIMEDOUT;
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}
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
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return 0;
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}
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static int rtl8187_init_hw(struct ieee80211_hw *dev)
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{
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struct rtl8187_priv *priv = dev->priv;
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u8 reg;
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int res;
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/* reset */
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
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RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
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~RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
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msleep(200);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
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rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
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msleep(200);
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res = rtl8187_cmd_reset(dev);
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if (res)
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return res;
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3,
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reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3,
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reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
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/* setup card */
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@ -426,9 +447,11 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
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rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
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rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
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rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_CONFIG);
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
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msleep(100);
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@ -445,16 +468,198 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
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return 0;
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}
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static const u8 rtl8187b_reg_table[][3] = {
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{0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
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{0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
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{0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
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{0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
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{0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
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{0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
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{0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
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{0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
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{0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
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{0xF7, 0x07, 1}, {0xF8, 0x08, 1},
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{0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
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{0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
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{0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
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{0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
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{0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
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{0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
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{0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
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{0x73, 0x9A, 2},
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{0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
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{0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
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{0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
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{0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
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{0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
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{0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
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{0x8E, 0x08, 0}, {0x8F, 0x00, 0}
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};
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static int rtl8187b_init_hw(struct ieee80211_hw *dev)
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{
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struct rtl8187_priv *priv = dev->priv;
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int res, i;
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u8 reg;
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, 0x727f3f52);
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rtl818x_iowrite32(priv, &priv->map->ANAPARAM, 0x45090658);
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rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, 0);
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rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
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reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
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rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
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rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_NORMAL);
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res = rtl8187_cmd_reset(dev);
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if (res)
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return res;
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rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
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reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
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reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
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rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
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reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
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reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
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RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
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rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
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reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
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reg |= RTL818X_RATE_FALLBACK_ENABLE;
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rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
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rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
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rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
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rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
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for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
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rtl818x_iowrite8_idx(priv,
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(u8 *)(uintptr_t)
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(rtl8187b_reg_table[i][0] | 0xFF00),
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rtl8187b_reg_table[i][1],
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rtl8187b_reg_table[i][2]);
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}
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rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
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rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
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rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
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rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
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rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
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rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_CONFIG);
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reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
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reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
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rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
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rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
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RTL818X_EEPROM_CMD_NORMAL);
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rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
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rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
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rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
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msleep(1100);
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priv->rf->init(dev);
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reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
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rtl818x_iowrite8(priv, &priv->map->CMD, reg);
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rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
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rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
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rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
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rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
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rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
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rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
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rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
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rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
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reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
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rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
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rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
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rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
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rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
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rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
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rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
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rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
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rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
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return 0;
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}
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static int rtl8187_start(struct ieee80211_hw *dev)
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{
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struct rtl8187_priv *priv = dev->priv;
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u32 reg;
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int ret;
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ret = rtl8187_init_hw(dev);
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ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
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rtl8187b_init_hw(dev);
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if (ret)
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return ret;
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if (priv->is_rtl8187b) {
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reg = RTL818X_RX_CONF_MGMT |
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RTL818X_RX_CONF_DATA |
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RTL818X_RX_CONF_BROADCAST |
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RTL818X_RX_CONF_NICMAC |
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RTL818X_RX_CONF_BSSID |
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(7 << 13 /* RX FIFO threshold NONE */) |
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(7 << 10 /* MAX RX DMA */) |
|
||||
RTL818X_RX_CONF_RX_AUTORESETPHY |
|
||||
RTL818X_RX_CONF_ONLYERLPKT |
|
||||
RTL818X_RX_CONF_MULTICAST;
|
||||
priv->rx_conf = reg;
|
||||
rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
|
||||
|
||||
rtl818x_iowrite32(priv, &priv->map->TX_CONF,
|
||||
RTL818X_TX_CONF_HW_SEQNUM |
|
||||
RTL818X_TX_CONF_DISREQQSIZE |
|
||||
(7 << 8 /* short retry limit */) |
|
||||
(7 << 0 /* long retry limit */) |
|
||||
(7 << 21 /* MAX TX DMA */));
|
||||
rtl8187_init_urbs(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
|
||||
|
||||
rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue