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drm/msm/a6xx: Fix PDC register overlap 

The current design greedily takes a big chunk of the PDC
register space instead of just the GPU specific sections
which conflicts with other drivers and generally makes
a mess of things.

Furthermore we only need to map the GPU PDC sections
just once during init so map the memory inside the function
that uses it and adjust the pointers and register offsets
accordingly.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Jordan Crouse 2018-08-08 16:39:38 -06:00 committed by Rob Clark
parent 06feed5618
commit f8fc924e08
3 changed files with 78 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
drivers/gpu/drm/msm/adreno/a6xx.xml.h
View File

@ -1981,59 +1981,59 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00018430
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00021140
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00021148
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00021540
#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00021541
#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00021542
#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00021543
#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00021544
#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00021545
#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00021572
#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00021573
#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00021574
#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00021575
#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00021576
#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00021577
#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000215a4
#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000215a5
#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000215a6
#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000215a7
#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000215a8
#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000215a9
#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000215d6
#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000215d7
#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000215d8
#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000215d9
#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000215da
#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000215db
#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x000a0000
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
#define REG_A6XX_X1_WINDOW_OFFSET 0x000088d4
#define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000

87
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@ -348,8 +348,23 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
}
static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
{
return msm_writel(value, ptr + (offset << 2));
}
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
const char *name);
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
{
struct platform_device *pdev = to_platform_device(gmu->dev);
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
if (!pdcptr || !seqptr)
goto err;
/* Disable SDE clock gating */
gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
@ -374,44 +389,48 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
/* Load PDC sequencer uCode for power up and power down sequence */
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
/* Set TCS commands used by PDC sequence for low power modes */
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
/* Setup GPU PDC */
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
pdc_write(gmu, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
/* ensure no writes happen before the uCode is fully written */
wmb();
err:
devm_iounmap(gmu->dev, pdcptr);
devm_iounmap(gmu->dev, seqptr);
}
/*
@ -1170,11 +1189,7 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
/* Map the GMU registers */
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
/* Map the GPU power domain controller registers */
gmu->pdc_mmio = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
if (IS_ERR(gmu->mmio) || IS_ERR(gmu->pdc_mmio))
if (IS_ERR(gmu->mmio))
goto err;
/* Get the HFI and GMU interrupts */

6
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
View File

@ -47,7 +47,6 @@ struct a6xx_gmu {
struct device *dev;
void * __iomem mmio;
void * __iomem pdc_mmio;
int hfi_irq;
int gmu_irq;
@ -89,11 +88,6 @@ static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
return msm_writel(value, gmu->mmio + (offset << 2));
}
static inline void pdc_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
return msm_writel(value, gmu->pdc_mmio + (offset << 2));
}
static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
{
u32 val = gmu_read(gmu, reg);