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qlcnic: Eliminate duplicate barriers on weakly-ordered archs 

Code includes wmb() followed by writel(). writel() already has a
barrier on some architectures like arm64.

This ends up CPU observing two barriers back to back before executing
the register write.

Since code already has an explicit barrier call, changing writel() to
writel_relaxed().

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: Manish Chopra <manish.chopra@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sinan Kaya 2018-03-25 10:39:16 -04:00 committed by David S. Miller
parent 3c95c56732
commit f9442ac498
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
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@ -478,7 +478,7 @@ irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
wmb();
/* clear the interrupt trigger control register */
writel(0, adapter->isr_int_vec);
writel_relaxed(0, adapter->isr_int_vec);
intr_val = readl(adapter->isr_int_vec);
do {
intr_val = readl(adapter->tgt_status_reg);